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ADSST-SALEM-3T
ADSST-218X COMMON-MODE PINS
Table 2.
Pin Name
No. of Pins
BG
1
BGH
1
BMS
1
BR
1
CMS
1
DMS
1
1
IOMS
PMS
1
RD
1
RESET
1
1
WR
IRQ2/
1
PF7
IRQL1/
1
PF6
IRQL0/
1
PF5
IRQE/
1
PF4
MODE A
1
PF0
MODE B
1
PF1
MODE C
1
PF2
MODE D
1
PF3
CLKIN, XTAL
2
CLKOUT
1
EZ-Port
9
FI, FO
FL0, FL1, FL2
3
GND
10
IRQ1:0
PWD
1
SPORT0
5
SPORT1
5
PWDACK
1
V
4
DDEXT
V
7
DDEXT
V
2
DDINT
V
4
DDINT
1
Interrupt/flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector
address when the pin is asserted, either by external devices or set as a programmable flag.
2
SPORT configuration determined by the DSP System Control register. Software configurable.
I/O
Function
O
Bus Grant Output
O
Bus Grant Hung Output
O
Byte Memory Select Output
I
Bus Request Input
O
Combined Memory Select Output
O
Data Memory Select Output
O
Memory Select Output
O
Program Memory Select Output
O
Memory Read Enable Output
I
Processor Reset Input
O
Memory Write Enable Output
I
Edge- or Level-Sensitive Interrupt Request
I/O
Programmable I/O Pin
I
Level-Sensitive Interrupt Requests
I/O
Programmable I/O Pin
I
Level-Sensitive Interrupt Requests
I/O
Programmable I/O Pin
I
Edge-Sensitive Interrupt Requests
I/O
Programmable I/O Pin
I
Mode Select Input−Checked only during RESET
I/O
Programmable I/O Pin during Normal Operation
I
Mode Select Input−Checked only during RESET
I/O
Programmable I/O Pin during Normal Operation
I
Mode Select Input−Checked only during RESET
I/O
Programmable I/O Pin during Normal Operation
I
Mode Select Input−Checked only during RESET
I/O
Programmable I/O Pin during Normal Operation
I
Clock or Quartz Crystal Input
O
Processor Clock Output
I/O
For Emulation Use
2
Flag In, Flag Out
O
Output Flags
I
Power and Ground
Edge- or Level-Sensitive Interrupts
I
Power-Down Control Input
I/O
Serial Port I/O Pins
I/O
Serial Port I/O Pins
O
Power-Down Control Output
I
External V
(2.5 V or 3.3 V) Power (LQFP)
DD
I
External V
(2.5 V or 3.3 V) Power (Mini-BGA)
DD
I
Internal V
(2.5 V) Power (LQFP)
DD
I
Internal V
(2.5 V) Power (Mini-BGA)
DD
Rev. 0 | Page 6 of 24
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