Pin Configuration And Pin Function Descriptions-Adsst-73360Lar; Pin Function Descriptions - Analog Devices ADSST-EM-3040 Manual

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS—ADSST-73360LAR

PIN FUNCTION DESCRIPTIONS

Table 9.
Pin No. Mnemonic
1 VINP2
2 VINN2
3 VINP1
4 VINN1
5 REFOUT
6 REFCAP
7 AVDD2
8 AGND2
9 DGND
10 DVDD
11 RESET
12 SCLK
13 MCLK
14 SDO
15 SDOFS
16 SDIFS
17 SDI
VINP2
VINN2
VINP1
VINN1
REFOUT
REFCAP
AVDD2
AGND2
DGND
DVDD
10
RESET
11
SCLK
12
MCLK
13
SDO
14
Figure 7. ADSST-73360LAR Pin Configuration—RW-28
Function
Analog Input to the Positive Terminal of Input Channel 2.
Analog Input to the Negative Terminal of Input Channel 2.
Analog Input to the Positive Terminal of Input Channel 1.
Analog Input to the Negative Terminal of Input Channel 1.
Buffered Output of the Internal Reference, which has a nominal value of 1.2 V.
Reference Voltage for ADCs. A bypass capacitor to AGND2 of 0.1 µF is required for the on-chip
reference. The capacitor should be fixed to this pin. The internal reference can be overdriven
by an external reference connected to this pin if required.
Analog Power Supply Connection.
Analog Ground/Substrate Connection.
Digital Ground/Substrate Connection.
Digital Power Supply Connection.
Active Low Reset Signal. This input resets the entire chip, resetting the control registers and
clearing the digital circuitry.
Output Serial Clock whose rate determines the serial transfer rate to/from the ADSST-
73360LAR. It is used to clock data or control information to and from the serial port (SPORT).
The frequency of SCLK is equal to the frequency of the master clock (MCLK) divided by an
integer number that is the product of the external master clock rate divider and the serial
clock rate divider.
Master Clock Input. MCLK is driven from an external clock signal.
Serial Data Output of the ADSST-73360LAR. Both data and control information may be output
on this pin and are clocked on the positive edge of SCLK. SDO is in three-state when no
information is being transmitted and when SE is low.
Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active
one SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the
positive edge of SCLK. SDOFS is in three-state when SE is low.
Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and it is valid one
SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative
edge of SCLK and is ignored when SE is low.
Serial Data Input of the ADSST-73360LAR. Both data and control information may be input on
this pin and are clocked on the negative edge of SCLK. SDI is ignored when SE is low.
Rev. 0 | Page 15 of 24
VINN3
1 28
VINP3
2 27
VINN4
3 26
TOP VIEW
(Not to Scale)
VINP4
4 25
VINN5
5 24
VINP5
6 23
VINN6
7 22
VINP6
8 21
AVDD1
9 20
AGND1
19
SE
18
SDI
17
SDIFS
16
SDOFS
15
NC = NO CONNECT
03738- 0- 005
ADSST-SALEM-3T