Specifications-Adsst-73360Lar - Analog Devices ADSST-EM-3040 Manual

Powerful energy meter chipset
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ADSST-SALEM-3T
SPECIFICATIONS—ADSST-73360LAR
(AVDD = 2.7 V to 3.6 V, DVDD = 2.7 V to 3.6 V, DGND = AGND = 0 V, f
1
T
, unless otherwise noted.)
MAX
Table 6.
Parameter
REFERENCE
REFCAP
Absolute Voltage, V
REFCAP
REFCAP TC
REFOUT
Typical Output Impedance
Absolute Voltage, V
REFOUT
Minimum Load Resistance
Maximum Load Capacitance
ADC SPECIFICATIONS
Maximum Input Range at VIN
Nominal Reference Level at VIN
(0 dBm0)
Absolute Gain
PGA = 0 dB
PGA = 38 dB
Signal to (Noise + Distortion)
PGA = 0 dB
PGA = 0 dB
PGA = 38 dB
Total Harmonic Distortion
PGA = 0 dB
PGA = 38 dB
Intermodulation Distortion
Idle Channel Noise
Crosstalk ADC-to-ADC
DC Offset
Power Supply Rejection
4, 5
Group Delay
2, 4
Input Resistance at VIN
Phase Mismatch
Min
Typ
1.08
1.2
50
130
1.08
1.2
1
2, 3
1.578
–2.85
1.0954
–6.02
–1.3
–0.8
76
71
76
58
–80
–64
–78
–68
–95
–30
–55
25
50
95
190
25
0.15
0.01
Rev. 0 | Page 12 of 24
= 16.384 MHz, f
MCLK
SCLK
Max
Unit
Test Conditions
1.32
V
0.1 µF Capacitor Required from REFCAP to AGND2
ppm/°C
1.32
V
Unloaded
kΩ
100
pF
V p-p
Measured Differentially
dBm
V p-p
Measured Differentially
dBm
+0.6
dB
1.0 kHz
+0.8
dB
1.0 kHz
dB
0 Hz to 4 kHz; f
dB
0 Hz to 2 kHz; f
f
= 60 kHz
IN
dB
0 Hz to 4 kHz; f
–71
dB
0 Hz to 2 kHz; f
dB
0 Hz to 2 kHz; f
dB
PGA = 0 dB
dB
PGA = 0 dB, f
dB
ADC1 at Idle; ADC2 to ADC6 Input Signal: 60 Hz
+30
mV
PGA = 0 dB
dB
Input Signal Level at AVDD and DVDD Pins
1.0 kHz, 100 mV p-p Sine Wave
µs
64 kHz Output Sample Rate
µs
32 kHz Output Sample Rate
µs
16 kHz Output Sample Rate
µs
8 kHz Output Sample Rate
6
kΩ
DMCLK = 16.384 MHz
Degrees
f
1 kHz
IN =
Degrees
f
60 Hz
IN =
= 8.192 MHz, f
= 8 kHz, T
S
A
= 8 kHz
S
= 8 kHz
S
= 64 kHz
S
= 8 kHz; f
= 60 kHz
S
IN
= 64 kHz; f
= 60 kHz
S
IN
= 64 kHz; SCLK = 16 MHz
S
= T
to
MIN

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