Analog Devices ADSP-2186 Specification Sheet page 19

Parameter
Bus Request/Grant
Timing Requirements:
t BR Hold after CLKOUT High
BH
t BR Setup before CLKOUT Low
BS
Switching Characteristics:
t CLKOUT High to xMS, RD, WR Disable
SD
t xMS, RD, WR Disable to BG Low
SDB
t BG High to xMS, RD, WR Enable
SE
t xMS, RD, WR Enable to CLKOUT High
SEC
t xMS, RD, WR Disable to BGH Low
SDBH
t BGH High to xMS, RD, WR Enable
SEH
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User's Manual for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
REV. 0
1
1
2
2
t
BH
CLKOUT
BR
t
BS
CLKOUT
PMS, DMS
BMS, RD
t
WR
SD
BG
t
SDB
BGH
t
SDBH
Figure 16. Bus Request–Bus Grant
Min
0.25 t + 2
CK
0.25 t + 17
CK
0
0
0.25 t – 7
CK
0
0
t
SE
t
SEH
–19–
ADSP-2186
Max
0.25 t + 10
CK
t
SEC
Unit
ns
ns
ns
ns
ns
ns
ns
ns