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TIMING PARAMETERS
Parameter
Clock Signals and Reset
Timing Requirements:
t
CLKIN Period
CKI
t
CLKIN Width Low
CKIL
t
CLKIN Width High
CKIH
Switching Characteristics:
t
CLKOUT Width Low
CKL
t
CLKOUT Width High
CKH
t
CLKIN High to CLKOUT High
CKOH
Control Signals
Timing Requirements:
t
RESET Width Low
RSP
t
Mode Setup Before RESET High
MS
t
Mode Setup After RESET High
MH
NOTES
Parameters displayed inside brackets [ ] represent preliminary 40 MHz specifications.
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
REV. 0
1
t
CLKIN
t
CKIL
CLKOUT
*
PF(2:0)
RESET
*
PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
Figure 14. Clock Signals
Min
60 [50]
20
20
0.5 t
– 7
CK
0.5 t
– 7
CK
0
5 t
CK
2
5
CKI
t
CKIH
t
CKOH
t
CKH
t
CKL
t
t
MH
MS
–17–
ADSP-2186
Max
Unit
150
ns
ns
ns
ns
ns
20
ns
ns
ns
ns
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