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ADSP-2186
concurrently on multiplexed pins. In cases where pin func-
tionality is reconfigurable, the default state is shown in plain
text; alternate functionality is shown in italics.
Common-Mode Pins
#
Input/
Pin
of
Out-
Name(s)
Pins put
RESET
1
I
BR
1
I
BG
1
O
BGH
1
O
DMS
1
O
PMS
1
O
IOMS
1
O
BMS
1
O
CMS
1
O
RD
1
O
WR
1
O
IRQ2/
1
I
PF7
I/O
IRQL0/
1
I
PF5
I/O
IRQL1/
1
I
PF6
I/O
IRQE/
1
I
PF4
I/O
PF3
1
I/O
Mode C/
1
I
PF2
I/O
Mode B/
1
I
PF1
I/O
Mode A/
1
I
PF0
I/O
CLKIN, XTAL 2
I
CLKOUT
1
O
SPORT0
5
I/O
SPORT1
5
I/O
IRQ1:0
FI, FO
PWD
1
I
PWDACK
1
O
FL0, FL1, FL2
3
O
V
and GND
16
I
DD
EZ-Port
9
I/O
NOTES
1
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to
enable the corresponding interrupts, the DSP will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices or
set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Soft-
ware configurable.
Function
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive
1
Interrupt Request
Programmable I/O Pin
Level-Sensitive Interrupt Requests
Programmable I/O Pin
Level-Sensitive Interrupt Requests
Programmable I/O Pin
Edge-Sensitive Interrupt Requests
Programmable I/O Pin
Programmable I/O Pin
Mode Select Input—Checked
only During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
only During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
only During RESET
Programmable I/O Pin During
Normal Operation
Clock or Quartz Crystal Input
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts,
2
Flag In, Flag Out
Power-Down Control Input
Power-Down Control Output
Output Flags
Power and Ground
For Emulation Use
Memory Interface Pins
The ADSP-2186 processor can be used in one of two modes:
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during RESET and cannot be changed while
the processor is running.
Full Memory Mode Pins (Mode C = 0)
#
of
Pin Name
Pins
A13:0
14
D23:0
24
Host Mode Pins (Mode C = 1)
#
of
1
Pin Name
Pins
1
IAD15:0
16
A0
1
1
D23:8
16
IWR
1
IRD
1
IAL
1
IS
1
IACK
1
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS, and IOMS signals.
Setting Memory Mode
Memory Mode selection for the ADSP-2186 is made during
chip reset through the use of the Mode C pin. This pin is multi-
plexed with the DSP's PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.
Passive configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 k , can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as a
programmable flag output without undue strain on the processor's
output driver. For minimum power consumption during
power-down, reconfigure PF2 to be an input, as the pull-up or
pull-down will hold the pin in a known state, and will not switch.
Active configuration involves the use of a three-stateable exter-
nal driver connected to the Mode C pin. A driver's output en-
able should be connected to the DSP's RESET signal such that
it only drives the PF2 pin when RESET is active (low). After
RESET is deasserted, the driver should three-state, thus allow-
ing full use of the PF2 pin as either an input or output.
–4–
Input/
Output Function
O
Address Output Pins for Pro-
gram, Data, Byte and I/O Spaces
I/O
Data I/O Pins for Program,
Data, Byte and I/O Spaces
(8 MSBs Are Also Used as
Byte Memory Addresses)
Input/
Output Function
I/O
IDMA Port Address/Data Bus
O
Address Pin for External I/O,
Program, Data, or Byte Access
I/O
Data I/O Pins for Program,
Data Byte and I/O Spaces
I
IDMA Write Enable
I
IDMA Read Enable
I
IDMA Address Latch Pin
I
IDMA Select
O
IDMA Port Acknowledge
REV. 0
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