Analog Devices ADSP-2186 Specification Sheet page 22

ADSP-2186
TIMING PARAMETERS
Parameter
Serial Ports
Timing Requirements:
t SCLK Period
SCK
t DR/TFS/RFS Setup before SCLK Low
SCS
t DR/TFS/RFS Hold after SCLK Low
SCH
t SCLK Width
SCP IN
Switching Characteristics:
t CLKOUT High to SCLK
CC
t SCLK High to DT Enable
SCDE
t SCLK High to DT Valid
SCDV
t TFS/RFS
RH OUT
t TFS/RFS
RD OUT
t DT Hold after SCLK High
SCDH
t TFS (Alt) to DT Enable
TDE
t TFS (Alt) to DT Valid
TDV
t SCLK High to DT Disable
SCDD
t RFS (Multichannel, Frame Delay Zero) to DT Valid
RDV
FRAME MODE
MULTICHANNEL MODE,
FRAME DELAY 0
FRAME MODE
MULTICHANNEL MODE,
FRAME DELAY 0
OUT
Hold after SCLK High
Delay from SCLK High
CLKOUT
t
CC
SCLK
DR
TFS
IN
RFS
IN
t
RD
t
RH
RFS
OUT
TFS
OUT
t
SCDV
t
SCDE
DT
t
TDE
t
TDV
TFS
OUT
ALTERNATE
t
RDV
RFS
OUT
(MFD = 0)
t
TDE
t
TDV
TFS
IN
ALTERNATE
t
RDV
RFS
IN
(MFD = 0)
Figure 19. Serial Ports
Min
50
4
7
20
0.25 t
CK
0
0
0
0
t
CC
t
SCP
t
t
SCS
SCH
t
SCDD
t
SCDH
–22–
Max
0.25 t + 10
CK
15
15
14
15
15
t
SCK
t
SCP
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. 0