Clock Output Function Control Registers; Timer Clock Select Register 0 Format - NEC PD78081(A) User Manual

8.3 Clock Output Function Control Registers

The following two types of registers are used to control the clock output function.
• Timer clock select register 0 (TCL0)
• Port mode register 3 (PM3)
(1) Timer clock select register 0 (TCL0)
This register sets PCL output clock.
TCL0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TCL0 to 00H.
7 6
Symbol
TCL0 CLOE 0
TCL03 TCL02 TCL01
0 1
0 1
0
1
1 0
1 0
1 0
1 0
1 1
Other than above
CLOE PCL Output Control
0 Output disable
1 Output enable
Cautions 1. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory
manipulation instruction.
2. When rewriting TCL0 to other data, stop the clock operation beforehand.
3. Set 0 to bits 4 to 6.
Remarks 1. f
XX
2. f
X
3. MCS : Oscillation mode selection register (OSMS) bit 0
4. Values in parentheses when operated at f
CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT
Figure 8-3. Timer Clock Select Register 0 Format
5 4 3 2
0 0 TCL03 TCL02 TCL01 TCL00
PCL Output Clock Selection
TCL00
0 1 f
XX
1 0 f /2
XX
2
1 f /2
1
XX
3
0 0 f /2
XX
4
0 1 f /2
XX
5
1 0 f /2
XX
6
1 1 f /2
XX
7
0 0 f /2
XX
Setting prohibited
: Main system clock frequency (f
: Main system clock oscillation frequency
1 0 Address
FF40H
MCS=1
f (5.0 MHz)
X
f /2 (2.5 MHz)
X
2
f /2 (1.25 MHz)
X
3
f /2 (625 kHz)
X
4
f /2 (313 kHz)
X
5
f /2 (156 kHz)
X
6
f /2 (78.1 kHz)
X
7
f /2 (39.1 kHz)
X
or f /2)
X X
= 5.0 MHz.
X
After
R/W
Reset
00H R/W
MCS=0
f /2 (2.5 MHz)
X
2
f /2 (1.25 MHz)
X
3
f /2 (625 kHz)
X
4
f /2 (313 kHz)
X
5
f /2 (156 kHz)
X
6
f /2 (78.1 kHz)
X
7
f /2 (39.1 kHz)
X
8
f /2 (19.5 kHz)
X
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