NEC PD78081(A) User Manual page 19

Fig. No.
11-6 Baud Rate Generator Control Register Format (2/2) .........................................................
11-7 Asynchronous Serial Interface Transmit/Receive Data Format ..........................................
11-8 Asynchronous Serial Interface Transmission Completion Interrupt Request Timing ..........
11-9 Asynchronous Serial Interface Reception Completion Interrupt Request Timing ...............
11-10 Receive Error Timing ..........................................................................................................
11-11 State of the Receive Buffer Register (RXB) when Reception is Interrupted, and
Generation/Non Generation of an Interrupt Request (INTSR) ...........................................
11-12 3-Wire serial I/O Mode Timing ............................................................................................
11-13 Circuit of Switching in Transfer Bit Order ...........................................................................
12-1 Basic Configuration of Interrupt Function (1/2) ...................................................................
12-1 Basic Configuration of Interrupt Function (2/2) ...................................................................
12-2 Interrupt Request Flag Register Format .............................................................................
12-3 Interrupt Mask Flag Register Format ..................................................................................
12-4 Priority Specify Flag Register Format .................................................................................
12-5 External Interrupt Mode Register 0 Format ........................................................................
12-6 External Interrupt Mode Register 1 Format ........................................................................
12-7 Program Status Word Configuration ...................................................................................
12-8 Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment ............
12-9 Non-Maskable Interrupt Request Acknowledge Timing ......................................................
12-10 Non-Maskable Interrupt Request Acknowledge Operation ................................................
12-11 Interrupt Request Acknowledge Processing Algorithm .......................................................
12-12 Interrupt Request Acknowledge Timing (Minimum Time) ...................................................
12-13 Interrupt Request Acknowledge Timing (Maximum Time) ..................................................
12-14 Example of Multiple Interrupt (1/2) .....................................................................................
12-14 Example of Multiple Interrupt (2/2) .....................................................................................
12-15 Interrupt Request Hold .......................................................................................................
13-1 Oscillation Stabilization Time Select Register Format ........................................................
13-2 HALT Mode Clear upon Interrupt Generation .....................................................................
13-3 HALT Mode Release by RESET Input ................................................................................
13-4 STOP Mode Release by Interrupt Generation ....................................................................
13-5 Release by STOP Mode RESET Input ...............................................................................
14-1 Block Diagram of Reset Function .......................................................................................
14-2 Timing of Reset Input by RESET Input ...............................................................................
14-3 Timing of Reset due to Watchdog Timer Overflow .............................................................
14-4 Timing of Reset Input in STOP Mode by RESET Input ......................................................
15-1 Memory Size Switching Register Format ...........................................................................
15-2 Page Program Mode Flowchart ..........................................................................................
15-3 Page Program Mode Timing ...............................................................................................
15-4 Byte Program Mode Flowchart ...........................................................................................
15-5 Byte Program Mode Timing ................................................................................................
FIGURE (3/4)
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