Cpu Clock Switching Procedure; Cpu Clock Switching - NEC PD78081(A) User Manual

5.6.2 CPU clock switching procedure

This section describes CPU clock switching procedure.
CPU Clock
(1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released
by setting the RESET signal to high level, main system clock starts oscillation. At this time, oscillation
stabilization time (2
After that, the CPU starts executing the instruction at the minimum speed of the main system clock (12.8 s when
operated at 5.0 MHz).
(2) After the lapse of a sufficient time for the V
the processor clock control register (PCC) and oscillation mode selection register (OSMS) are rewritten and
the maximum-speed operation is carried out.
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CHAPTER 5 CLOCK GENERATOR
Figure 5-7. CPU Clock Switching
V
DD
RESET
17
/f ) is secured automatically.
X
Minimum Maximum Speed
Speed Operation
Operation
Wait (26.2 ms : 5.0 MHz)
Internal Reset Operation
voltage to increase to enable operation at maximum speeds,
DD