Chapter 1. Introduction - Altera PHY IP Core User Manual

The Altera
protocol-specific PHYs:
10GBASE-R PHY IP Core
■
■ XAUI PHY IP Core
■ Interlaken PHY IP Core
■ PHY IP Core for PCI Express (PIPE)
Custom PHY IP Core
■
Low Latency PHY IP Core
■
■ Deterministic Latency PHY IP Core
The protocol-specific PHYs automatically configure settings for the physical coding
sublayer (PCS) module, leaving a small number of parameters in the physical media
attachment (PMA) module for you to configure. You can use the Custom PHY or Low
Latency PHY for applications that require more flexible settings. The design of all of
these PHYs is modular and uses standard interfaces. All PHYs include an Avalon
Memory-Mapped (Avalon-MM) interface to access control and status registers and an
Avalon Streaming (Avalon-ST) interface to connect to the MAC for data transfer. The
control and status registers store device-dependent information about the PCS and
PMA modules. You can access this device-dependent information using the
device-independent Avalon-MM interface, reducing overall complexity of your
design and the number of device-dependent signals that you must expose in your
top-level module.
f
For more information about the Avalon-MM and Avalon-ST protocols, including
timing diagrams, refer to the
Table 1–1
cores in Stratix
logic, saving FPGA resources and reducing the complexity of verification. In some
cases, the PCS is also available in soft logic as
Table 1–1. Stratix V GX Support for Protocol Specific PHY IP Cores
10GBASE-R
XAUI
Interlaken
PCI Express Gen1 and Gen2
Custom PHY
Low latency PHY
Deterministic Latency PHY
March 2012 Altera Corporation
® Transceiver PHY IP Core User Guide describes the following
Avalon Interface
shows hard and soft implementation support for these transceiver PHY IP
® V devices. Typically, the PCS and PMA are implemented as hard
PHY Protocol
1. Introduction
Specifications.
Table 1–1 indicates.
Soft PCS Hard PCS
No Yes
Yes No
No Yes
No Yes
No Yes
No Yes
No Yes
®
Hard PMA
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Altera Transceiver PHY IP Core
User Guide