Altera PHY IP Core User Manual page 73

Chapter 5: Interlaken PHY IP Core
Parameter Settings
Table 5–5. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3)
QSF Assignment Name
XCVR_TX_COMMON_MODE_
VOLTAGE
XCVR_TX_PRE_EMP_1ST_POST_
TAP
XCVR_TX_PRE_EMP_2ND_
POST_TAP
XCVR_TX_PRE_EMP_INV_
2ND_TAP
XCVR_TX_PRE_EMP_INV_
PRE_TAP
XCVR_TX_PRE_EMP_PRE_TAP
XCVR_TX_RX_DET_ENABLE
XCVR_TX_RX_DET_MODE
XCVR_TX_RX_DET_OUTPUT_SEL
XCVR_TX_VOD
XCVR_TX_VOD_PRE_EMP_
CTRL_SRC
March 2012 Altera Corporation
Pin Planner and
Assignment Editor
Name
Transmitter Common Transmitter common-mode driver
Mode Driver Voltage voltage
Transmitter Preemphasis Specifies the first post-tap setting
First Post-Tap value.
Transmitter Preemphasis Specifies the second post-tap setting
Second Post-Tap value.
Transmitter Preemphasis Inverts the transmitter pre-emphasis
Second Tap Invert 2nd post tap.
Transmitter Preemphasis Inverts the transmitter pre-emphasis
Pre Tap Invert pre-tap.
Transmitter Preemphasis Specifies the pre-tap pre-emphasis
Pre-Tap setting.
Transmitter's Receiver Enables or disables the receiver
Detect Block Enable detector circuit at the transmitter.
Transmitter's Receiver
Sets the mode for receiver detect block
Detect Block Mode
Transmitter's Receiver
Determines QPI or PCI Express mode
Detect Block QPI/PCI
for the Receiver Detect block.
Express Control
Differential output voltage setting. The
Transmitter Differential values are monotonically increasing
Output Voltage with the driver main tap current
strength.
When set to DYNAMIC_CTL, the PCS
block controls the V
preemphasis coefficients for PCI
Transmitter V /
OD
Express. When this assignment is set
Preemphasis Control
to RAM_CTL the V
Source
are controlled by other assignments,
such as
XCVR_TX_PRE_EMP_1ST_POST_TAP.
Description
VOLT_0P80V
VOLT_0P75V
VOLT_0P70V
VOLT_0P65V
VOLT_0P60V
VOLT_0P55V
VOLT_0P50V
VOLT_0P35V
PULL_UP
PULL_DOWN
TRISTATED1
GROUNDED
PULL_UP_TO
VCCELA
TRISTATED2
TRISTATED3
TRISTATED4
RX_DET_QPI_
OUT
RX_DET_PCIE_
OUT
and
OD
DYNAMIC_CTL
RAM_CTL
and preemphasis
OD
5–7
Options Assign To
Pin
Pin
0 –31
Pin
0–15
TRUE
Pin
FALSE
TRUE
Pin
FALSE
Pin
0 –15
TRUE
Pin
FALSE
Pin
0–15
Pin
0–63
Pin
50
Pin
Altera Transceiver PHY IP Core
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