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Summary of Contents for Altera Stratix II GX EP2SGX90
- Page 1 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board Reference Manual 101 Innovation Drive San Jose, CA 95134 Development Board Version: 1.0.0 (408) 544-7000 www.altera.com Document Version: 1.0.0 Document Date: May 2006...
- Page 2 Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U.S.
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Page 3: Table Of Contents
Contents About this Manual Revision History ............................v How to Contact Altera ..........................v Typographic Conventions........................vi Chapter 1. Introduction General Description..........................1-1 Board Component Blocks......................... 1-2 Block Diagram ........................... 1-3 Target Applications........................... 1-3 Data Rate & Clock Frequency Support Per Protocol ..............1-4 Handling the Board .......................... - Page 4 Contents Stratix II GX EP2GX90 Signal Integrity Development Board Reference Manual Altera Corporation Preliminary May 2006...
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Page 5: About This Manual
® ® Altera Stratix II GX family of devices and the Stratix II GX EP2SGX90 transceiver signal integrity development board. How to Contact For the most up-to-date information about Altera products, go to the Altera world-wide web site at www.altera.com. For technical support on Altera this product, go to www.altera.com/mysupport. -
Page 6: Typographic Conventions
The warning indicates information that should be read prior to starting or continuing the procedure or processes The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. Altera Corporation Preliminary May 2006... -
Page 7: Chapter 1. Introduction
The reference design is designed and tested by Altera engineers and distributed with the Transceiver SI Development Kit, Stratix II GX Edition (ordering code: DK-SI-2SGX90N). -
Page 8: Board Component Blocks
Builder CFI controller module ■ FPGA configuration JTAG interface header ● Active serial configuration scheme using EPCS64 device ● • Configures Stratix II GX device on power-up 1–2 Reference Manual Altera Corporation Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006... -
Page 9: Block Diagram
Introduction Block Diagram Figure 1–1 shows a functional block diagram of the Stratix II GX EP2SGX90 transceiver signal integrity development board. Figure 1–1. Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board Block Diagram Clock Power Supply Management Management Block Unit with Switching &... -
Page 10: Data Rate & Clock Frequency Support Per Protocol
When handling the board, it is important to observe the following precaution: Board Static Discharge Precaution—Without proper anti-static handling, the board can be damaged. Therefore, use anti-static handling precautions when touching the board. 1–4 Reference Manual Altera Corporation Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006... -
Page 11: Chapter 2. Board Components & Interfaces
For information on powering-up the Stratix II GX transceiver signal integrity development board and installing the demo software, refer to the Transceiver SI Development Kit, Stratix II GX Edition Getting Started User Guide. Altera Corporation Reference Manual 2–1 May 2006... - Page 12 Board Overview Figure 2–1 shows the top view of the Stratix II GX EP2SGX90 transceiver signal integrity development board. Figure 2–1. Top View of the Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board Temperature Sensor with Alarm (U17) 50-MHz Oscillator...
- Page 13 Board Components & Interfaces Figure 2–2 shows the diagonal view of the Stratix II GX EP2SGX90 transceiver signal integrity development board. Figure 2–2. Diagonal View of the Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board Altera Corporation Reference Manual 2–3...
- Page 14 Input Jumper Jumper header to select which JTAG source the board 2–28 header uses, i.e., the JTAG header configuration or the USB JTAG configuration. 2–4 Reference Manual Altera Corporation Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006...
- Page 15 Reference clock input for quad 3 transceiver 2–12 clock connectors Output SMA output J12, J14 Output clock from Stratix II GX 2–12 clock connectors Altera Corporation Reference Manual 2–5 May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board...
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Page 16: Featured Device
SRAM process and other DSP functions ● Supports a wide range of external memory interfaces For additional information about Altera devices, go to www.altera.com/products/devices. 2–6 Reference Manual Altera Corporation Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006... -
Page 17: Clocking Circuitry
High-speed interface support 25-MHz crystal Supports the ICS557-03 clock buffer 156.25-MHz oscillator Supports the OIF, CEI-6G, and XAUI protocols 50-MHz oscillator Supports the ICS8543 clock buffer Altera Corporation Reference Manual 2–7 May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board... - Page 18 20-pin TSSOP package, A 2:1 multiplexer to a 4:1 purpose 3.3V, LVPECL/LVDS input and low-voltage differential signaling clocking LVDS output (LVDS) fanout buffer. Part # ICS8543 2–8 Reference Manual Altera Corporation Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006...
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Page 19: Clock Buffer Functional Descriptions
Clock Buffer Functional Descriptions This section provides functional descriptions for the board’s three clock buffers: ■ ICS557-03 (U5) ■ ICS8543 (U8) ■ ICS83023 (U7) Altera Corporation Reference Manual 2–9 May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board... -
Page 20: Ics557-03 (U5): Spread Spectrum Clock Generator For Pci-Express
Table 2–6. Spread Spectrum Output Selection Setting (S8) Switch Center =/-0.25 Down -0.5 Down -0.75 No Spread Closed Open Closed Open Closed Closed Open Open 2–10 Reference Manual Altera Corporation Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006... -
Page 21: Ics8543 (U8): General Purpose 1:4 Differential Fanout Buffer
The ICS83023 is a differential I/O to a single-ended clock buffer, which is used for both the PCI-Express and Basic trigger clocks. See Figure 2–5. Figure 2–5. ICS83023 Clock Buffer Block Diagram clk0 nclk0 clk1 nclk1 Altera Corporation Reference Manual 2–11 May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board... -
Page 22: Interfaces
SMA Board Stratix II GX (U20) Schematic Signal Name Reference Pin Number REFCLKOP_QUAD1 REFCLKON_QUAD1 REFCLKOP_QUAD3 REFCLKON_QUAD3 CLOCKOUT_P AP17 GLK_P AP18 CLOCKOUT_N AN17 GCLK_N AP19 2–12 Reference Manual Altera Corporation Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006... - Page 23 FPGA Pin (Part 1 of 2) SMA Reference Block Signal Stratix II GX Pin Designator Transceiver Block 1, TX_P0 1 Channel TX_N0 RX_P0 RX_N0 Altera Corporation Reference Manual 2–13 May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board...
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Page 24: Usb Interface
In addition, the USB UART design allows the software to be designed as if writing directly to the host PC’s COM port, which eliminates the need for designing a USB software driver (see Figure 2–7). 2–14 Reference Manual Altera Corporation Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006... - Page 25 USB Interface (U2) Stratix II GX (U20) Schematic Signal Name Pin Number Pin Number UART_DATA0 UART_DATA1 UART_DATA2 UART_DATA3 UART_DATA4 UART_DATA5 UART_DATA6 UART_DATA7 UART_DATA8 UART_DATA9 UART_DATA10 UART_DATA11 Altera Corporation Reference Manual 2–15 May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board...
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Page 26: General User Interfaces
D_HED5 AA26 D_HED6 AA25 D_HED7 AA34 D_HED8 AB34 D_HED9 AB29 D_HED10 AB28 D_HED11 AC32 D_HED12 AC31 D_HED13 AB24 D_HED14 AC24 D_HED15 AC34 D_HED16 AC33 2–16 Reference Manual Altera Corporation Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006... - Page 27 D_HED12 D_HED13 D_HED14 D_HED15 D_HED16 D_HED17 D_HED19 D_HED18 CONN_PCB_10X2 Figure 2–9 shows the debug header’s board labels. Figure 2–9. Debug Header (J1) Board Labels Altera Corporation Reference Manual 2–17 May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board...
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Page 28: Leds (D1 Through D8)
USER_LED3 AD25 USER_LED4 AD34 USER_LED5 AE34 USER_LED6 AC29 USER_LED7 AC28 Figure 2–10 shows a board image of the user-defined LEDs. Figure 2–10. User-Defined LEDs 2–18 Reference Manual Altera Corporation Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006... -
Page 29: 7-Segment Displays (D9, D10)
I/O pin. When the EP2SGX90 FPGA pin drives logic 0, the corresponding segment illuminates. See Figure 2–12. Altera Corporation Reference Manual 2–19 May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board... - Page 30 DIG_1_G DIG_2_G DIG_1_DP DIG_2_DP Figure 2–12 shows the board image and name of each segment. Figure 2–12. Segment Names for the Dual 7-Segment Displays 2–20 Reference Manual Altera Corporation Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006...
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Page 31: Push-Button Switches (S1 Through S6)
2–13: The PB5 is a special purpose button, called DEV_CLRn, connected to the AH20 pin of the FPGA. The PB5 clears the FPGA data. Altera Corporation Reference Manual 2–21 May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board... -
Page 32: Dip Switches (S7 And S8)
In the open position, the selected signal is driven to logic 1. In the closed position, the selected signal is driven to logic 0. 2–22 Reference Manual Altera Corporation Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006... - Page 33 Table 2–15. Output Clock Setting DIP Switch Pinout (S8) Switch 25 MHz 100 MHz 125 MHz 200 MHz Closed Open Closed Open Closed Closed Open Open Altera Corporation Reference Manual 2–23 May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board...
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Page 34: Clock Selection Switches (S9 And S10)
Table 2–18. Clock Selection Switch (S9) Switch Setting Result Switch in OSC setting Selects the 156.25-MHz oscillator Switch in SMA position Selects external clock input 2–24 Reference Manual Altera Corporation Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006... -
Page 35: Power Supply
Linear regulators Switching regulators are used for digital circuits and linear regulators are used for analog circuits. Table 2–19 lists board regulators’ specifications. Table 2–19. Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board Regulators Board Voltage Manufacturer Part Type... - Page 36 4.75 A VCCTX VCCH 290 mA 1V2A VCCR and VCCT 1.70 A VCCIO and external components 2.45 A 3V3A VCCA and external components 1.04 A 2–26 Reference Manual Altera Corporation Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006...
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Page 37: Thermal Management Block
The active-cooling device is similar to the Radian FB35+K52+T725 active BGA cooler with clip. For more information, go to the Radian website at http://www.radianheatsinks.com/products.html. Altera Corporation Reference Manual 2–27 May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board... -
Page 38: Fpga Configuration Block
The JTAG interface permits the Quartus II software to load the Stratix II GX device with a user design through an Altera download cable. The user design remains in the Stratix II GX device until power is removed from the board. - Page 39 For more information about Stratix II GX configuration, refer to the Configuring Stratix II and Stratix II GX Devices chapter in volume 1 of the Configuration Handbook. Altera Corporation Reference Manual 2–29 May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board...
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Page 40: Flash Memory
128-Mbit memory module. The memory is available in either a 56-pin TSOP or a 64-pin FBGA. For simplicity and cost effectiveness, the board uses the TSOP package. 2–30 Reference Manual Altera Corporation Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006...