Page 1 This section provides information on the configuration modes for ® Stratix II GX devices. It also includes information on testing, Stratix II GX port and parameter information, and pin constraint information. This section includes the following chapters: ■ Chapter 1, Stratix II GX Transceiver Block Overview ■...
Page 2: Stratix Ii Gx Device Handbook, Volume
Stratix II GX Transceiver User Guide Stratix II GX Device Handbook, Volume 2 Section I–2 Altera Corporation Preliminary...
Page 3: Figure
This documentation uses the terminology inter-transceiver block routing instead of inter-quad (IQ) routing, as seen in the Quartus II software. In addition to custom (Basic) modes, Stratix II GX transceivers support the following protocols: ■ Physical Interface for PCI Express (PIPE) – single lane (×1), four lane (×4), and eight lane (×8)
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For detailed information about each block, refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. Figure 1–1. Stratix II GX Gigabit Transceiver Block Diagram Transmitter Digital Logic...
Page 5 32 bits or 40 bits, depending on the serialization factor. 8B/10B Encoder Many protocols use 8B/10B encoding. Stratix II GX devices have two dedicated 8B/10B encoders in each transmitter channel. This encoding technique ensures sufficient data transitions and a DC-balanced stream within the data signal for successful data recovery at the receiver.
Page 6 The modules originate from the serial receiver Channel buffer to the parallel FPGA interface (Figure 1–3). Overview Figure 1–3. Stratix II GX Receiver Block Diagram Receiver Digital Logic Receiver Analog Circuits RX Phase Clock Deskew Byte...
Page 7 Clock Recovery Unit The Stratix II GX transceiver block CRU performs analog clock data recovery (CDR). The CRU recovers the embedded clock in the data stream to properly clock the incoming data. The recovered clock also clocks the reset of the receiver logic clock (rx_digitalreset) and is available in the PLD fabric.
Page 8 An embedded channel aligner aligns byte boundaries across multiple channels and synchronizes the data entering the logic array from the Gigabit transceiver block’s four channels. The Stratix II GX channel aligner is optimized for a 10-Gigabit Ethernet XAUI four-channel implementation. The channel aligner includes the control circuitry and channel alignment character detection defined by the 10-Gigbit Attachment Unit Interface (XAUI) protocol.
Page 9 Basic modes and for specific protocols—XAUI, Gigabit Ethernet (GIGE), and PCI Express (PIPE). 8B/10B Decoder Various protocols use 8B/10B decoding. Stratix II GX devices have two dedicated 8B/10B decoders in each channel to support high data rates. This decoding technique ensures fast disparity and code group error detection.
Page 10: Pipe Interface
PLD fabric. The BIST pseudo-random binary sequence (PRBS) and incremental pattern generators, along with their respective pattern verifiers, provide a full self-test path. 1–8 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 11: Revision History
Stratix II GX Transceiver Block Overview Reset and Power Stratix II GX transceivers offer multiple reset signals to control separate ports of the transceiver channels and blocks. Each unused channel is Down automatically powered down to reduce power consumption. Additionally, there are dynamic power-down signals for each receiver and transmitter block.
Page 12 Updated “Word Aligner” section. ● Updated “Byte Ordering” section. ● Updated “Loopback” section. ● Updated “Built-In Self-Test” section. October 2005 Added chapter to the Stratix II GX Device — v1.0 Handbook. 1–10 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 13: Altera Corporation October
SIIGX52002-4.2 Introduction This chapter provides detailed information about the architecture of ® Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram alt2gxb Input Output rx_datain rx_dataout rx_seriallpbken rx_signaldetect...
Page 14 Stratix II GX ALT2GXB Ports List Stratix II GX Table 2–1 provides information about the Stratix II GX ports. ALT2GXB Ports List Table 2–1. Stratix II GX ALT2GXB Ports (Part 1 of 7) Port Name Input/Output Description Scope Receiver Physical Coding Sublayer (PCS) Ports Output Receiver parallel data output.
Page 15 Stratix II GX Transceiver Architecture Overview Table 2–1. Stratix II GX ALT2GXB Ports (Part 2 of 7) Port Name Input/Output Description Scope Output PIPE receiver status port. In case of multiple Channel pipestatus status signals, the lower number signal takes precedence.
Page 16 Stratix II GX ALT2GXB Ports List Table 2–1. Stratix II GX ALT2GXB Ports (Part 3 of 7) Port Name Input/Output Description Scope Output Indicates when the word aligner either aligns to Channel rx_syncstatus a new word boundary (in single-width mode...
Page 17 Stratix II GX Transceiver Architecture Overview Table 2–1. Stratix II GX ALT2GXB Ports (Part 4 of 7) Port Name Input/Output Description Scope Receiver Physical Media Attachment (PMA) Output Receiver PLL locked signal. Indicates if the Channel rx_pll_locked receiver PLL is phase locked to the CRU reference clock.
Page 18 Stratix II GX ALT2GXB Ports List Table 2–1. Stratix II GX ALT2GXB Ports (Part 5 of 7) Port Name Input/Output Description Scope Input Optional write clock port for the transmitter Channel tx_coreclk phase compensation FIFO. If not selected, Quartus II software automatically selects...
Page 19 Stratix II GX Transceiver Architecture Overview Table 2–1. Stratix II GX ALT2GXB Ports (Part 6 of 7) Port Name Input/Output Description Scope Input Available in all modes except (OIF) CEI PHY. Channel tx_invpolarity Inverts the polarity of the data to be transmitted at the transmitter PCS-PMA interface (input to the serializer).
Page 20 Stratix II GX ALT2GXB Ports List Table 2–1. Stratix II GX ALT2GXB Ports (Part 7 of 7) Port Name Input/Output Description Scope Output PLL locked indicator for the transmitter PLLs. Transceiver pll_locked block Input Reference clocks for the transmitter PLLs.
Page 21 Transmitter buffer Clock Multiplier Unit The CMU in Stratix II GX devices takes the reference clock from either the PLD or the dedicated reference clock inputs (refclk0 and refclk1) and synthesizes the clocks that are used for the transmitter logic, serializer, receiver PLL reference clock, and PLD clocks.
Page 22 Table 2–3. Reference Clock Specifications (Part 1 of 2) Protocol I/O Standard Coupling Termination Basic, XAUI, GIGE, 1.2-V PCML, 1.5-V PCML, On-chip SONET/SDH, (OIF) 3.3-V PCML, Differential CEI PHY, Serial LVPECL, LVDS RapidIO, SDI, CPRI 2–10 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 23 PLL1 can support data rates from 600 Mbps to 6.375 Gbps. Each PLL has a dedicated locked signal (pll_locked) that is fed to the PLD logic array to indicate when the PLLs are locked to the reference clock. Altera Corporation 2–11 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 24 ONLY for the pll_inclk/rx_cruclk ports of the transceiver, the Quartus II software requires the following setting for the clock source in the assignment editor for successful compilation: Assignment name: Stratix II GX REFCLK and termination setting Value: Use as regular I/O. 2–12...
Page 25 500 MHz to 3.1875 GHz to support a native data rate of 1 Gbps to 6.375 GHz. Lower data rates (600 Mbps to 1 Gbps) are supported via additional clock dividers (refer to “Clock Synthesis” on page 2–16 more information). Altera Corporation 2–13 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 26 PIPE mode, the slow-speed clock is multiplexed from the lower transceiver block. The high-speed clock goes directly into each channel’s serializer through a clock multiplexer. 2–14 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 27 PIPE ×8 mode, it also feeds the adjacent upper transceiver block. This ensures that the serializer in each channel outputs the same bit number at the same time and minimizes the channel-to-channel skew. Altera Corporation 2–15 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 28 This block synthesizes the high-speed serial clock (used by the serializer) and slow-speed clock (used by the transceiver block PCS logic—transmitter and receiver (if the rate matcher is used). The PLD 2–16 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 29 If the input clock frequency is greater than or equal to 100 MHz ● If the ratio of data rate to input clock frequency is 4, 5, or 25 ● Altera Corporation 2–17 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 30 (> 3.125 Gbps to 6.375 Gbps) Transmitter PLL Bandwidth Setting The Stratix II GX transmitter PLLs in the transceiver offer a programmable bandwidth setting. The bandwidth of a PLL is the measure of its ability to track the input clock and jitter. It is determined by the –3dB frequency of the closed-loop gain of the PLL.
Page 31 There are a maximum of five inter-transceiver clock routing lines available in each device in the Stratix II GX family. Each transceiver block can drive one inter-transceiver line from either one of its associated REFCLK pins. The inter-transceiver lines can drive any or all of the transmitter PLLs and receiver PLLs in the device.
Page 32 The transmitter clock generation blocks can divide those down to create additional frequencies for specific data rate 2–20 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 33 All channels in a transceiver must operate at the same data rate. This configuration is only supported in PIPE ×4, XAUI and Basic single-width mode with ×4 clocking. Altera Corporation 2–21 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 34 The clock to the PLD (coreclkout) is generated by the central clock generation block of the master transceiver block (the lower transceiver block). 2–22 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 35 ×8 mode if you do not assign placement. If you do not place the master and slave transceiver blocks accordingly (through pin assignments), a no fit error occurs. Altera Corporation 2–23 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 36: Table Of Contents
PCIe Lane 4 GXB_TX/RX2 PCIe Lane 6 GXB_TX/RX3 PCIe Lane 7 Bank 14 (Master) GXB_TX/RX5 PCIe Lane 1 GXB_TX/RX4 PCIe Lane 0 GXB_TX/RX6 PCIe Lane 2 GXB_TX/RX7 PCIe Lane 3 2–24 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 37 PCIe Lane 2 GXB_TX/RX7 PCIe Lane 3 Bank 15 GXB_TX/RX9 GXB_TX/RX8 GXB_TX/RX10 GXB_TX/RX11 Note to Figure 2–13: Transceiver Bank 15 can be active and used to support other protocols. Altera Corporation 2–25 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 38: Pcie Lane
PCIe Lane 6 GXB_TX/RX11 PCIe Lane 7 Second PIPE x8 Channel Bank 16 (Master) GXB_TX/RX13 PCIe Lane 1 GXB_TX/RX12 PCIe Lane 0 GXB_TX/RX14 PCIe Lane 2 GXB_TX/RX15 PCIe Lane 3 2–26 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 39: Pcie Lane
PCIe Lane 2 GXB_TX/RX15 PCIe Lane 3 Bank 17 GXB_TX/RX17 GXB_TX/RX16 GXB_TX/RX18 GXB_TX/RX19 Note to Figure 2–15: Transceiver Bank 17 can be active and used to support other protocols. Altera Corporation 2–27 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 40: Altera Corporation October
FIFO buffer and the PIPE interface (for PIPE mode) is clocked by the tx_clkout fed back through the PLD logic. Figure 2–17 shows the clocking of the receiver logic with the rate matcher. 2–28 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 41 PLD. In the PIPE ×8 slave transceiver, the central block of the associated transceiver is not active and the transmitter logic to the read port of the transmitter phase compensation FIFO buffer is clocked by Altera Corporation 2–29 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 42 FIFO buffer. The coreclkout signal routed through the PLD from the central block feeds the read side of the phase compensation FIFO buffer. In PIPE ×8, the slave transceiver takes 2–30 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 43 PLL clock. The write clock is fed by tx_clkout of the associated channel in a single-channel configuration. The FIFO buffer’s write clock is clocked by coreclkout in the four- or eight-channel configuration. Altera Corporation 2–31 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 44 To 8B/10B Encoder Byte Serializer Phase Control Signals in [3..0] Control Signals out [1..0] Compensation FIFO Slow-Speed Slow-Speed ÷2 Transmitter Clock Transmitter Clock or Divide by 2 Version 2–32 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 45 8B/10B Encoder The 8B/10B encoder (refer to Figure 2–25) is part of the Stratix II GX transceiver digital blocks and lies between the byte serializer and the serializer. The 8B/10B encoder operates in two modes: single-width and double-width and can be bypassed if the 8B/10B encoder is not used. In...
Page 46: Note To Figure
8B/10B dataout[19..10] Encoder MSByte Control Signal[1] (1) From Byte To Serializer Serializer datain[7..0] 8B/10B dataout[9..0] Encoder LSByte Control Signal[0] Note to Figure 2–26: The control signal is tx_ctrlenable. 2–34 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 47 While the tx_digitalreset signal is asserted, the 8B/10B decoder receives errors in the form of an invalid code error, synchronization error, control detect, and/or disparity error. Altera Corporation 2–35 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 48 10-bit code group may be encoded as an invalid code (does not map to a valid Dx.y or Kx.y code), or unintended valid Dx.y code, depending on the value entered. 2–36 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 49: Note To Figure
K24.1 (tx_datain = 8'h38 + tx_ctrl = 1'b1) can be encoded to 10'b0110001100 (0×18C), which is equivalent to a D24.6+ (8'hD8 from the RD+ column). Altera recommends that you do not send invalid control words. Double-Width Mode In double-width mode, the 8B/10B encoder operates in a cascaded mode.
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Both LSByte and MSByte transmit three K28.5 code groups each before the data at the tx_datain port is encoded and sent out. 2–38 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 51 It is possible for an 8B/10B decoder to decode an invalid control word encoded into a valid Dx.y code without asserting any code error flags. For example, depending on the current running disparity, the invalid code Altera Corporation 2–39 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 52 Transmitter Modules K24.1 (tx_datain = 8'h38 + tx_ctrl = 1'b1) can be encoded to 10'b0110001100 (0x18C), which is equivalent to a D24.6+ (8'hD8 from the RD+ column). Altera recommends that you do not send invalid control words. Transmitter Force Disparity Upon power on or reset, the 8B/10B encoder has a negative disparity and will choose the 10-bit code from the RD- column.
Page 53 K28.5 with a positive disparity. If the upper bit of tx_forcedisp were driven high in time n+4, the upper byte K28.5 in time n+4 will be encoded with negative disparity. Altera Corporation 2–41 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 54 8B/10B encoded link. The downstream system must be able to tolerate these disparity errors. 2–42 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 55 10-bit wide data path configuration. Figure 2–36. Transmitter Polarity Inversion in Single-Width Mode tx _invpolarity = HIGH To Serializer Output from transmitter PCS Input to transmitter PMA Altera Corporation 2–43 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 56 20-bit wide data path configuration. Figure 2–37. Transmitter Polarity Inversion in Double-Width Mode tx _invpolarity = HIGH To Serializer Input to transmitter PMA Output from transmitter PCS 2–44 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 57 Stratix II GX Transceiver Architecture Overview Transmitter Bit Reversal By default, the Stratix II GX transmitted bit order is LSBit to MSBit. In single-width mode, the least significant bit of the 8/10-bit data word is transmitted first and the most significant bit is transmitted last. In double-width mode, the least significant bit of the 16/20-bit data word is transmitted first and the most significant bit is transmitted last.
Page 58 600 Mbps to 3.125 Gbps. The 16-bit and 20-bit operations are for the double-width mode and support the data rate range from 1 Gbps to 6.375 Gbps. 2–46 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 59 8'h6A (01101010) value is serialized, and the serial data is transmitted from LSB to MSB. Figure 2–41. Serializer Bit Order Low-Speed TX_PLL_CLK High-Speed TX_PLL_CLK tx_datain[7..0] 01101010 00000000 tx_dataout[0] 0 1 0 Altera Corporation 2–47 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 60 8-bit serialization (disable 8B/10B). Transmitter Buffer The Stratix II GX transmitter buffers support 1.2-V and 1.5-V pseudo current mode logic (PCML) up to 6.375 Gbps and can drive 40 inches of FR4 trace across two connectors. The transmitter buffer (refer to Figure 2–42) has additional circuitry to improve signal integrity—...
Page 61 ALT2GXB MegaWizard Plug-In Manager (the What is the transmit buffer power (V )? option). The transmitter buffer power supply in Stratix II GX devices is transceiver based. The 1.2-V power supply supports the 1.2-V PCML standard. Altera Corporation 2–49...
Page 62 (refer to “Calibration Blocks” on page 2–229 for more information), which compensates for temperature, voltage, and process changes. The Stratix II GX transmitter buffers in the transceiver are current mode 2–50 Altera Corporation Stratix II GX Device Handbook, Volume 2...
Page 63 ALT2GXB MegaWizard Programmable Common Mode You can set the common mode in Stratix II GX devices to 600 mV or 700 mV. Use the 600-mV setting with the 1.2-V PCML standard. Use the 700-mV setting for the 1.5-V PCML standard.
Page 64 PCI Express Electrical Idle The Stratix II GX transmitter buffer supports PCI Express Electrical Idle (or individual transmitter tri-state). This feature is only active in the PIPE mode. The tx_forceelecidle port puts the transmitter buffer in Electrical Idle mode.
Page 65 Stratix II GX Transceiver Architecture Overview Receiver Buffer The Stratix II GX receiver buffers support 1.2-V, 1.5-V, 3.3-V PCML (pseudo-current mode logic), differential LVPECL and LVDS I/O standards. The receiver buffers support data rates from 600 Mbps to 6.375 Gbps and are capable of compensating up to 40 inches of FR4 trace across two connectors.
Page 66 Programmable Equalization The Stratix II GX device offers an equalization circuit in each gigabit transceiver block receiver channel to increase noise margins and help reduce the effects of high-frequency losses. The programmable equalizer...
Page 67 ALT2GXB MegaWizard Plug-In Manager. After you enable that option, you must configure the settings in the ALT2GXB_RECONFIG MegaWizard Plug-In Manager (Stratix II GX device family) in the Quartus II software. Refer to “Introduction” on page 2–1 for more information.
Page 68 Figure 2–46 shows a DC coupled link. Figure 2–46. DC Coupled Link Transmitter Receiver Trace Trace Ω Ω 50/60/75- 50/60/75- TX Termination RX Termination 2–56 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 69 Stratix II GX Transmitter (PCML) to Stratix II GX Receiver (PCML) Figure 2–47 shows a typical Stratix II GX to Stratix II GX DC coupled link. Figure 2–47. Stratix II GX to Stratix II GX DC Coupling VCCH = 1.2 V/1.5 V...
Page 70 Stratix II GX to Stratix II GX DC coupled link. Table 2–11. Settings for a Stratix II GX to Stratix II GX DC Coupled Link Transmitter (Stratix II GX) Settings Receiver (Stratix II GX) Settings...
Page 71 Stratix II GX to Stratix GX DC coupled link. Table 2–12. Settings for a Stratix II GX to Stratix GX DC Coupled Link Transmitter (Stratix II GX) Settings Receiver (Stratix GX) Settings...
Page 72 Stratix GX to Stratix II GX DC coupled link. Table 2–13. Settings for a Stratix GX to Stratix II GX DC Coupled Link Transmitter (Stratix GX) Settings Receiver (Stratix II GX) Settings...
Page 73 This is an expected behavior because the receiver PLL is inactive in the lock-to-data mode Altera Corporation 2–61 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 74 Quartus II software. The MegaWizard takes the data rate input and provides a list of the available reference clock frequencies that fall within the supported multiplication factors that you can select. 2–62 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 75 Receiver Bandwidth Type The Stratix II GX receiver PLL in the CRU offers a programmable bandwidth setting. The PLL bandwidth is the measure of its ability to track the input data and jitter. The bandwidth is determined by the –3dB frequency of the closed-loop gain of the PLL.
Page 76 (62.5, 100, 125, 200, 250, 300 , 500, or 1,000 PPM) of the CRU reference clock. ■ The reference clock and CRU PLL output are phase matched (phases are within approximately 0.08 UI). 2–64 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 77 If the CRU falls out of lock-to-data mode, the rx_freqlocked signal is deasserted. You can also deassert the rx_freqlocked signal by asserting either rx_analogreset (powers down the receiver) or gxb_powerdown (powers down all four channels of the transceiver block. Altera Corporation 2–65 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 78 600 Mbps to 3.125 Gbps, in the single-width mode. Use the 16- and 20-bit operations, which support a data rate from 1 Gbps to 6.375 Gbps, for the double-width mode. 2–66 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 79 (01101010) deserialized into a value 8’h6A (01101010). The serial data is received LSB to MSB. In Quartus II software version 7.1 and later, basic single width allows 8-bit deserializer (disable 8B/10B). Altera Corporation 2–67 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 80 8B/10B decoder and is available only in PIPE mode. Enabling the generic receiver polarity inversion and the PIPE 8B/10B polarity inversion simultaneously is not allowed in PIPE mode. 2–68 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 81 10-bit wide data path configuration. Figure 2–55. Receiver Polarity Inversion in Single-Width Mode To Word Aligner rx _ invpolarity = HIGH Output from Deserializer Input to Word Aligner Altera Corporation 2–69 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 82 20-bit wide data path configuration. Figure 2–56. Receiver Polarity Inversion in Double-Width Mode rx _invpolarity = HIGH To Word Aligner Output from Deserializer Input to Word Aligner 2–70 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 83 Word Aligner The word aligner (refer to Figure 2–57) is part of the Stratix II GX transceiver digital blocks and is located in the receiver path between the deserializer and the de-skew FIFO buffer. The word aligner restores the byte boundary of the upstream transmitter based on a programmable alignment pattern that appears in the serial data stream.
Page 84 Alignment to detected rx_enapatternalign rx_syncstatus mode pattern when allowed by rx_patterndetect rx_enapatternalign signal Manual bit-slipping Manual bit slip controlled rx_bitslip rx_patterndetect alignment mode by the PLD logic array 2–72 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 85 (widths of 16 and 32) is shown in Table 2–20. Table 2–20. Corresponding Signals for rx_dataout (Part 1 of 2) Data Width Signal Corresponding Signal rx_patterndetect[1] rx_dataout[15:8] rx_patterndetect[0] rx_dataout[7:0] Altera Corporation 2–73 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 86 [15..8]. Therefore, the alignment pattern is specified as [A2,A1] in the MegaWizard. Only the actual alignment pattern specified in the MegaWizard is detected in this mode. 2–74 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 87 K28.7 and K28.5, and also again in K28.5 (refer to Figure 2–59). Figure 2–59. Cross Boundary 7-Bit Comma When /K28.7 is Followed by /K28.5 K28.7 K28.5 7-bit comma- 7-bit comma- 7-bit comma+ Altera Corporation 2–75 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 88 In this case, the rx_syncstatus acts as a re-synchronization signal to signify that the 2–76 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 89 The alignment pattern is detected at time n + 2, but it exists on a different boundary than the current locked boundary. The bit orientation of the Stratix II GX device is LSB to MSB, so the alignment pattern exists across time n + 2 and n + 3 (refer to Figure 2–61).
Page 90 SONET/SDH alignment mode for an A1A2 pattern. For this example, a SONET/SDH A1A2 framing pattern uses 16'hF628 (16'b1111011000101000) with the reverse bit ordering. This option reverses 2–78 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 91 Manual 16-bit Alignment Mode You enable the 16-bit alignment mode in the single-width mode. This mode aligns to the 16-bit alignment pattern you specified in the MegaWizard. Altera Corporation 2–79 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 92 PLD logic array to control the bit-slip circuitry. The bit slipper is useful if the alignment pattern changes dynamically when the Stratix II GX device is in user mode. You can implement the controller in the logic array, so you can build a custom controller to dynamically change the alignment pattern without needing to reprogram the Stratix II GX device.
Page 93 8B/10B encoder/decoder is bypassed, the 8B/10B encoder/decoder logic must be implemented outside the transceiver as a requirement for using the synchronization state machine. Altera Corporation 2–81 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 94 Figure 2–64 shows a flowchart of the synchronization state machine. 2–82 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 95 This does not negate the bad code group that actually triggers the loss of synchronization. To negate a loss of synchronization, the protocol-defined number of alignment patterns must be received. Altera Corporation 2–83 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 96 There are no synchronization state machines available for the double-width mode. 2–84 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 97 For example, in the 8B/10B encoded data, a /K28.5/ (b’0011111010), /K28.1/ (b’0011111001), and /K28.7/ (b’0011111000) share seven common LSBs, so masking the three MSBs allows the pattern Altera Corporation 2–85 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 98 (but different disparity). The Dx.y code group does not necessarily use its true and complement to represent the same code group. 2–86 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 99 7-bit alignment pattern. You must differentiate if the acquired byte boundary is correct, because the 7-bit pattern can appear between word boundaries. For example, in the standard 7-bit Altera Corporation 2–87 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 100 The rx_syncstatus signal remains high until it sees another rising edge on the rx_enapatternalign. After detecting a rising edge 2–88 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 101 You must deassert the rx_enapatternalign signal and assert it again for re-alignment. Altera recommends using the /K28.5/ code group as one of the control codes for this alignment pattern.
Page 102 MegaWizard because the true and complement of each code group is checked automatically by the pattern detector. Do not use Dx.y codes as the alignment pattern in the 20-bit alignment mode. 2–90 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 103 MegaWizard, the rx_patterndetect signal is asserted for one clock cycle. You must implement the logic in the PLD logic array to control the bit-slip circuitry. Altera Corporation 2–91 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 104 Double-width Receiver Bit Reversal By default, the Stratix II GX receiver assumes an LSBit to MSBit transmission. If the transmission order is MSBit to LSBit, then the receiver will put out the bit-flipped version of the data on the PLD interface. The Receiver Bit Reversal feature is available to correct this situation.
Page 105 MegaWizard Plug-In. In configurations where this feature is dynamic, an rx_revbitordwa port is available to control the bit reversal dynamically. A high on the rx_revbitordwa port reverses the bit order at the input of the word aligner. Altera Corporation 2–93 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 106 RX Bit Reversal = Enabled D[4] D[5] D[3] D[6] D[2] D[7] D[1] D[8] D[0] D[9] Output of Word Aligner after RX Output of Word Aligner before bit reversal RX bit reversal 2–94 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 107 D[5] D[14] D[4] D[15] D[3] D[16] D[2] D[17] D[1] D[18] D[0] D[19] Output of Word Aligner Output of Word Aligner after RX bit reversal before RX bit reversal Altera Corporation 2–95 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 108 Figure 2–71. Receiver Byte Reversal Feature MSByte Data to be transmitted LSByte MSByte Input data to transmitter LSByte revbyteordwa MSByte Word Aligner Output with rx _revbyteordwa LSByte asserted 2–96 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 109 "Align"/A/, Code Groups Lane 3 Stratix II GX devices manage XAUI channel alignment with a dedicated deskew macro that consists of a 16-word-deep FIFO buffer that is controlled by a XAUI deskew state machine. The XAUI deskew state machine first looks for the /A/ code group within each channel. When the XAUI deskew state machine detects /A/ in each channel, the deskew FIFO buffer is enabled.
Page 110: Rate Matcher
The rate matcher operates in five modes: GIGE, XAUI, PIPE, Basic single-width mode, and Basic double-width mode. Figure 2–74. Rate Matcher datain dataout Rate Matcher wrclock rdclock 2–98 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 111 The transceiver block can operate in multi-crystal environments, which can tolerate frequency variations of ± 300 PPM between crystals. Stratix II GX devices have embedded circuitry to perform clock rate compensation. Clock rate compensation is achieved by inserting or removing skip characters from the IPG or idle streams. This process is called rate matching or clock rate compensation.
Page 112 PIPE mode. There is no limit on the consecutive number of skip characters allowed per skip cluster. The Stratix II GX rate matcher in PIPE mode has FIFO buffer overflow and underflow protection. In the event of a FIFO buffer overflow, the rate matcher deletes any data after the overflow condition to prevent FIFO pointer corruption until the rate matcher is not full.
Page 113 Altera Corporation 2–101 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 114 K28.5 K28.0 K28.0 The Stratix II GX rate matcher in single-width mode has FIFO buffer overflow and underflow protection. In the event of a FIFO buffer overflow the rate matcher deletes any data after the overflow condition to prevent FIFO buffer pointer corruption until the rate matcher is not full.
Page 115 8B/10B Decoder The 8B/10B decoder (Figure 2–80) is part of the Stratix II GX transceiver digital blocks and lies in the receiver path between the rate matcher and the byte deserializer blocks. The 8B/10B decoder operates in two modes: single-width and double-width modes and can be bypassed if 8B/10B decoding is not needed.
Page 116 Figure 2–80: Status signals include rx_ctrldetect, rx_disperr, and rxerrdectect. Single-Width Mode In single-width mode, the Stratix II GX 8B/10B decoder operates in a similar fashion as the Stratix GX 8B/10B decoder. The highlighted data path in Figure 2–81 is active in the single-width mode.
Page 117 Disparity Error Detector The 8B/10B decoder detects disparity errors based on which 10-bit code it received. The disparity error is indicated at the optional rx_disperr port. Altera Corporation 2–105 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 118 Refer to the Specifications & Additional Information chapter in volume 2 of the Stratix II GX Device Handbook for information on the disparity calculation. If negative disparity is calculated for the last 10-bit code, a neutral or positive disparity 10-bit code is expected. If the 8B/10B decoder does not receive a neutral or positive disparity 10-bit code, the rx_disperr signal goes high, indicating that the code received had a disparity error.
Page 119 The rest of the codes received are Dx.y code groups. Figure 2–84. Control Code Detection clock rx_dataout[7..0 ] rx_ctrldetect Code Group D3.4 D24.3 D28.5 K28.5 D15.0 D0.0 D31.5 D28.1 Altera Corporation 2–107 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 120 Dx.y or Kx.y list with the proper disparity or error flags asserted. All 8B/10B control signals (disparity error, control detect, and code error) are pipelined with the data in the Stratix II GX receiver block and are edge-aligned with the data.
Page 121 LSByte decoder on the next clock cycle. Refer to the Specifications & Additional Information chapter in volume 2 of the Stratix II GX Device Handbook for information on the disparity calculation. Altera Corporation 2–109 October 2007...
Page 122 Figure 2–87. Disparity Error clock rx_dataout[15..0 ] BCBC BCBC xxBC BCBC rx_disperr[1..0] rx_errdetect[1..0] rx_ctrldetect[1..0] Expected RD Code RD Code Received rx_datain 17C 283 17C 283 283 283 283 17C 2–110 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 123 The receiver block must be word aligned after reset before the 8B/10B decoder can decode valid data or control codes. If word alignment has not been achieved, the data from the 8B/10B decoder is discarded and considered invalid. Altera Corporation 2–111 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 124 40-bits (36-bits when using the 8B/10B encoder) and the interface speed drops to 159.375 MHz. Table 2–22. Byte Deserializer Input and Output Widths Deserialized Output Data Width to the FPGA Input Data Width (Bits) Logic Array (Bits) 2–112 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 125 Byte Ordering The Stratix II GX device has a dedicated byte ordering circuit on each receiver to obtain a certain byte order on multiple lanes. This circuit is used in conjunction with the byte deserializer block. The byte deserializer doubles the number of lanes for each receiver.
Page 126 “A” character, goes into the byte ordering block in lane two. The byte ordering block inserts two pad bytes, denoted by PD, delaying the alignment byte until it appears in the LSByte position (lane 0). 2–114 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 127 (stays high). If the alignment pattern is already in the LSByte position, the byte ordering block does not add any pad byte, considers the byte ordering process complete, and asserts the rx_byteorderalignstatus signal. Altera Corporation 2–115 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 128 A in the second least significant byte position and adds three pad bytes PD. The byte ordering pattern A now appears at the least significant byte position and rx_byteordalignstatus is asserted. 2–116 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 129 What to choose as the byte ordering pattern ■ When to assert the rx_enabyteord signal In Stratix II GX configurations, PLD-controlled byte ordering is available only in SONET/SDH OC-48 mode or Basic double-width mode. In SONET/SDH OC-48 mode, byte A2 of the A1A2 word alignment pattern is automatically selected as the byte ordering pattern.
Page 130 FIFO can be clocked by either the recovered clock (rx_clkout) or transmitter PLL output clock (tx_clkout or coreclkout). The read port can be clocked by the recovered clock (rx_clkout), transmitter PLL output clock (tx_clkout or 2–118 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 131 The following clock inputs utilize the PLD interface clocks: ■ rx_cruclk (if driven from the PLD clock tree) ■ Pll_inclk (if driven from the PLD clock tree) ■ tx_coreclk ■ rx_coreclk ■ Cal_blk_clk Altera Corporation 2–119 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 132 REFCLK pins to save on PLD interface clocks. The Quartus II software does not cross the transceiver block boundary when combining like TX channels. Also, the Quartus II software does not combine RX clocks automatically. 2–120 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 133 PLD phase compensation must decouple the phase difference. Figure 2–99 shows of TX and RX PLD phase compensation FIFOs decoupling the user logic from the transceiver. Altera Corporation 2–121 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 134 PLD output clock frequency, you will need to manually connect the tx_coreclk and rx_coreclk ports. 2–122 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 135 For example, in a synchronous system, the TX and RX are of the same data rate and configuration. The clock output of the channel 0 is used (but any TX clock output can be used). The Stratix II GX GXB Shared Clock Group Driver Setting is made in the assignment editor on the tx_dataout[0] name.
Page 136 A breakdown of the assignment in the assignment editor is shown in Table 2–23: Table 2–23. Assignment Editor tx_dataout[0] Assignment name: Stratix II GX GXB Shared Clock Group Driver Setting Value: (note that the [] signifies the entire rx_datain[] group) rx_datain...
Page 137 To user logic Tx_clkout[0] The Stratix II GX 0PPM Clock Group Setting is for more advanced users that know the clocking configuration of the entire system and wants to reduce the PLD global clock resource and PLD interface clock resource utilization.
Page 138 An integer value is specified for the group identification. The Stratix II GX 0 PPM Clock Group Setting is made to the TX or RX channel names. A breakdown of the assignment in the assignment editor is shown in Table 2–24:...
Page 139 Channel 3 RX Phase Comp FIFO Channel 2 RX Phase Comp FIFO Channel 1 RX Phase Comp FIFO Channel 0 RX Phase Comp FIFO To user logic rx_clkout[0] Altera Corporation 2–127 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 140 All logic and the write ports of all the TX phase compensation FIFO will the driving clock feeds will flatline. A digital reset must be done on all channels after a driving transceiver block power down event. 2–128 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 141 REFCLK pin be of the same frequency as the transceiver output clocks of the associated channels. Any frequency difference yields corruption of data. Altera Corporation 2–129 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 142 0PPM setting will also allow TX and/or RX channel PCFIFOs of multiple transceiver blocks to be clocked by a common clock. 2–130 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 143 PLD and transceiver blocks. Tables 2–25 through 2–28 give the number of LRIO resources available for Stratix II GX devices with different numbers of transceiver blocks. Altera Corporation 2–131 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 144: Bank
Bank16 Global Clock Clock 8 Clock I/O 8 Clock I/O 8 Clock I/O 8 Clock I/O Region0 RCLK 20-27 8 LRIO Clock Region1 RCLK 20-27 8 LRIO Clock 2–132 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 145 Table 2–29. Clock Port List (Part 1 of 2) Maximum Number per Clock Name Notes Transceiver Block pll_inclk can share rx_cruclk rx_cruclk resources with pll_incl tx_clkout / tx_coreclk rx_clkout / rx_coreclk Altera Corporation 2–133 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 146 XAUI To PLD fabric. coreclkout Region0 LRIO Clock pll_inclk Using one REFCLK pin. Bank14 Connect to rx_cruclk pll_inclk. GIGE 4ch To PLD fabric. tx_clkout Region1 LRIO Clock 2–134 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 147 Region3 LRIO Clock 5/8 (or 6/8, 7/8) Multiple Stratix II GX supports multiple protocols and/or data rates in a single transceiver block. This allows for better utilization of the channels and Protocols and power savings. There can be up to four independent data rates supported...
Page 148 Quartus II software automatically combines multiple ALT2GXB Megafunction instances into a transceiver block if possible. If there is a particular placement required, Altera recommends that you force the placement via TX and/or RX channel pin assignment in the assignment editor. Quartus II software checks to see if the desired placement is possible.
Page 149 Mixing single-width and double-width modes is not allowed for TXPLL sharing. Altera Corporation 2–137 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 150 1 Gbps links. Since the target data rate is either a /1, /2, or /4 division factor from the highest data rate, it is possible to combine this into a single transceiver block. It is assumed that the VCCH, transceiver block signals 2–138 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 151 If the two 4 Gbps channels were to be configured in separate instances, the resultant transceiver block configuration will not have changed. Altera Corporation 2–139 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 152 Primary Data rate : 4 Gbps Inst 2 ALT2GXB Ch 0 Data rate: 1 Gbps TX Loc Div: /4 TXPLL Primary Data rate : 4 Gbps Inst 3 2–140 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 153 Data rate : 4 Gbps Ch 1 TX Loc Div: / 1 Data rate : 4 Gbps Ch 0 TX Loc Div: / 1 TXPLL Primary Data rate: 4 Gbps Altera Corporation 2–141 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 154 2 Gbps and 1 Gbps channels operate in a single-width mode (due to the sub 3.125 Gbps primary data rate). 2–142 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 155 Primary Data rate : 2 Gbps Inst 2 ALT2GXB Ch 0 Data rate: 1 Gbps TX Loc Div: /2 TXPLL Primary Data rate : 2 Gbps Inst 3 Altera Corporation 2–143 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 156 Primary Data rate : 4 Gbps Data rate: 4 Gbps Ch 1 TX Loc Div: / 1 Data rate: 4 Gbps Ch 0 TX Loc Div: / 1 2–144 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 157 “Combining RX Channels in a Transceiver Block” on page 2–145. Native Modes The Stratix II GX transceiver operates in one of nine native modes: ■ Basic Single-width mode (600 Mbps to 3.125 Gbps) ● Double-width mode (1 Gbps to 6.375 Gbps) ●...
Page 158 (CRU). Configuring transceivers in this mode yields low transmitter channel-to-channel skew within a transceiver block. It does not provide skew reduction for channels placed across transceiver blocks. 2–146 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 159 All channels within the transceiver block configured to this mode must be instantiated using the same ALT2GXB MegaWizard instance. Altera Corporation 2–147 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 160 REFCLK pins of either Bank 14 or 15. ■ De-asserting the tx_digitalreset signal of all used transceiver blocks simultaneously after pll_locked signal from all active transceiver blocks goes high. 2–148 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 161 Use Basic double-width mode for custom protocols that are not part of the pre-defined supported protocols, for example, PIPE. With some restrictions, the following PCS blocks are available: ■ Transmitter phase compensation FIFO buffer ■ Transmitter byte serializer Altera Corporation 2–149 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 162 Compen- serializer Ordering Decoder FIFO Aligner serializer FIFO Unit sation FIFO Receiver Digital Logic Stratix II GX devices support the PIPE standard in ×1, ×4, and ×8 configurations. 2–150 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 163 Stratix II GX Transceiver Architecture Overview The Stratix II GX device has dedicated circuits to support the PCI Express protocol, including the following: ■ 8B/10B encoder and decoder ■ Rate matcher, which supports a multi-crystal environment up to ±300 PPM (600 PPM total) clock difference ■...
Page 164 A PCI Express fast training sequence consists of a /K28.5/, followed by three /K28.1/ code group. If there is one code group error during the synchronization process, resynchronization must be performed. 2–152 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 165 Bit 2 = 1, assert Bit 3–Disable scrambling Bit 3 = 0, deassert Bit 3 = 1, assert Bit 4..7–Reserved Bit 0 = 0, deassert Set to 0 6–15 D10.2 TS1 identifier Altera Corporation 2–153 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 166 Bit 2 = 1, assert Bit 3–Disable scrambling Bit 3 = 0, deassert Bit 3 = 1, assert Bit 4..7–Reserved Bit 0 = 0, deassert Set to 0 6–15 D5.2 TS2 identifier 2–154 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 167 There is no limit on the consecutive number of skip characters allowed per skip cluster. The Stratix II GX rate matcher in PIPE mode has FIFO buffer overflow and underflow protection. In the event of a FIFO buffer overflow, the rate matcher deletes any data after the overflow condition to prevent FIFO pointer corruption until the rate matcher is not full.
Page 168 P2 power-down state. Table 2–35 shows the behavior of the tx_detectrxloopback and tx_forceelecidle signals in the power states. 2–156 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 169 3'b000— received data. If the upper MAC layer must know when a skip character was added or removed, Altera recommends monitoring the number of skip characters received. The transmitter should send three skip characters in a standard skip-ordered set.
Page 170 P2 power state. This signal is optional, and the Stratix II GX device does not have dedicated beacon transmission circuitry. The Stratix II GX device supports the transmission of the beacon signal through a 10-bit encoded code word that has a five 1’s pulse (for example, K28.5).
Page 171 NTFS Fast Recovery IP (NFRI) The PCI-E specification fast training sequences (FTS) are used for bit and byte synchronization to transition from L0s state to L0 (Stratix II GX P0s to P0) power states. The PCI-E base specification states that the required time period for this transaction be within 16 ns to 4 us.
Page 172 In the Quartus II software version 7.2, the solution is built into the software when you enable the fast recovery mode option in the ALT2GXB MegaWizard. 2–160 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 173 P0s to P0 per the protocol specification. ■ 3.2us_timer: A user-implemented timer in the PLD logic to count 3.2 us. This timer represents the minimum time period to wait before looking for valid data. Altera Corporation 2–161 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 174 ALT2GXB to the user logic). Set the pipedatavalid_PLD to the pipedatavalid value (that is, forward the pipedatavalid value from the ALT2GXB to the user logic). Return to Step 1. ● 2–162 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 175 ALT2GXB to the user logic). Set pipedatavalid_PLD to the pipedatavalid value (that is, ● forward the pipedatavalid value from the ALT2GXB to the user logic). Return to Step 1. ● Altera Corporation 2–163 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 176 FIFO should be cleared and the pointers reset to the middle. Following this reset, look for the FTS ordered set. For other cases to assert rx_diditalreset, refer to “Reset Sequence for PIPE Mode” on page 2–218. 2–164 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 177 Low-Latency PIPE mode The Stratix II GX receiver data path employs a rate match FIFO in PIPE mode to compensate up to ± 300 PPM difference between the upstream transmitter and the local receiver reference clock. The rate match FIFO adds a latency of 12-16 parallel clock cycles to the link.
Page 178 (Table 2–37). Table 2–37. Normal and Low-Latency PIPE Status (Part 1 of 2) pipestatus[2:0] Normal PIPE Low-Latency PIPE Received Data OK Received Data OK Not supported Not supported 2–166 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 179 XGMII Extender Sublayer (XGXS) to 10 Gigabit Media Independent Interface (XGMII) and XGMII to XGXS code-group conversion macros. For HiGig, the Stratix II GX XAUI data rate protocol has been extended from 3.125 Gbps up to 3.75 Gbps. For HiGig data rates, select the XAUI protocol and type in the increased data rate.
Page 180 4 differential receiver channels for a total of a 16-pin-wide interface. This reduction in pin count significantly simplifies the routing process in the layout design. Figure 2–121 shows the relationships between the XGMII and XAUI layers. 2–168 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 181 XAUI functions as a self-managed interface because code group synchronization, channel deskew, and clock domain decoupling is handled with no upper layer support requirements. This functionality is Altera Corporation 2–169 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 182 - - - T/RxD<23:16> - - - T/RxD<31:24> - - - Lane 0 - - - Lane 1 - - - Lane 2 - - - Lane 3 2–170 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 183 Each comma can be followed by any number of valid code groups. Invalid code groups are not allowed during the synchronization stage. When you configure Stratix II GX devices to the XAUI protocol, the built-in pattern detector, word aligner, and XAUI state machines adhere to the PCS synchronization specification.
Page 184 SUDI SUDI PUDI([/INVALID/]) PUDI([/INVALID/]) PUDI(∉[/INVALID/])*good_cgs = 3 PUDI(∉[/INVALID/]) SYNC_ACQUIRED_4 SYNC_ACQUIRED_4A PUDI(∉[/INVALID/])* ⇐ ⇐ good_cgs good_cgs good_cgs + 1 good_cgs ≠ 3 SUDI SUDI PUDI([/INVALID/]) PUDI([/INVALID/]) PUDI(∉[/INVALID/])*good_cgs = 3 2–172 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 185 "Align"/A/, Code Groups Lane 3 Stratix II GX devices manage XAUI channel alignment with a dedicated deskew macro that consists of a 16-word-deep FIFO buffer that is controlled by a XAUI deskew state machine. The XAUI deskew state machine first looks for the /A/ code group within each channel. When the XAUI deskew state machine detects /A/ in each channel, the deskew FIFO buffer is enabled.
Page 186 IPG or idle stream. This process is called rate matching and is sometimes referred to as clock rate compensation. The rate matcher in Stratix II GX devices consists of a 12-word-deep FIFO buffer along with control logic that you can configure to support XAUI, GIGE, or custom modes.
Page 187 This circuitry compensates for ±100 PPM frequency variations. PCS Code Group to XGMII Character Mapping In XAUI mode, the 8B/10B decoder in Stratix II GX devices is controlled by a global receiver state machine that maps various PCS code groups into specific 8-bit XGMII codes.
Page 188 A_CNT=0 A_CNT=0 A_CNT≠0 * cod_sel=1 SEND_RANDOM_A ⇐ tx_code_group<39:0> ||A|| PUDR Q_det !Q_det * cod_sel=1 SEND_RANDOM_Q ⇐ tx_code_group<39:0> TQMSG ⇐ Q_det FALSE !Q_det * cod_set=1 PUDR cod_set=1 cod_set=1 2–176 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 189 PCS, the PMA, and the physical medium dependent (PMD) layers. GMII offers data rates up to 1000 Mbps at either half- or full-duplex modes. Altera Corporation 2–177 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 190 This layer handles the serialization and deserialization of the data. The PMD sublayer defines actual physical attachment, such as connectors for different media types. 2–178 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 191 Data Link Physical Medium The Stratix II GX transceiver can be used for the PCS and the PMA layers of the GMII. Stratix II GX devices in GIGE mode use the 8B/10B encoder/decoder, rate matcher, and synchronizer built-in hard macros.
Page 192 Synchronization is required in GIGE mode to align the byte boundary of the receiver to the byte boundary of the transmitter, because the Stratix II GX transceiver block uses a non-source-synchronous serial stream. To correctly align the byte boundary at the receiver, a unique synchronization pattern must be received that does not occur between any Dx.y and/or Kx.y code combinations.
Page 193 SYNC_ACQUIRED_4A cggood *good_cgs = 3 ⇐ ⇐ rx_even ! rx_even rx_even ! rx_even SUDI SUDI ⇐ ⇐ good_cgs good_cgs good_cgs + 1 cgbad cgbad cggood *good_cgs = 3 Altera Corporation 2–181 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 194 GIGE Transmitter Synchronization The transmitter must send out the GIGE synchronization sequence to synchronize the target receiver. Stratix II GX devices do not contain a built-in macro that provides this function upon power-up or reset. You must implement this function in user logic to send out a /K28.5/, /Dx.y/, /K28.5/, /Dx.y/, /K28.5/, /Dx.y/ sequence.
Page 195 (right before the idle code). This ensures a negative running disparity at the end of an idle ordered set. A /Kx.y/ following a /K28.5/ is not replaced. Altera Corporation 2–183 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 196 GIGE can operate in a multi crystal environment, so rate matching is necessary to compensate for the frequency variations from different crystals. Stratix II GX devices contain a built-in rate matcher (12-word-deep FIFO buffer with control logic) that can tolerate up to, and compensate for, a ±100 PPM frequency variation.
Page 197 Figure 2–136 shows one don’t care data between the tx_digitalreset signal going low and the first of three automatic K28.5, but there could be more. Altera Corporation 2–185 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 198 SONET/SDH defines various optical carrier (OC) subprotocols for carrying signals of different capacities through a synchronous optical hierarchy. Stratix II GX transceivers can be employed as physical layer devices in a SONET/SDH system. These transceivers provide support for SONET/SDH protocol-specific functions and electrical features; for example, alignment to A1A2 or A1A1A2A2 pattern.
Page 199 PLD interface as compared to the 8-bit PLD interface in an OC-12 configuration. The OC-48 configuration employs the byte serializer and deserializer and a byte ordering block to translate 16-bit PLD interfaces into an 8-bit transceiver data path. Altera Corporation 2–187 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 200 OC-96 configuration does not have the byte ordering block in the transceiver data path. If required, you should implement byte ordering logic in the PLD logic array in OC-96 configurations. 2–188 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 201 In OC-12 and OC-48 configurations, you can configure the word aligner to either align to a 16-bit A1A2 pattern or a 32-bit A1A1A2A2 pattern. This is controlled by the rx_a1a2size input port to the transceiver. A Altera Corporation 2–189 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 202 The byte serializer and deserializer blocks are explained in the sections “Byte Serializer” on page 2–32 “Byte Deserializer” on page 2–112, respectively. The OC-48 byte serializer converts 16-bit data words from 2–190 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 203 So, if a byte ordering operation is required, the receiver must go through an rx_digitalreset cycle. Altera Corporation 2–191 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 204 Internetworking Forum (OIF) at data rates between 4.976 Gbps and 6.375 Gbps ■ Interlaken protocol at data rates between 3.135 Gbps and 6.375 Gbps Stratix II GX transceivers support a data rate between 3.135 Gbps and 6.375 Gbps in (OIF) CEI PHY Interface Mode. 2–192 Altera Corporation...
Page 205 FIFO Receiver Digital Logic Table 2–44 shows ALT2GXB configurations supported by the Stratix II GX transceivers in (OIF) CEI PHY Interface mode. Table 2–44. ALT2GXB Configurations in (OIF) CEI PHY Interface Mode REFCLK Frequency (PLL Data Rate (Mbps) Channel Width Multiplication Factor) 3135 <...
Page 206 Figures 2–144 2–145 show two examples each of legal and illegal transceiver placements with respect to the improved jitter clocking option in (OIF) CEI PHY Interface mode. 2–194 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 207 The following three SMPTE standards are popular in video broadcasting applications: ■ SMPTE 259M standard—more popularly known as the standard-definition (SD) SDI, is defined to carry video data at 270 Mbps. Altera Corporation 2–195 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 208 SMPTE 424M standard—more popularly known as the third-generation (3G) SDI, is defined to carry video data at either 2970 Mbps or 2967 Mbps. You can configure Stratix II GX transceivers in HD-SDI or 3G-SDI configuration using the ALT2GXB MegaWizard Plug-In Manager. Figure 2–146 shows the ALT2GXB transceiver data path in SDI mode.
Page 209 Altera recommends driving the ALT2GXB rx_bitslip signal low to avoid the word aligner from inserting bits in the received data stream. Altera offers SDI MegaCore function that can be configured at SD-SDI, HD-SDI, and 3G-SDI data rates. The SDI MegaCore function implements system-level functions like scrambling and de-scrambling and CRC generation and checking.
Page 210 It also defines two link widths—single-lane (1×) and bonded four-lane (4×) at each line rate. Stratix II GX transceivers support only single-lane (1×) configuration at all three line rates. Four 1× channels configured in Serial RapidIO mode can be instantiated to achieve a 4× Serial RapidIO link. The four transmitter channels in this 4×...
Page 211 Stratix II GX Transceiver Architecture Overview Stratix II GX transceivers do not have built-in support for other PCS functions; for example, clock frequency compensation between upstream transmitter clock and local receiver clock (rate matcher), pseudo-random idle sequence generation, and lane alignment in 4× mode. Depending on your system requirements, you must implement these functions in the logic array or external circuits.
Page 212 CPRI Mode The common public radio interface (CPRI) specification defines a radio base station interface standard between the radio equipment control (REC) and the radio equipment (RE). 2–200 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 213 CPRI line bit rate option 2: 1228.8 Mbps (2 x 614.4 Mbps) ■ CPRI line bit rate option 3: 2457.6 Mbps (4 x 614.4 Mbps) Stratix II GX transceivers support all three line bit rate options. Figure 2–149 shows the ALT2GXB transceiver data path when configured in CPRI mode.
Page 214 FIFO latency becomes constant. The Quartus II software performs the delay adjustment to minimize the uncertainty in link latency only in CPRI mode. 2–202 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 215 Since a maximum of 32 global and/or regional clock resources are available for transceivers in the Stratix II GX device, the clock resource availability governs the maximum number of CPRI channels that you can instantiate per device.
Page 216 Individual Clocks window, select New. In the New Clock Settings window, browse to all rx_clkout and tx_clkout nodes and assign 60% in the Duty Cycle option for each of these phase compensation FIFO clocks. 2–204 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 217 The serial data is the data that is transmitted from the Stratix II GX device. Once the data enters the receiver in serial form, it can utilize any of the receiver blocks and is then fed into the FPGA logic array.
Page 218 Serial loopback is often used to check the entire path of the transceiver. The data is retimed through different clock domains and an alignment pattern is still necessary for the word aligner. Figure 2–152. Stratix II GX Block in Serial Loopback Mode Transmitter Digital Logic Analog Receiver and...
Page 219: Reverse Serial Loopback
Stratix II GX Transceiver Architecture Overview Figure 2–153. Stratix II GX Block in PCI Express PIPE Reverse Parallel Loopback Mode Transmitter Digital Logic Analog Receiver and Transmitter Logic BIST BIST Incremental PRBS Generator Generator TX Phase Byte 8B/10B Serializer Compensation...
Page 220 Loopback Modes Figure 2–154. Stratix II GX Block in Reverse Serial Loopback Mode Transmitter Digital Logic Analog Receiver and Transmitter Logic BIST BIST PRBS Incremental Generator Generator TX Phase Byte 8B/10B Serializer Compensation Serializer Encoder FIFO FPGA Logic Reverse Array...
Page 221: Parallel Loopback
Stratix II GX Transceiver Architecture Overview Figure 2–155 show the Stratix II GX block in reverse serial pre-CDR loopback mode. Figure 2–155. Stratix II GX Block in Reverse Serial Pre-CDR Loopback Mode Transmitter Digital Logic Analog Receiver and Transmitter Logic...
Page 222 Pattern 16 Bit 20 Bit Pattern Incremental with 20'h16E83 All 8B/10B valid code 8B/10B groups Figure 2–156. Stratix II GX Block in Parallel Loopback Mode Transmitter Digital Logic Analog Receiver and Transmitter Logic BIST BIST PRBS Incremental Generator Generator TX Phase...
Page 223 Buit-In Self Test tx_digitalreset[] (BIST) rx_bisterr rx_digitalreset[] rx_seriallpbken[] rx_bistdone pll_inclk[] Notes to Figure 2–157: rx_seriallpbken[] is required in PRBS. rx_bisterr[] and rx_bistdone[] are only available in PRBS and BIST modes. Altera Corporation 2–211 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 224 BIST patterns for single-width mode. Table 2–50. Available BIST Patterns in Single-Width Mode Single-Width Mode Word Aligner Byte Order Align Pattern Description Alignment Pattern Pattern 8 Bit 10 Bit PRBS10 10'h3FF 2–212 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 225 8B/10B paths, the incremental BIST can test this path. BIST in Double-Width Mode Double-width mode supports only PRBS7 pattern generation and verification. The PRBS7 pattern is only available when the SERDES factor is 20 bits. Altera Corporation 2–213 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 226 Use the rx_digitalreset signal to re-start the PRBS verification. Reset Control Stratix II GX transceivers offer multiple reset signals to control separate ports of the transceiver channels and blocks (Figure 2–159).
Page 227 User Reset and Enable Signals Each transceiver block and each channel in the transceiver block of the Stratix II GX device has individual reset signals to reset the digital and analog portions of the channel. The analog resets are power-down signals, which require a longer pulse width for the circuits to power down.
Page 228 BIST generators Receiver deserializer Receiver word aligner Receiver deskew FIFO buffer Receiver rate matcher Receiver 8B/10B encoder Receiver phase compensation FIFO buffer and byte deserializer Receiver PLL and 2–216 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 229 PLL asserts its associated pll_locked signal. The rx_digitalreset signal can be de-asserted 4us after the rx_freqlocklocked signal goes high (time between markers 6 and 7). Altera Corporation 2–217 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 230 During this phase, all the transceiver reset signals (gxb_powerdown, tx_digitalreset, rx_analogreset, and rx_digitalreset) are asserted. The minimum time period between markers 1 and 2 for the gxb_powerdown signal is 100 ns (Figure 2–161). 2–218 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 231 Figure 2–162. PIPE Mode Reset During Rate Matcher FIFO Buffer Overflow and Underflow Condition tx_digitalreset rx_analogreset rx_digitalreset rx_freqlocked pipestatus Notes to Figure 2–162: Pipestatus = 101 represents elastic overflow. Pipestatus = 110 represents elastic overflow. Altera Corporation 2–219 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 232 Power Down The Quartus II software automatically selects the power-down channel feature, which takes affect when you configure the Stratix II GX device. All unused transceiver and blocks in a design are powered down to reduce the overall power consumption. You cannot use the power-down feature on the fly to turn the transceiver channels and transceiver blocks on and off without reconfiguration.
Page 233 Either leave these pins floating or connect refclk(n) to GND through a 10-kΩ resistor and connect refclk(p) to GXB_VCC through a 10-kΩ resistor to improve the device’s immunity to noise. Altera recommends driving the reference resistor pin low for the powered down transceiver block. All supported VODs.
Page 234 The tx_digitalreset port is driven from an input pin. Figures 2–164 2–165 show the TimeQuest Timing Analyzer Report for Unconstrained Input Port Paths and Unconstrained Output Port Paths, respectively. 2–222 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 235 Stratix II GX Transceiver Architecture Overview Figure 2–164. Unconstrained Input Port Paths Altera Corporation 2–223 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 236 Input Port Paths or Unconstrained Output Port Paths report. Right click on the reset/powerdown port in the To column and select Set Max Delay. On the resulting window, enter an initial Delay Value of 4 ns. 2–224 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 237 13. Execute Report Top Failing Paths once again. If there are any failing paths involving the reset/powerdown ports, adjust the delay values in the SDC file and repeat the procedure until no failing paths are reported. Altera Corporation 2–225 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 238 After running the Quartus II fitter with the above timing constraints for the gxb_powerdown port, the following slack is reported on this path after executing Report Top Failing Paths (Figure 2–166). Figure 2–166. Slack Reported for the gxb_powerdown Port 2–226 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 239 This is acceptable as long as the skew is within the specified period (2.8 ns) for each path in the SDC file for each timing model. Altera Corporation 2–227 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 240 For example, if the rx_invpolarity signal is driven by the signal top_rx_invpolarity on an input pin, the SDC file constraint for this port should be set as: set_max_delay -from [get_ports {top_rx_invpolarity}] [get_keepers {xcvr_inst.receive~OBSERVABLEINVPOL}] 10.000 2–228 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 241 PLL and Output Buffer Calibration Block Each Stratix II GX transceiver block contains a PLL and output buffer calibration circuit to counter the effects of PVT (process, voltage, and temperature) on the PLL and output buffer. Each transceiver block’s calibration circuit uses a voltage reference derived from an external reference resistor.
Page 242 Calibration Blocks Termination Resistor Calibration Block The Stratix II GX transceiver’s on-chip termination resistors in the transceiver channels of the entire device are calibrated by a single calibration block. This block ensures that process, voltage, and temperature variations do not have an impact on the termination resistor value.
Page 243 Figure 2–70 ● Figure 2–118 Updated: — ● Table 2–1 ● Table 2–3 ● Table 2–6 ● Table 2–8 ● Table 2–18 ● Table 2–19 ● Table 2–24 Altera Corporation 2–231 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 244 “Serial Digital Interface (SDI) Mode” ● “Serial RapidIO Mode” ● “CPRI Mode” ● “DC Coupling” ● “Basic Single-Width Mode with x4 Clocking” Added Table 2–2. — Minor text edits. — 2–232 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 245 Changes Made Summary of Changes Document Version August 2007, v4.1 Moved the Dynamic Reconfiguration section. The Dynamic Reconfiguration section was moved to the Stratix II GX Dynamic Reconfiguration chapter in this handbook. Added Table 2–45. — Added note to “Serializer” and “Deserializer”.
Page 246 “Loopback Modes” ● ● “BIST in Single-Width Mode” ● “BIST in Double-Width Mode” ● “Transmitter Buffer” “Transmitter PLL Block” ● ● “Transmitter PLL Bandwidth Setting” ● “Transmitter Polarity Inversion” 2–234 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 247 Minor change to Figure 2–1. ● Updated descriptions for ● Updated Table 2–1. rx_errdetect ● Updated Figures 2–90 and 2–96. cal_blk_powerdown ● Added “NTFS Fast Recovery IP (NFRI)” section. Table 2–1. Altera Corporation 2–235 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 248 ● Added “Dynamic Reconfiguration” section. December 2005, Updated technical content throughout chapter. — v2.0 October 2005 Added chapter to the Stratix II GX Device — v1.0 Handbook. 2–236 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 249 Typically, to achieve the intended bit error rate (BER) for a system, you will take advantage of the multiple analog settings provided in the Stratix II GX device. Being able to change the analog settings is a powerful tool that you can use during link and system debug.
Page 250 Quartus II ALT2GXB_RECONFIG module to control the Reconfiguration configurable settings of the transceiver. The dynamic reconfiguration controller is a soft IP which utilizes Stratix II GX device PLD resources. It Controller is optimized for minimal PLD resource usage. Only one controller is Architecture allowed per transceiver block.
Page 251 Not backward compatible with Stratix GX devices ■ To and from PCI Express (PIPE) mode with NFRI IP ■ Testability features (pseudo-random binary sequence [PRBS] and built-in self test [BIST]) Altera Corporation 3–3 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 252 Extending the same logic to the maximum possible instances case of 20 transmit-only and 20 receive-only configurations, targeted for a five transceiver block Stratix II GX device, the maximum starting channel number of the dynamic reconfiguration option is 156 (40 instances * 4).
Page 253 Analog Settings Reconfiguration—Write and Read (read is optional) ■ Channel Reconfiguration—Write Transaction Only ■ Dynamic Transmit Rate Switch—Write and Read (read is optional) ■ Channel and CMU PLL Reconfiguration ■ CMU PLL-Only Reconfiguration Altera Corporation 3–5 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 254 Quartus II software version 6.0 and later 001 – Channel Reconfiguration ● 011 – Dynamic Transmit rate switch ● 100, 101, 110 – Channel and CMU PLL Reconfiguration ● 3–6 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 255 Reconfiguration” on page 3–87 for detailed reconfig_mode_sel[2:0] signal encoding. As described in “Stratix II GX ALT2GXB Megafunction User Guide” on page 4–1, the signals reconfig_togxb[2:0] and reconfig_fromgxb are the interface signals between the ALT2GXB instance and the ALT2GXB_RECONFIG instance. The dynamic reconfiguration controller runs at a frequency determined by the clock reconfig_clk signal.
Page 256: Reconfig_Clk
Output Status signal to indicate that the reconfiguration controller busy has not completed the read or write transaction. 3–8 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 257 Error checks/data rate switch tab. The dynamic reconfiguration controller de-asserts the busy signal and asserts the signal error for two cycles when you attempt an reconfig_clk unsupported operation. Altera Corporation 3–9 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 258 9–15 represents 1 to 7 8 maps to 0 Input Optional equalization control signal on the receive side of rx_eqctrl the PMA. It is a 4-bit bus per each channel. 3–10 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 259 Channel Reconfiguration or Channel and CMU PLL Reconfiguration feature (discussed in “Channel and Clock Multiplier Unit (CMU) PLL Reconfiguration” on page 3–87). Altera Corporation 3–11 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 260 00 - Divide by 1 01 - Divide by 2 10 - Divide by 4 11 - Not supported (do not attempt to read or write with this value) 3–12 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 261: Logical_Tx_Pll_Sel
Example 1 Consider a design with two instances of an ALT2XGB configuration, Instance1 with five transceiver channels and Instance2 with three transceiver channels. Altera Corporation 3–13 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 262 Set the What is the number of channels controlled by the controller? option to 12. The setting for this option has a number that is more than the total number of channels needed to be controlled 3–14 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 263 ALT2GXB_RECONFIG reconfig_fromgxb[2]. Refer to Figure 3–3 for more information. ■ Connect the reconfig_togxb signal from the ALT2GXB_RECONFIG instance to the same signal on the ALT2GXB instance. Altera Corporation 3–15 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 264 5 along with other options in the ALT2GXB MegaWizard. ■ Enable the Analog controls option under the dynamic reconfiguration settings (to dynamically change equalization values, also enable the Enable equalizer settings option). 3–16 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 265 (three channels into one transceiver block) and have the option set to at least three so that the Quartus II software enables three channels of the analog control signals in the options sections. Altera Corporation 3–17 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 266 ALT2GXB Instance ALT2GXB_RECONFIG (Three Channels) tx_vodctrl[8..0] tx_vodctrl_out[8..0] rx_eqctrl[11..0] rx_eqctrl_out[11..0] reconfig_fromgxb reconfig_fromgxb What is the number of channels controlled by the controller? in ALT2GXB_RECONFIG is 3 3–18 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 267 20 so that five interface signals are enabled (reconfig_fromgxb[4:0]). ■ Select the necessary analog control signals to write in and read out from the V , pre-emphasis, equalization, and DC gain options. Altera Corporation 3–19 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 268 Set the reconfig_mode_sel signal to 000 to reconfigure the analog settings of a transceiver channel. 3–20 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 269 To properly initiate and complete a write transaction during channel reconfiguration, the dynamic reconfiguration controller provides additional signals. These signals are listed below and are classified into control and status signals. Altera Corporation 3–21 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 270 This signal is very useful for user logic to implement reset recommendations during and after dynamic reconfiguration. Refer “Reset Recommendations” on page 3–66 for more information about using this signal. 3–22 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 271 The rate_switch_ctrl[1:0] input port is set to 11 • reconfig_mode_sel input port is set to 4 (if other reconfiguration mode options are selected in the Reconfiguration settings tab) • write_all is asserted Altera Corporation 3–23 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 272 ALT2GXB is instantiated in the design. In this section, the different ways of setting up the ALT2GXB instantiation and the corresponding logical_channel_address values for these transceiver channels are shown. 3–24 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 273 0 to 5, respectively (as shown in Figure 3–6). ■ The logical_channel_address values for transceiver channels 0 through 5 (tx_dataout[0] to tx_dataout[5]) are 0, 4, 8, 12, 16, and 20, respectively. Altera Corporation 3–25 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 274 = 8) controller togxb[2:0] reconfig_fromgxb[3] Channel 3 (Logical channel number = 12) reconfig_fromgxb[4] Channel 4 (Logical channel number = 16) reconfig_fromgxb[5] Channel 5 (Logical channel number = 20) 3–26 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 275 2 to 5 are 4, 5, 8, and 9, respectively. (The starting channel number option value for instantiation1 is 4. Therefore, the logical_channel_address value for channel 2 is 4). Altera Corporation 3–27 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 276 _ clk write _ all busy reconfig _ address _ out[4:0] Addr 0 Addr 1 reconfig _ address_en bits reconfig_data[15:0] _ st 16- nd 16-bits Don't Care 3–28 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 277 Figure 3–10. Read Transaction Waveform – V , Analog Settings Reconfiguration reconfig _ clk read data _ valid busy 3'b000 Invalid output tx _ vodctrl _ out [ 2 :0 ] Altera Corporation 3–29 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 278 However, some of the CME features are static and set through the Quartus II ALT2GXB configuration. Channel reconfiguration only affects the channel involved in the reconfiguration; other channels are not affected. 3–30 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 279 The settings are all legal register settings of the transceiver channel. The ALT2GXB_RECONFIG instance reads the value in the MIF using the reconfig_data[15..0] port for every write transaction. Altera Corporation 3–31 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 280 MIF generation. Once the Quartus II software settings are enabled, a MIF is generated after you compile an ALT2GXB instance. The three steps to enable MIF generation are shown below. 3–32 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 281 Stratix II GX Dynamic Reconfiguration On the Assignments menu, select Settings (Figure 3–12). Figure 3–12. MIF Generation, Step 1 (Settings Option) Altera Corporation 3–33 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 282 Channel and PMA Controls Reconfiguration Select Fitter settings, then choose More Settings (Figure 3–13). Figure 3–13. MIF Generation, Step 2 (Fitter Settings) 3–34 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 283 Stratix II GX Dynamic Reconfiguration In the Option box of the More Fitter Settings page, set the Generate Stratix II GX GXB reconfig MIF option to On c (Figure 3–14). Figure 3–14. MIF Generation, Step 3 (Enable Settings) The MIF is generated in the Assembler stage of the compilation process.
Page 284 Local clock dividers further divide the TX PLL base rate and are present in transmit and receive block of every transceiver channel (refer toFigure 3–15). 3–36 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 285 Set the local clock divider setting (use the effective data rate for that configuration). Enable either the Channel Internals or Channel Interface option (refer to “Channel Internals” on page 3–53 “Channel Interface” on page 3–53 for more information). Altera Corporation 3–37 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 286 Step is a mandatory step and is an important part of clocking in every channel reconfiguration (refer to Figure 3–17). Figure 3–17. ALT2GXB Instance—TX/RX Local Clock Divider 3–38 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 287 10. Similarly, generate a MIF for Mode2 as primary and Mode1 as alternate by going through steps 1 through 9 again (refer to “Example 1” on page 3–13). Altera Corporation 3–39 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 288 PCI-E or GIGE, the alternate PLL related options will be automatically populated by the Quartus II software. For more information about the channel internal option, refer to “Channel Interface” on page 3–53. 3–40 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 289 TX PLL setup, you will set the logical reference index. To generate a MIF for the GIGE protocol, set the GIGE as the main configuration in the ALT2GXB instance and SONET/SDH mode as the Altera Corporation 3–41 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 290 TX PLL 1 (77.76MHz) (SONET) 625MHz pll_inclk TX PLL 2 (125 MHz) (GIGE) CMU Block local refclk MuxSelect =1 rx_cruclk_alt (77.76 MHz) Clock to CDR rx_cruclk (125 MHz) RX Channel 3–42 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 291 MIF is a complement in the second MIF. Steps is discussed in “Core Clocking” on page 3–45. Altera Corporation 3–43 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 292 MIF through the Quartus II Assignment Editor by setting the Stratix II GXB reconfig group setting option to ON in the Quartus Assignment Editor (Figure 3–22). 3–44 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 293 Transmitter core clocking is the write clocking options for the Transmit Phase Comp FIFO. The transmitter core clocking is used to write the parallel data into the Transmit Phase Comp FIFO from the PLD interface. Altera Corporation 3–45 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 294 ALT2GXB MegaWizard. Figure 3–23 shows the two options in transmit core clocking for tx_clkout routing. Figure 3–23. ALT2GXB MegaWizard Reconfiguration – Transmit Core Clocking Options 3–46 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 295 TX Phase Comp FIFO. This type of core clocking configuration is needed when individual transmit channels can switch modes (basically, each channel switches to a different mode using channel reconfiguration). Altera Corporation 3–47 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 296 ALT2GXB MegaWizard only asks for the rx_clkout settings. The Quartus II software automatically routes the clock paths based on a given mode setup. You must verify that clock routing is compatible with each 3–48 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 297 Basic 2 Gbps mode with rate matching, and then switches to a Basic 3.125 Gbps mode with rate matching. In this case, option 1 is applicable. Altera Corporation 3–49 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 298 TX3/RX3: Basic 4 Gbps with rate matching to Basic 1 Gbps with rate matching ■ TX0/RX0: Basic 3.125 Gbps with rate matching to 1 Gbps with rate matching and vice versa 3–50 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 299 TX1/RX1: GIGE to SONET/SDH OC48 ■ TX2/RX2: Basic 2.5 Gbps no rate matching to Basic 1.244 G bps no rate matching In this case, option 3 is applicable. Altera Corporation 3–51 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 300 (for example, CME features) in a transceiver channel In the ALT2GXB instance’s reconfiguration section, the PLD data path interface can be set up through two subsections: ■ Channel Internals ■ Channel Interface 3–52 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 301 Enabling the channel interface provides an option pane in the ALT2GXB megafunction where you can select the necessary ports for control and status signals that are needed for each of their channel reconfiguration. Altera Corporation 3–53 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 302 Receiver PLD interface: ● rx_dataout[39:0] ● rx_syncstatus[3:0] ● rx_patterndetect[3:0] ● rx_a1a2sizeout[3:0] ● rx_ctrldetect[3:0] ● rx_errdetect[3:0] ● rx_disperr[3:0] ■ Transmitter PLD interface: ● tx_datain[39..0] ● tx_ctrlenable[3:0] ● tx_forcedisp[3:0] ● tx_dispval[3:0] 3–54 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 303 Stratix II GX Dynamic Reconfiguration Figure 3–30. ALT2GXB Reconfiguration – Channel Interface Enabled Altera Corporation 3–55 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 304 3–4. Table 3–3. tx_datainfull[43:0] PLD Data Signal Descriptions (Part 1 of 3) Transmit Signal Description PLD Interface Description (Based on Stratix II GX Supported PLD Interface Widths) : 8-bit data ( tx_datainfull[7:0] tx_datain The following signals are used only in 8B/10B modes:...
Page 305 Stratix II GX Dynamic Reconfiguration Table 3–3. tx_datainfull[43:0] PLD Data Signal Descriptions (Part 2 of 3) Transmit Signal Description PLD Interface Description (Based on Stratix II GX Supported PLD Interface Widths) Two 8-bit Data ( tx_datain tx_datainfull[7:0 tx_datain (LSByte) and...
Page 306 Channel and PMA Controls Reconfiguration Table 3–3. tx_datainfull[43:0] PLD Data Signal Descriptions (Part 3 of 3) Transmit Signal Description PLD Interface Description (Based on Stratix II GX Supported PLD Interface Widths) Four 8-bit Data ( tx_datain tx_datainfull[7:0] tx_datain (LSByte) and...
Page 307 Table 3–4. rx_dataoutfull[63:0] PLD Data Signal Descriptions (Part 1 of 6) Receive Signal Description PLD Interface Description (Based on Stratix II GX Supported PLD Interface Widths) The following signals are used in 8-bit 8B/10B modes: : 8-bit decoded data (...
Page 308 Channel and PMA Controls Reconfiguration Table 3–4. rx_dataoutfull[63:0] PLD Data Signal Descriptions (Part 2 of 6) Receive Signal Description PLD Interface Description (Based on Stratix II GX Supported PLD Interface Widths) Two 8-bit un-encoded Data ( rx_dataout rx_dataoutfull[7:0] rx_dataout (LSByte) and...
Page 309 Stratix II GX Dynamic Reconfiguration Table 3–4. rx_dataoutfull[63:0] PLD Data Signal Descriptions (Part 3 of 6) Receive Signal Description PLD Interface Description (Based on Stratix II GX Supported PLD Interface Widths) Two 8-bit Data rx_dataoutfull[7:0] rx_dataout (LSByte) and (MSByte) rx_dataoutfull[39:32]...
Page 310 Table 3–4. rx_dataoutfull[63:0] PLD Data Signal Descriptions (Part 4 of 6) Receive Signal Description PLD Interface Description (Based on Stratix II GX Supported PLD Interface Widths) Two Receiver Pattern Detect Bits 16-bit PLD interface with PCS-PMA set to 8/10 bits...
Page 311 Stratix II GX Dynamic Reconfiguration Table 3–4. rx_dataoutfull[63:0] PLD Data Signal Descriptions (Part 5 of 6) Receive Signal Description PLD Interface Description (Based on Stratix II GX Supported PLD Interface Widths) Four 8-bit un-encoded Data ( rx_dataout rx_dataoutfull[7:0] rx_dataout (LSByte)
Page 312 Table 3–4. rx_dataoutfull[63:0] PLD Data Signal Descriptions (Part 6 of 6) Receive Signal Description PLD Interface Description (Based on Stratix II GX Supported PLD Interface Widths) The following signals are used in 32-bit SONET/SDH scrambled backplane mode: Four Control Data Bits (...
Page 313 Quartus II software, since it is an on-the-fly control feature. You also need to ensure that a specific functional mode supports the data rate range before dividing the clock when using this rate switch option. Altera Corporation 3–65 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 314 Channel and PMA Controls Reconfiguration Reset Recommendations Altera recommends that you follow a proper reset sequence during and after for PMA controls reconfiguration, channel reconfiguration, and dynamic transmit rate switching. PMA Controls Reconfiguration During the first time the dynamic reconfiguration controller initiates a...
Page 315 Refer to the Reset Control and Power Down section of the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Handbook for more information. In addition to the above recommendations, if you are using the Channel...
Page 316 Figure 3–33 shows the receiver sequence. Dynamic Rate Switching For a design using dynamic transmit rate switching, Altera recommends that you assert the tx_digitalreset when you initiate the rate switch operation until the busy signal goes low. 3–68 Altera Corporation...
Page 317 Stratix II GX Dynamic Reconfiguration Overall Design Flow for Channel Reconfiguration The following describes the design flow for Stratix II GX channel reconfiguration. ALT2GXB Instantiation Create an ALT2GXB MegaWizard instantiation. Select the protocol mode, single width, double width, data rate, and input reference clock frequency.
Page 318 Reconfiguration tab. Control Logic for ALT2GXB_RECONFIG: 12. Implement logic to control the ALT2GXB_RECONFIG signals and to select the appropriate MIFs from memory and send the MIF data to ALT2GXB_RECONFIG. 3–70 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 319 “Reset Recommendations” on page 3–66 more information. Figure 3–34. Functional Blocks for Channel Reconfiguration Data Path Logic Reset Control Logic ALT2GXB MIF1 Control Logic for ALT2GXB_ ALT2GXB_ RECONFIG MIF2 RECONFIG Altera Corporation 3–71 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 320 These differences determine the selection of parameters in the ALT2GXB MegaWizard and the required PLD logic to configure a transceiver channel between these two modes. Figure 3–35 shows the required functional blocks to perform channel reconfiguration. 3–72 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 321 (shown in Table 3–5). ■ Section IV—Resets the control logic to control the transceiver and system resets. Altera Corporation 3–73 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 322 For a list of ALT2GXB signals and their functionality, refer to “Stratix II GX ALT2GXB Ports List” on page 2–2 in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. In the Reconfig tab, set the following options: If you need control of the transceiver PMA values, select the ●...
Page 323 (row 5 of Table 3–5). Therefore, the PLD logic can clock the receive output of the ALT2GXB with rx_clkout for SONET/SDH mode and tx_clkout for the GIGE mode. Altera Corporation 3–75 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 324 “Stratix II GX ALT2GXB Ports List” on page 2–2 in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. 13. In the subsequent tabs, select the required signals and complete the MegaWizard instantiation.
Page 325 Refer to the “Stratix II GX ALT2GXB Ports List” on page 2–2 in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for the cal_block_clk signal requirements. Connect the tx_dataout and rx_datain ports to the top-level module.
Page 326 Write Logic to Select the MIF and to Control the ALT2GXB_RECONFIG: Create two memory elements, each 16-wide and 28-bits deep. The memory elements can be a RAM/ROM inside or outside the Stratix II GX device. Assign the two MIFs to each of these memory elements. 3–78 Altera Corporation...
Page 327 You can also use the channel_reconfig_done signal to determine the end of the write operation. The channel_reconfig_done signal goes high one clock cycle after the reconfig_address_out signal changes from 27 back to 0. Altera Corporation 3–79 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 328 The PLD logic should selectively use some of these signals based on whether the transceiver channel is configured in GIGE mode or SONET/SDH OC48 mode. 3–80 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 329 GIGE and SONET/SDH OC48 modes. Based on the configured protocol mode, the receive side logic selects the appropriate data path. Altera Corporation 3–81 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 330 .hex file, open the .mif in the Quartus II software and save it as a .hex file. Initialize the memory elements with the .hex file to simulate the design. 3–82 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 331 ● Set the data rate to 3.125 Gbps. ● Set the input reference clock to 156.25 MHz. Select all the resets, pll_locked, rx_freqlocked, and other required status signals. Altera Corporation 3–83 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 332 This design example explains the steps to dynamically divide the transmit data rate of a transceiver channel by 4, 2, or 1 without requiring MIF generation. The ALT2GXB_RECONFIG instance provides a rate_switch_ctrl signal for this purpose. 3–84 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 333 Mode and SONET/SDH OC48 Mode” on page 3–72. Select the Modify the data rate using the local divider option in the Reconfiguration Settings tab. This creates the rate_switch_ctrl and rate_switch_ctrl_out signals. Altera Corporation 3–85 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 334 The signals that are referred to in the following write sequence correspond to the input and output ports of the ALT2GXB_RECONFIG instantiation in your design. 3–86 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 335 0. Channel and Introduction Clock Multiplier The Stratix II GX transceiver can be dynamically reconfigured to various protocols and data rates. This section discusses the dynamic Unit (CMU) PLL reconfiguration features introduced in Quartus II software version 7.1.
Page 336 Channel and TX PLL reconfiguration ● Channel reconfiguration with TX PLL select ● ■ The number of possible clock sources for the input reference clocks is increased from two to five. 3–88 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 337 TX PLLs, and to configure a transceiver channel. Using these enhancements, you can use the Stratix II GX transceiver to dynamically support multiple protocols and data rates. In the following sections, the new dynamic reconfiguration features and the different software settings required to implement these features are discussed in detail.
Page 338 Inter Quad (IQ) lines, or from the global clock networks that are driven by an input pin. Figure 3–40 shows the reference clock connections to TX PLLs and RX PLLs in a transceiver channel. 3–90 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 339 Since each transceiver block has a fixed LRIO resource, using the global clock line may restrict the number of clocks you can provide to the transceiver channels in your design. Altera Corporation 3–91 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 340 Clock Resource section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. Using Dedicated refclks When you use dedicated refclks as input reference clocks, the refclk pre-divider is required if one of the following conditions is satisfied: If the input clock frequency is greater than 325 MHz.
Page 341 Figure 2–4 in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for more information. The refclk pre-divider is not part of the information stored in the MIF. It is a static setting created during the ALT2GXB MegaWizard configuration.
Page 342 156.25 MHz pll_inclk_rx_cruclk[1] bank 13 clock source ALT2GXB Instance 1 IQ Lines or Global Clock Network bank 14 pll_inclk_rx_cruclk[0] 125 MHz ALT2GXB 125 MHz Instance 2 pll_inclk_rx_cruclk[1] clock source 3–94 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 343 The Quartus II software automatically routes the clock input to all the transceiver blocks through IQ lines or global clock routing resources, depending on whether you Altera Corporation 3–95 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 344 Stratix II GX Device pll_inclk_rx_ 156.25 MHz cruclk[0] clock source ALT2GXB refclk0 Instance 1 bank 13 IQ Lines or Global Clock Network pll_inclk_rx_ cruclk[0] ALT2GXB Instance 2 bank 14 3–96 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 345 “D”, “E”, and “F” in Figure 3–45. These fields are explained in detail in “ALT2GXB MegaWizard Settings” on page 3–113. Figure 3–45. Input Clock Settings of the Reconfig Clks 1 Tab Altera Corporation 3–97 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 346 The channel and CMU PLL reconfiguration feature is divided into three categories based on the functionality: ■ Channel and TX PLL reconfiguration ■ TX PLL reconfiguration ■ Channel reconfiguration with TX PLL select 3–98 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 347 Table 3–10. Address Incremented by the Reconfig Controller (Part 1 of 2) reconfig_mode_sel[2:0] Incremented Address 001 (channel reconfiguration) 0-27 100 (TX PLL only) 0, 28-37 Altera Corporation 3–99 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 348 Assume that the logical tx pll value is set to 0 for the main TXPLL. (The settings to select the logical tx pll value for the TX PLLs are discussed in “ALT2GXB MegaWizard Settings” on page 3–113). 3–100 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 349 MIF are covered later in this section. The intent of this example is to show how the functional blocks are reconfigured based on the feature used). Altera Corporation 3–101 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 350 TX PLL, you can reconfigure the other TX PLL, and later switch the transmit channel to listen to the configured TX PLL (explained in “Channel Reconfiguration with TX PLL Select” on page 3–103). 3–102 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 351 TX PLLs. To use this feature, set the reconfig_mode_sel value to 110 and write the MIF contents. The Channel Reconfiguration with TX PLL Select option, in combination with the TX PLL Reconfiguration Altera Corporation 3–103 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 352 + analog logic Select 2.5 Gbps clock LOGICAL TXPLL1 RX CHANNEL 6.25 Gbps 6.25 Gbps clock digital + analog logic RX PLL Reconfigured functional blocks after MIF write 3–104 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 353 Port Port the Reconfig Controller enabled enabled - value high Value on the port. logical_tx_pll_sel enabled enabled - value zero value stored in logical tx pll the MIF. Altera Corporation 3–105 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 354 MIF. When you configure a transceiver channel in the ALT2GXB MegaWizard, Altera recommends that you keep track of the TX PLL that drives the channel. You may require this information when you want to reconfigure the TX PLLs dynamically. This is illustrated in “Design Examples”...
Page 355 6.25 Gbps. The transmit channel still listens to the logical TXPLL0 and therefore runs at 5 Gbps (since in this mode, the logical tx pll select MUX is not reconfigured). The receive side is not configured with this feature. Altera Corporation 3–107 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 356 MIF and the logical_tx_pll_sel set to 1. Note that in this case, the TX PLL is not configured. After the MIF is written, the logical TX PLL multiplexer gets configured to select the logical TXPLL1. 3–108 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 357 TX PLL that is reconfigured) before continuing normal operation. The dynamic reconfig controller powers down ONLY the selected TX PLL. The other TX PLL is not affected. Altera Corporation 3–109 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 358 Words 0 to 27 - approximately 260 clock cycles per word ■ Words 28 to 37 - approximately 521 clock cycles per word Reset Recommendations Altera recommends that you follow a proper reset sequence during and after CMU PLL reconfiguration. Figure 3–55 shows the recommended reset sequence.
Page 359 38 words, complete the following steps: Go to the Assignments menu and select Settings, then Fitter settings. Click the more settings button and set the Generate Stratix II GX GXB Reconfig MIF with PLL option to ON using the Settings option (as shown in Figure 3–56).
Page 360 Quartus II software automatically assigns these channels to different transceiver blocks. If you use a Stratix II GX device with one transceiver block, you cannot compile the design if you assign different TX PLL reconfig group values for the channels in your design.
Page 361 : tx_dataout_ch0 Assignment Name: Stratix II GX GXB TX PLL Reconfig group setting Value : tx_dataout_ch1 Assignment Name: Stratix II GX GXB TX PLL Reconfig group setting...
Page 362 When you select the Enable Channel and Transmitter PLL Reconfiguration option, you cannot select the Use alternate reference clock option (used in channel reconfiguration feature). These two fields are mutually exclusive. Figure 3–58. Reconfig Tab 3–114 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 363 TXPLL. Otherwise, you can select the logical tx pll value for the main TXPLL in this tab (at the What is the main PLL logical reference clock index? option in Figure 3–60). Altera Corporation 3–115 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 364 For additional information on the input clock requirements, refer to “Clocking Enhancements and Requirements” on page 3–90. 3–116 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 365 If you would like to reuse the MIF across transceiver channels, you must have the same order of clock inputs across all the ALT2GXB instantiations that are using this MIF. Altera Corporation 3–117 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 366 Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for information about other ALT2GXB MegaWizard settings. ALT2GXB RECONFIG Tab Settings The Quartus II software version 7.1 has the following enhancements in the ports/values option in the ALT2GXB_RECONFIG MegaWizard.
Page 367 Quartus II software version 6.1. To write the MIF, follow the method used for the channel reconfiguration feature. Refer to Figure 3–8 on page 3–28 for more information. Altera Corporation 3–119 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 368 Consider that you create an ALT2XB instantiation (full-duplex or TX-only configuration) that has only one TX PLL. If you would like to create another ALT2GXB instantiation configured at a different data rate in the 3–120 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 369 When you merge the transmit only and receive only configurations, you should add the Stratix II GX Reconfig group setting in the assignment editor for the tx_dataout and rx_datain pins and assign the same value to these two pins (0 or 1).
Page 370 Case I: Configuring Transceiver Channels to Switch Together Between GIGE, SONE-OC48, and Fibre Channel (FC)-4G Protocols The GIGE, SONET/SDH OC48, and FC-4G have different input reference clocks, data path, and clocking requirements. For this example, assume the following Stratix II GX device configuration: ■ Three transceiver banks ■...
Page 371 TX PLL is connected to CH1). Similarly, the same method can be applied for all the other channels in this example design. In total, you only need three MIFs for this example design. Altera Corporation 3–123 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 372 Tab Page and Option Setting General Tab Settings which protocol you will be using basic which sub protocol you will be using serial loopback operation mode receiver and transmitter 3–124 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 373 TX PLL to switch across protocols. Therefore, you do not need an alternate TXPLL for this instance. Reconfig Clks 1 Tab Settings what is the main PLL logical reference clock index Altera Corporation 3–125 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 374 Refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook for more information about these options. how should the transmitters be clocked use the respective channel transmitter core clocks.
Page 375 Table 3–13 use clock 2 reference clock divider do not check this option Reconfig2 Tab Settings same as of the FC-4G instantiation shown in Table 3–13 Altera Corporation 3–127 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 376 106.25 MHz use clock 0 reference clock divider do not check this option what is the reconfig protocol driven by GIGE clock1 what is clock1 input frequency 125 MHz 3–128 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 377 4 channels. Therefore, set the above field to 24 (rounded to the nearest transceiver block). For additional information on starting channel numbers and logical channel addressing, refer to “Introduction” on page 3–1. Altera Corporation 3–129 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 378 This section explains the steps to create all the MIFs at one time: Go to the Assignments menu and select Settings, then Fitter settings. Click the more settings button and set the Generate Stratix II GX GXB Reconfig MIF with PLL option to ON using the settings option (as shown in Figure 3–56).
Page 379 CH1, CH3, and CH5. Add the reset and user logic and connect the signals. In the assignment editor, use the Stratix II GX GXB TX PLL Reconfig group setting option and assign the tx_dataout of CH0 and CH1 to the same reconfig group (this is required to assign CH0 and CH1 to the same transceiver bank).
Page 380 MIF contents into the second TX PLL. Assume that the TX PLL configured for FC- 4G data rate is assigned a logical tx pll value of 0. This means that the other TX PLL configured for GIGE and SONET/SDH 3–132 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 381 40 (8b/10b encoder/decoder in the ALT2GXB is not used) what is the data rate 4250 Mbps what is the input clock frequency 106.25 MHz Altera Corporation 3–133 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 382 Transmitter what is deserializer block width double what is channel width (8b/10b in the ALT2GXB) 3–134 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 383 SONET/SDH which sub protocol you will be using OC48 what is the input clock frequency 77.76 MHz Reconfig Alt PLL Tab Settings Altera Corporation 3–135 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 384 CMU PLL Reconfiguration” on page 3–111 to create your MIFs. In the top-level design, assign the Stratix II GX GXB TX PLL Reconfig group setting and assign the same reconfig group to the three channels. If you would like to reconfigure CH0 to SONET/SDH OC48 mode, use...
Page 385 The adaptive equalization feature solves this problem by enabling the Stratix II GX device to continuously tune the receiver equalization settings based on the frequency content of the incoming signal. Five equalizer filters are tuned during this adaptive equalization process. The user logic can dynamically control the AEQ hardware through the dynamic reconfiguration controller.
Page 386 Enabling the AEQ Hardware The AEQ hardware is available for each transceiver channel in the Stratix II GX device. To enable the AEQ hardware, select the Enable adaptive equalizer control option in the Reconfig page of the ALT2GXB MegaWizard plug-in Manager (Figure 3–66).
Page 387 6 bits and 4 bits, respectively. If you have multiple transceiver instances, connect the least significant byte of the aeq_togxb[3:0] and aeq_fromgxb[5:0] ports between the ALT2GXB_RECONFIG and the transceiver channel Altera Corporation 3–139 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 388 (PIPE) protocol, the fixedclk is used to operate the receiver detect circuitry. In this protocol mode, fixedclk requires a fixed 125 MHz input clock frequency. The AEQ feature is not available in PCI-Express (PIPE) protocol mode. 3–140 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 389 You can select these options by setting different values in the reconfig_mode_sel[] port. To use these options, set the reconfig_mode_sel[] port to the corresponding value shown in Table 3–22. Altera Corporation 3–141 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 390 This results in transient bit errors on the parallel interface on the receive side. The ALT2GXB_RECONFIG de-asserts the busy signal after the write transaction is completed. 3–142 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 391 The number of reconfig_clk cycles required to complete the AEQ write operation in this mode is approximately 7,000 multiplied by the number of active channels. Altera Corporation 3–143 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 392 AEQ hardware in logical channel 4. When you perform a read operation using the PMA controls option, the translated manual equalization values are available in rx_eqctrl_out port in bits 19 down to 16, as shown in Figure 3–71. 3–144 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 393 0, 4, and 8, respectively. If only logical channels 4 and 8 have the AEQ feature enabled, when you use this option, the ALT2GXB_RECONFIG starts the Altera Corporation 3–145 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 394 In addition to controlling the AEQ hardware, ALT2GXB_RECONFIG supports multiple features; for example, PMA controls, channel reconfiguration, etc. Therefore, only one operation (selected by reconfig_mode_sel[]) can be performed at any given time. 3–146 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 395 Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook ■ Stratix II GX Transceiver Architecture Overview chapter (the Reset Control and Power Down section) in volume 2 of the Stratix II GX Handbook. Altera Corporation 3–147 October 2007...
Page 396 II GX Architecture Overview chapter to this chapter. Updated the “Introduction” and “Channel and — PMA Controls Reconfiguration” sections. Initial release of the “Channel and Clock Multiplier — Unit (CMU) PLL Reconfiguration” section. 3–148 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 397 4. Stratix II GX ALT2GXB Megafunction User Guide SIIGX52003-4.2 Introduction ® ® The MegaWizard Plug-In Manager in the Quartus II software creates or modifies design files that contain custom megafunction variations that can then be instantiated in a design file. The MegaWizard Plug-In Manager provides a MegaWizard that allows you to specify options for the ALT2GXB megafunction.
Page 398 Basic Mode Figure 4–2 shows the second page of the MegaWizard Plug-In Manager. Select the Stratix II GX device as the device family. Figure 4–2. MegaWizard Plug-In Manager (Page 2) Basic Mode This section provides descriptions of the options available on the individual pages of the ALT2GXB MegaWizard Plug-In Manager for Basic mode.
Page 399 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–3 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager in Basic mode. Figure 4–3. MegaWizard Plug-In Manager - ALT2GXB (General) Altera Corporation 4–3 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 400 What is the operation mode? The available operation modes are receiver only, transmitter only, and receiver and transmitter. What is the number of This option determines how many duplicate channels channels? this ALT2GXB instance contains. 4–4 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 401 Stratix II GX ALT2GXB Megafunction User Guide Table 4–1. MegaWizard Plug-In Manager Options (Page 3 for Basic Mode) (Part 2 of 3) ALT2GXB Setting Description Reference What is the deserializer This option sets the transceiver data path width. block width? ●...
Page 402 Stratix II GX Device Handbook. Create Transmitter digital reset port. Resets the PCS portion Reset Control and Power of the transmitter. Altera recommends using this port Down section in the tx_digitalreset port along with logic to implement the recommended reset Stratix II GX Transceiver sequence.
Page 403 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–4 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager for Basic mode. Figure 4–4. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports) Altera Corporation 4–7 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 404 Stratix II GX Transceiver Architecture Reset Control and Power Create gxb_powerdown Overview chapter in volume 2 of the Stratix II GX Down section in the port to power down the Device Handbook for information about this port. Stratix II GX Transceiver...
Page 405 Clock Multiplier Unit Create pll_locked port Overview chapter in volume 2 of the Stratix II GX section in the to indicate PLL is in lock with Device Handbook for information about this port. Stratix II GX Transceiver the reference input clock...
Page 406 PLD clock. Stratix II GX Transceiver of the TX phase Architecture Overview compensation FIFO chapter in volume 2 of the Stratix II GX Device Handbook. 4–10 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 407 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–5 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager for Basic mode. Figure 4–5. MegaWizard Plug-In Manager - ALT2GXB (RX Analog/Cal Blk) Altera Corporation 4–11 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 408 100 Ω , 120 Ω , and 150 Ω . termination resistance? in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–12 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 409 Create active low Refer to the Stratix II GX Transceiver Architecture Calibration Blocks Overview chapter in volume 2 of the Stratix II GX section in the cal_blk_powerdown Device Handbook for information about this port. Stratix II GX power down the calibration...
Page 410 Basic Mode Figure 4–6 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager for Basic mode. Figure 4–6. MegaWizard Plug-In Manager - ALT2GXB (TX Analog) 4–14 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 411 Stratix II GX ALT2GXB Megafunction User Guide Table 4–4 describes the available options on page 6 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–4. MegaWizard Plug-In Manager Options (Page 6 for Basic Mode) (Part 1 of 2)
Page 412 (% of V transmitter buffer using second post-tap. Figure 4–7 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager for Basic mode. Figure 4–7. MegaWizard Plug-In Manager - ALT2GXB (Reconfig) 4–16 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 413 Stratix II GX ALT2GXB Megafunction User Guide Table 4–5 describes the available options on page 7 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–5. MegaWizard Plug-In Manager Options (Page 7 for Basic Mode) ALT2GXB Setting...
Page 414 PLLs in its transceiver block. Reconfiguration The information regarding which PLL it listens to is chapter in volume 2 of stored in the MIF. the Stratix II GX Device Handbook. 4–18 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 415 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–9 shows page 9 of the ALT2GXB MegaWizard Plug-In Manager for Basic mode. This page appears only if the Channel Internals and the Enable Channel and Transmitter PLL Reconfiguration options are selected in the Reconfig page (Page 7).
Page 416 PLL, these Reconfiguration options allow you to instruct the MegaWizard about the chapter in volume 2 of the Stratix II GX Device REFCLK pre-divider on input reference clocks. Handbook. 4–20 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 417 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–10 shows page 10 of the ALT2GXB MegaWizard Plug-In Manager for Basic mode. This page appears only if the Channel Internals or the Channel Interface option is selected in the Reconfig page (Page 7).
Page 418 Stratix II GX Dynamic corresponding control port depending on what protocol(s) you intend to Reconfiguration dynamically reconfigure the transceiver to. chapter in volume 2 of the Stratix II GX Device Handbook. 4–22 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 419 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–11 shows page 11 of the MegaWizard Plug-In Manager for the Basic protocol mode set up. Figure 4–11. MegaWizard Plug-In Manager - ALT2GXB (Basic 1) Altera Corporation 4–23 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 420 Stratix II GX Transceiver double-width mode with the 8B/10B decoder. Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. What do you want the byte This option allows you to trigger the byte ordering Byte Ordering Block section in...
Page 421 Architecture Overview chapter pattern) identifies which group of skip patterns to use for in volume 2 of the Stratix II GX rate matching. If only one disparity is needed for Device Handbook. rate matching, you can enter the same pattern for both rate matching patterns (pattern1 and pattern2).
Page 422 Basic Mode Figure 4–12 shows page 12 of the MegaWizard Plug-In Manager for the Basic protocol mode set up. Figure 4–12. MegaWizard Plug-In Manager - ALT2GXB (Basic 2) 4–26 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 423 Stratix II GX ALT2GXB Megafunction User Guide Table 4–10 describes the available options on page 12 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–10. MegaWizard Plug-In Manager Options (Page 12 for Basic Mode) (Part 1 of 3)
Page 424 Architecture Overview chapter in volume 2 of the Stratix II GX Transceiver output port for pattern Stratix II GX Device Handbook for information Architecture Overview detector and word aligner about this port. chapter in volume 2 of the Stratix II GX Device Handbook.
Page 425 Stratix II GX ALT2GXB Megafunction User Guide Table 4–10. MegaWizard Plug-In Manager Options (Page 12 for Basic Mode) (Part 3 of 3) ALT2GXB Setting Description Reference Refer to the Stratix II GX Transceiver 8B/10B Decoder section in Create rx_ctrldetect Architecture Overview...
Page 426 The Generate Netlist option generates a netlist for the third party EDA synthesis tool to estimate timing and resource utilization for the ALT2GXB instance. Figure 4–13. MegaWizard Plug-In Manager - ALT2GXB (EDA) 4–30 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 427 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–14 shows page 14 (last page) of the MegaWizard Plug-In Manager for the Basic protocol mode set up. You can select optional files on this page. After you make your selections, click Finish to generate the files.
Page 428 Physical Interface for PCI-Express (PIPE) Mode Figure 4–15 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager for PIPE mode. Figure 4–15. MegaWizard Plug-In Manager - ALT2GXB (General) 4–32 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 429 Stratix II GX ALT2GXB Megafunction User Guide Table 4–11 describes the available options on page 3 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–11. MegaWizard Plug-In Manager Options (Page 3 for PIPE Mode) (Part 1 of 2)
Page 430 Receiver digital reset port. Resets the PCS portion Reset Control and Power Create rx_digitalreset of the receiver. Altera recommends using this port Down section in the port for the digital portion of along with logic to implement the recommended Stratix II GX Transceiver the receiver reset sequence.
Page 431 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–16 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager for PIPE mode. Figure 4–16. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports) Table 4–12 describes the available options on page 4 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation.
Page 432 Stratix II GX Transceiver Architecture Reset Control and Power gxb_powerdown Overview chapter in volume 2 of the Stratix II GX Down section in the to power down the Quad Device Handbook for information about this port. Stratix II GX Transceiver...
Page 433 Clock Recovery Unit Create rx_pll_locked port Overview chapter in volume 2 of the Stratix II GX section in the to indicate RX PLL is in lock with Device Handbook for information about this port. Stratix II GX Transceiver the reference clock...
Page 434 FIFO with a non-transceiver PLD clock. section in the TX phase compensation FIFO Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–38 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 435 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–17 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager for PIPE mode. Figure 4–17. MegaWizard Plug-In Manager - ALT2GXB (RX Analog/Cal Blk) Note (1) Note to Figure 4–17: If the equalizer DC gain is controlled by the ALT2GXB_RECONFIG controller, the rx_eqdcgain input to the ALT2GXB_RECONFIG controller should be tied to "01"...
Page 436 Stratix II GX (OCT). If checked, this option turns off the receiver Transceiver Architecture OCT. Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–40 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 437 Create active low Refer to the Stratix II GX Transceiver Architecture Calibration Blocks Overview chapter in volume 2 of the Stratix II GX section in the cal_blk_powerdown Device Handbook for information about this port. Stratix II GX Transceiver power down the calibration...
Page 438 Physical Interface for PCI-Express (PIPE) Mode Figure 4–18 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager for PIPE mode. Figure 4–18. MegaWizard Plug-In Manager - ALT2GXB (TX Analog) 4–42 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 439 Stratix II GX ALT2GXB Megafunction User Guide Table 4–14 describes the available options on page 6 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–14. MegaWizard Plug-In Manager Options (Page 6 for PIPE Mode) (Part 1 of 2)
Page 440 Figure 4–19 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager for PIPE mode. Figure 4–19. MegaWizard Plug-In Manager - ALT2GXB (Reconfig) 4–44 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 441 Stratix II GX ALT2GXB Megafunction User Guide Table 4–15 describes the available options on page 7 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–15. MegaWizard Plug-In Manager Options (Page 7 for PIPE Mode) ALT2GXB Setting...
Page 442 PLLs in its transceiver Reconfiguration block. The information regarding which PLL it chapter in volume 2 of listens to is stored in the MIF. the Stratix II GX Device Handbook. 4–46 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 443 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–21 shows page 9 of the ALT2GXB MegaWizard Plug-In Manager for PCI Express (PIPE) mode. This page appears only if the Channel Internals and the Enable Channel and Transmitter PLL Reconfiguration options are selected in the Reconfig page (Page 7).
Page 444 Reconfiguration these options allow you to instruct the MegaWizard chapter in volume 2 of the Stratix II GX Device about the pre-divider on input reference REFCLK Handbook. clocks. 4–48 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 445 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–22 shows page 10 of the MegaWizard Plug-In Manager for the PIPE protocol selection. This page appears only when the Channel Internals or Channel Interface options are selected in the Reconfig page (Page 7).
Page 446 Stratix II GX Dynamic corresponding control port depending on what protocol(s) you intend to Reconfiguration dynamically reconfigure the transceiver to. chapter in volume 2 of the Stratix II GX Device Handbook. 4–50 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 447 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–23 shows page 11 of the MegaWizard Plug-In Manager for the PIPE protocol selection. If the Enforce default settings for this protocol option is selected, this page does not appear in the MegaWizard.
Page 448 Architecture Overview chapter in volume 2 of Stratix II GX Transceiver the Stratix II GX Device Handbook for Architecture Overview word aligner information about this port. chapter in volume 2 of the Stratix II GX Device Handbook.
Page 449 Stratix II GX ALT2GXB Megafunction User Guide Table 4–19. MegaWizard Plug-In Manager Options (Page 11 for PIPE Mode) (Part 2 of 3) ALT2GXB Setting Description Reference Refer to the Stratix II GX Transceiver PIPE Mode section in the Create pipestatus...
Page 450 PIPE Mode section in the Architecture Overview chapter in volume 2 of Stratix II GX Transceiver tx_forcedispcompliance the Stratix II GX Device Handbook for Architecture Overview input port to force negative information about this port. chapter in volume 2 of the...
Page 451 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–24 shows page 12 of the MegaWizard Plug-In Manager for the PIPE protocol selection. The Generate simulation model creates a behavioral model (.vo or .vho) of the transceiver instance for third-party simulators. The Generate Netlist option generates a netlist for the third party EDA synthesis tool to estimate timing and resource utilization for the ALT2GXB instance.
Page 452 XAUI mode. The MegaWizard Plug-In Manager provides a warning if any of the settings you choose are illegal. The word aligner and rate matcher operations and patterns are pre-configured for the XAUI mode and cannot be altered. 4–56 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 453 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–26 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager for XAUI mode. Figure 4–26. MegaWizard Plug-In Manager - ALT2GXB (General) Table 4–20 describes the available options on page 3 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation.
Page 454 Receiver digital reset port. Resets the PCS portion Reset Control and Power Create rx_digitalreset of the receiver. Altera recommends using this port Down section in the port for the digital portion of along with logic to implement the recommended Stratix II GX Transceiver the receiver reset sequence.
Page 455 Stratix II GX ALT2GXB Megafunction User Guide Table 4–20. MegaWizard Plug-In Manager Options (Page 3 for XAUI Mode) (Part 3 of 3) ALT2GXB Setting Description Reference Transmitter digital reset port. Resets the PCS Reset Control and Power Create tx_digitalreset portion of the transmitter. Altera recommends using...
Page 456 Stratix II GX Transceiver Architecture Reset Control and Power Create port gxb_powerdown Overview chapter in volume 2 of the Stratix II GX Down section in the to power down the Quad Device Handbook for information about this port. Stratix II GX Transceiver Architecture Overview...
Page 457 Clock Multiplier Unit Create pll_locked port to Overview chapter in volume 2 of the Stratix II GX section in the indicate PLL is in lock with the Device Handbook for information about this port. Stratix II GX Transceiver reference input clock...
Page 458 FIFO with a non-transceiver PLD clock. section in the TX phase compensation FIFO Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–62 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 459 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–28 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager for XAUI mode. Figure 4–28. MegaWizard Plug-In Manager - ALT2GXB (RX Analog/Cal Blk) Altera Corporation 4–63 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 460 Stratix II GX termination (OCT). If checked, this option turns off Transceiver Architecture the receiver OCT. Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–64 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 461 Handbook. Create Refer to the Stratix II GX Transceiver Architecture Calibration Blocks section Overview chapter in volume 2 of the Stratix II GX in the Stratix II GX cal_blk_powerdown Device Handbook for information about this port. Transceiver Architecture power down the calibration...
Page 462 XAUI Mode Figure 4–29 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager for XAUI mode. Figure 4–29. MegaWizard Plug-In Manager - ALT2GXB (TX Analog) 4–66 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 463 Stratix II GX ALT2GXB Megafunction User Guide Table 4–23 describes the available options on page 6 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–23. MegaWizard Plug-In Manager Options (Page 6 for XAUI Mode) (Part 1 of 2)
Page 464 The amount of pre-emphasis is to be determined by characterization. Figure 4–30 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager for XAUI mode. Figure 4–30. MegaWizard Plug-In Manager - ALT2GXB (Reconfig) 4–68 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 465 Stratix II GX ALT2GXB Megafunction User Guide Table 4–24 describes the available options on page 7 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–24. MegaWizard Plug-In Manager Options (Page 7 for XAUI Mode) ALT2GXB Setting...
Page 466 XAUI Mode Figure 4–31 shows page 8 of the ALT2GXB MegaWizard Plug-In Manager for XAUI mode. Figure 4–31. MegaWizard Plug-In Manager - ALT2GXB (Loopback) 4–70 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 467 Stratix II GX ALT2GXB Megafunction User Guide Table 4–25 describes the available options on page 8 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–25. MegaWizard Plug-In Manager Options (Page 8 for XAUI Mode) ALT2GXB Setting...
Page 468 XAUI mode. If the Enforce default settings for this protocol option is selected, this page does not appear in the MegaWizard. Figure 4–32. MegaWizard Plug-In Manager - ALT2GXB (XAUI) 4–72 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 469 Stratix II GX ALT2GXB Megafunction User Guide Table 4–26 describes the available options on page 9 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–26. MegaWizard Plug-In Manager Options (Page 9 for XAUI Mode) (Part 1 of 2)
Page 470 Stratix II GX allow Transmitter polarity at the transmitter PCS-PMA interface. Transceiver Architecture inversion Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–74 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 471 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–33 shows page 10 of the MegaWizard Plug-In Manager for the XAUI protocol selection. The Generate simulation model creates a behavioral model (.vo or .vho) of the transceiver instance for third-party simulators. The Generate Netlist option generates a netlist for the third party EDA synthesis tool to be able to estimate timing and resource utilization for the ALT2GXB instance.
Page 472 GIGE mode. The MegaWizard Plug-In Manager provides a warning if any of the settings you choose are illegal. The word aligner and rate matcher operations and patterns are pre-configured for the GIGE mode and cannot be altered. 4–76 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 473 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–35 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager for GIGE mode. Figure 4–35. MegaWizard Plug-In Manager - ALT2GXB (General) Table 4–27 describes the available options on page 3 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation.
Page 474 Receiver digital reset port. Resets the PCS portion of Reset Control and Power Create rx_digitalreset the receiver. Altera recommends using this port along Down section in the port for the digital portion of with logic to implement the recommended reset...
Page 475 Stratix II GX ALT2GXB Megafunction User Guide Table 4–27. MegaWizard Plug-In Manager Options (Page 3 for GIGE Mode) (Part 3 of 3) ALT2GXB Setting Description Reference Receiver analog reset port. Reset Control and Power Create rx_analogreset Down section in the...
Page 476 GIGE Mode Figure 4–36 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager for GIGE mode. Figure 4–36. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports) 4–80 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 477 Stratix II GX Transceiver Architecture Reset Control and Power Create port gxb_powerdown Overview chapter in volume 2 of the Stratix II GX Down section in the to power down the Quad Device Handbook for information about this port. Stratix II GX Transceiver Architecture Overview...
Page 478 Clock Multiplier Unit Create pll_locked port to Overview chapter in volume 2 of the Stratix II GX section in the indicate PLL is in lock with the Device Handbook for information about this port. Stratix II GX Transceiver reference input clock...
Page 479 Stratix II GX ALT2GXB Megafunction User Guide Table 4–28. MegaWizard Plug-In Manager Options (Page 4 for GIGE Mode) (Part 3 of 3) ALT2GXB Setting Description Reference Create This optional output port indicates Receiver Phase Receiver Phase Compensation FIFO overflow/underrun condition.
Page 480 GIGE Mode Figure 4–37 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager for GIGE mode. Figure 4–37. MegaWizard Plug-In Manager - ALT2GXB (RX Analog/Cal Blk) 4–84 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 481 Stratix II GX ALT2GXB Megafunction User Guide Table 4–29 describes the available options on page 5 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–29. MegaWizard Plug-In Manager Options (Page 5 for GIGE Mode) (Part 1 of 2)
Page 482 Create Refer to the Stratix II GX Transceiver Architecture Calibration Blocks Overview chapter in volume 2 of the Stratix II GX section in the cal_blk_powerdown Device Handbook for information about this port. Stratix II GX Transceiver power down the calibration...
Page 483 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–38 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager for GIGE mode. Figure 4–38. MegaWizard Plug-In Manager - ALT2GXB (TX Analog) Altera Corporation 4–87 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 484 The amount in the Stratix II GX of pre-emphasis is to be determined by Transceiver Architecture characterization. Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–88 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 485 Stratix II GX ALT2GXB Megafunction User Guide Table 4–30. MegaWizard Plug-In Manager Options (Page 6 for GIGE Mode) (Part 2 of 2) ALT2GXB Setting Description Reference Pre-emphasis first post-tap This option sets the amount of pre-emphasis on setting (% of V the transmitter buffer using first post-tap.
Page 486 Stratix II GX Device The range of 0—156 is the logical channel address, Handbook. based purely on the number of possible ALT2GXB instances. 4–90 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 487 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–40 shows page 8 of the ALT2GXB MegaWizard Plug-In Manager for GIGE mode. This page appears only when the Channel Internals or Channel Interface options are selected in the Reconfig page (Page 7).
Page 488 GIGE mode. This page appears only if the Channel Internals and the Enable Channel and Transmitter PLL Reconfiguration options are selected on the Reconfig page (Page 7). Figure 4–41. MegaWizard Plug-In Manager - ALT2GXB (Reconfig Clks 1) 4–92 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 489 Stratix II GX ALT2GXB Megafunction User Guide Table 4–33 describes the available options on page 9 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–33. MegaWizard Plug-In Manager Options (Page 9 for GIGE Mode) ALT2GXB Setting...
Page 490 Manager for GIGE mode. This page appears only when the Channel Internals and Channel Interface options are selected in the Reconfig page (Page 7). Figure 4–42. MegaWizard Plug-In Manager - ALT2GXB (Reconfig 2) 4–94 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 491 Stratix II GX ALT2GXB Megafunction User Guide Table 4–34 describes the available options on page 10 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–34. MegaWizard Plug-In Manager Options (Page 10 for GIGE Mode) ALT2GXB Setting...
Page 492 GIGE Mode Figure 4–43 shows page 11 of the ALT2GXB MegaWizard Plug-In Manager for GIGE mode. Figure 4–43. MegaWizard Plug-In Manager - ALT2GXB (Loopback) 4–96 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 493 Stratix II GX ALT2GXB Megafunction User Guide Table 4–35 describes the available options on page 11 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–35. MegaWizard Plug-In Manager Options (Page 11 for GIGE Mode) ALT2GXB Setting...
Page 494 Manager for GIGE mode. If the Enforce default settings for this protocol option is selected, this page does not appear in the MegaWizard. Figure 4–44. MegaWizard Plug-In Manager - ALT2GXB (GIGE) 4–98 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 495 Stratix II GX Transceiver Architecture Word Aligner section in Create output rx_syncstatus Overview chapter in volume 2 of the Stratix II GX Stratix II GX port for pattern detector and Device Handbook for information about this port. Transceiver Architecture word aligner...
Page 496 Stratix II GX allow Transmitter polarity at the transmitter PCS-PMA interface. Transceiver Architecture inversion Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–100 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 497 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–45 shows page 13 of the MegaWizard Plug-In Manager for the GIGE protocol selection. The Generate simulation model creates a behavioral model (.vo or .vho) of the transceiver instance for third-party simulators. The Generate Netlist option generates a netlist for third party EDA synthesis tool to be able to estimate timing and resource utilization for the ALT2GXB instance.
Page 498 ALT2GXB MegaWizard Plug-In Manager for the Mode SONET/SDH mode. The MegaWizard Plug-In Manager provides a warning if any of the settings you choose are illegal. 4–102 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 499 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–47 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager for SONET/SDH mode. Figure 4–47. MegaWizard Plug-In Manager - ALT2GXB (General) Altera Corporation 4–103 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 500 This option is not used because the data rate is the setting on? fixed at: ● 622 Mbps for OC-12 ● 2488.32 Mbps for OC-48 ● 4976 Mbps for OC-96 4–104 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 501 Stratix II GX ALT2GXB Megafunction User Guide Table 4–37. MegaWizard Plug-In Manager Options (Page 3 for SONET/SDH Mode) (Part 2 of 2) ALT2GXB Setting Description Reference What is the data rate? This option is not used because the data rate is fixed at: ●...
Page 502 SONET/SDH Mode Figure 4–48 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager for SONET/SDH mode. Figure 4–48. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports) 4–106 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 503 Stratix II GX Transceiver Architecture Reset Control and Power Create port gxb_powerdown Overview chapter in volume 2 of the Stratix II GX Down section in the to power down the Quad Device Handbook for information about this port. Stratix II GX Transceiver Architecture Overview...
Page 504 Clock Multiplier Unit Create pll_locked port to Overview chapter in volume 2 of the Stratix II GX section in the indicate PLL is in lock with the Device Handbook for information about this port. Stratix II GX Transceiver reference input clock...
Page 505 Stratix II GX ALT2GXB Megafunction User Guide Table 4–38. MegaWizard Plug-In Manager Options (Page 4 for SONET/SDH Mode) (Part 3 of 3) ALT2GXB Setting Description Reference Create This optional output port indicates Receiver Phase Receiver Phase Compensation FIFO overflow/underrun condition.
Page 506 SONET/SDH Mode Figure 4–49 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager for SONET/SDH mode. Figure 4–49. MegaWizard Plug-In Manager - ALT2GXB (RX Analog/Cal Blk) 4–110 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 507 Stratix II GX ALT2GXB Megafunction User Guide Table 4–39 describes the available options on page 5 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–39. MegaWizard Plug-In Manager Options (Page 5 for SONET/SDH Mode) (Part 1 of 2)
Page 508 Create active low Refer to the Stratix II GX Transceiver Architecture Calibration Blocks Overview chapter in volume 2 of the Stratix II GX section in the cal_blk_powerdown Device Handbook for information about this port. Stratix II GX Transceiver power down the calibration...
Page 509 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–50 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager for SONET/SDH mode. Figure 4–50. MegaWizard Plug-In Manager - ALT2GXB (TX Analog) Altera Corporation 4–113 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 510 The amount in the Stratix II GX of pre-emphasis is to be determined by Transceiver Architecture characterization. Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–114 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 511 Stratix II GX ALT2GXB Megafunction User Guide Table 4–40. MegaWizard Plug-In Manager Options (Page 6 for SONET/SDH Mode) (Part 2 of 2) ALT2GXB Setting Description Reference Pre-emphasis first post-tap This option sets the amount of pre-emphasis on setting (% of V the transmitter buffer using first post-tap.
Page 512 Stratix II GX Device The range of 0—156 is the logical channel address, Handbook. based purely on the number of possible ALT2GXB instances. 4–116 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 513 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–52 shows page 8 of the ALT2GXB MegaWizard Plug-In Manager for SONET/SDH mode. This page appears only if the Channel Internals and the Enable Channel and Transmitter PLL Reconfiguration options are selected in the Reconfig page (Page 7).
Page 514 SONET/SDH mode. This page appears only if the Channel Internals and the Enable Channel and Transmitter PLL Reconfiguration options are selected in the Reconfig page (Page 7). Figure 4–53. MegaWizard Plug-In Manager - ALT2GXB (Reconfig Clks 1) 4–118 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 515 Stratix II GX ALT2GXB Megafunction User Guide Table 4–43 describes the available options on page 9 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–43. MegaWizard Plug-In Manager Options (Page 9 for SONET/SDH Mode) ALT2GXB Setting...
Page 516 Manager for SONET/SDH mode. This page appears only when the Channel Internals or Channel Interface options are selected in the Reconfig page (Page 7). Figure 4–54. MegaWizard Plug-In Manager - ALT2GXB (Reconfig 2) 4–120 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 517 Stratix II GX ALT2GXB Megafunction User Guide Table 4–44 describes the available options on page 10 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–44. MegaWizard Plug-In Manager Options (Page 10 for SONET/SDH Mode) ALT2GXB Setting...
Page 518 SONET/SDH Mode Figure 4–55 shows page 11 of the ALT2GXB MegaWizard Plug-In Manager for SONET/SDH mode. Figure 4–55. MegaWizard Plug-In Manager - ALT2GXB (Loopback) 4–122 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 519 Stratix II GX ALT2GXB Megafunction User Guide Table 4–45 describes the available options on page 11 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–45. MegaWizard Plug-In Manager Options (Page 11 for SONET/SDH Mode) ALT2GXB Setting...
Page 520 Manager for SONET/SDH mode. If the Enforce default settings for this protocol option is selected, this page does not appear in the MegaWizard. Figure 4–56. MegaWizard Plug-In Manager - ALT2GXB (SONET) 4–124 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 521 Stratix II GX ALT2GXB Megafunction User Guide Table 4–46 describes the available options on page 12 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–46. MegaWizard Plug-In Manager Options (Page 12 for SONET/SDH Mode) (Part 1 of 3)
Page 522 Stratix II GX Transceiver Architecture Word Aligner section in Create output rx_syncstatus Overview chapter in volume 2 of the Stratix II GX Stratix II GX port for pattern detector and Device Handbook for information about this port. Transceiver Architecture word aligner...
Page 523 Stratix II GX ALT2GXB Megafunction User Guide Table 4–46. MegaWizard Plug-In Manager Options (Page 12 for SONET/SDH Mode) (Part 3 of 3) ALT2GXB Setting Description Reference Flip Receiver output data bits This option reverses the bit order of the receiver...
Page 524 The Generate Netlist option generates a netlist for third party EDA synthesis tool to be able to estimate timing and resource utilization for the ALT2GXB instance. Figure 4–57. MegaWizard Plug-In Manager - ALT2GXB (EDA) 4–128 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 525 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–58 shows page 14 (the last page) of the MegaWizard Plug-In Manager for the SONET/SDH protocol set up. You can select optional files on this page. After you make your selections, click Finish to generate the files.
Page 526 Interface mode, you must select the (OIF) CEI PHY Interface protocol. Which subprotocol will you This option does not apply to the (OIF) CEI PHY be using? Interface mode. 4–130 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 527 Stratix II GX ALT2GXB Megafunction User Guide Table 4–47. MegaWizard Plug-In Manager Options (Page 3 for [OIF] CEI PHY Interface Mode) (Part 2 of 3) ALT2GXB Setting Description Reference Enforce default settings for If this option is checked, all (OIF) CEI PHY this protocol Interface-specific ports are used.
Page 528 Stratix II GX Transceiver the transmitter recommended reset sequence. Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–132 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 529 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–60 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager for (OIF) CEI PHY Interface mode. Figure 4–60. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports) Altera Corporation 4–133 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 530 Stratix II GX Transceiver Architecture Reset Control and Power Create port gxb_powerdown Overview chapter in volume 2 of the Stratix II GX Down section in the to power down the Quad Device Handbook for information about this port. Stratix II GX Transceiver Architecture Overview...
Page 531 Clock Multiplier Unit Create pll_locked port to Overview chapter in volume 2 of the Stratix II GX section in the indicate PLL is in lock with the Device Handbook for information about this port. Stratix II GX Transceiver reference input clock...
Page 532 FIFO with a non-transceiver PLD clock. Stratix II GX Transceiver TX phase compensation FIFO Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–136 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 533 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–61 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager for (OIF) CEI PHY Interface mode. Figure 4–61. MegaWizard Plug-In Manager - ALT2GXB (RX Analog/Cal Blk) Altera Corporation 4–137 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 534 Stratix II GX (OCT). If checked, this option turns off the receiver Transceiver Architecture OCT. Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–138 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 535 Create Refer to the Stratix II GX Transceiver Architecture Calibration Blocks Overview chapter in volume 2 of the Stratix II GX section in the cal_blk_powerdown Device Handbook for information about this port. Stratix II GX Transceiver power down the calibration...
Page 536 (OIF) CEI PHY Interface Mode Figure 4–62 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager for (OIF) CEI PHY Interface mode. Figure 4–62. MegaWizard Plug-In Manager - ALT2GXB (TX Analog) 4–140 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 537 Stratix II GX ALT2GXB Megafunction User Guide Table 4–50 describes the available options on page 6 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–50. MegaWizard Plug-In Manager Options (Page 6 for [OIF] CEI PHY Interface Mode) (Part 1 of 2)
Page 538 The amount of pre-emphasis is to be determined by characterization. Figure 4–63 shows page 7 of theALT2GXB MegaWizard Plug-In Manager for (OIF) CEI PHY Interface mode. Figure 4–63. MegaWizard Plug-In Manager - ALT2GXB (Reconfig) 4–142 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 539 Stratix II GX ALT2GXB Megafunction User Guide Table 4–51 describes the available options on page 7 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–51. MegaWizard Plug-In Manager Options (Page 7 for [OIF] CEI PHY Interface Mode)
Page 540 PLLs in its Reconfiguration chapter in transceiver block. The information regarding which volume 2 of the Stratix II PLL it listens to is stored in the MIF. GX Device Handbook. 4–144 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 541 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–65 shows page 9 of the ALT2GXB MegaWizard Plug-In Manager for (OIF) CEI PHY Interface mode. This page appears only if the Channel Internals and Enable Channel and Transmitter PLL Reconfiguration options are selected in the Reconfig page (Page 7).
Page 542 Reconfiguration chapter in these options allow you to instruct the volume 2 of the Stratix II GX Device Handbook. MegaWizard about the pre-divider on REFCLK input reference clocks. 4–146 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 543 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–66 shows page 10 of the MegaWizard Plug-In Manager for the (OIF) CEI PHY Interface protocol selection. This page appears only when the Channel Internals or Channel Interface option is selected in the Reconfig page (Page 7).
Page 544 Stratix II GX Dynamic corresponding control port depending on what protocol(s) you intend to Reconfiguration chapter in dynamically reconfigure the transceiver to. volume 2 of the Stratix II GX Device Handbook. 4–148 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 545 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–67 shows page 11 of the MegaWizard Plug-In Manager for the (OIF) CEI PHY Interface protocol selection. Figure 4–67. MegaWizard Plug-In Manager - ALT2GXB (Loopback) Altera Corporation 4–149 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 546 This option is not available in (OIF) CEI PHY Loopback Modes section in Interface mode. Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–150 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 547 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–68 shows the CEI page of the MegaWizard Plug In Manager for the (OIF) CEI PHY Interface protocol selection. If the Enforce default settings for this protocol option is selected, this page does not appear in the MegaWizard.
Page 548 EDA synthesis tool to be able to estimate timing and resource utilization for the ALT2GXB instance. Figure 4–69. MegaWizard Plug-In Manager - ALT2GXB (EDA) 4–152 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 549 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–70 shows page 14 (the last page) of the MegaWizard Plug-In Manager for the (OIF) CEI PHY Interface protocol set up. You can select optional files on this page. After you make your selections, click Finish to generate the files.
Page 550 For the CPRI mode, you must select the CPRI protocol. Which subprotocol will you This option is not available in CPRI mode. be using? 4–154 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 551 1. Architecture Overview A maximum of 16 CPRI channels can be chapter in volume 2 of the instantiated in the largest Stratix II GX device Stratix II GX Device (EP2SGX130G) due to clocking constraints. Handbook.
Page 552 Stratix II GX Transceiver the transmitter recommended reset sequence. Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–156 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 553 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–72 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager for CPRI mode. Figure 4–72. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports) Altera Corporation 4–157 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 554 Stratix II GX Transceiver Architecture Reset Control and Power Create port gxb_powerdown Overview chapter in volume 2 of the Stratix II GX Down section in the to power down the Quad Device Handbook for information about this port. Stratix II GX Transceiver Architecture Overview...
Page 555 Clock Multiplier Unit Create pll_locked port to Overview chapter in volume 2 of the Stratix II GX section in the indicate PLL is in lock with the Device Handbook for information about this port. Stratix II GX Transceiver reference input clock...
Page 556 FIFO with a non-transceiver PLD clock. Stratix II GX Transceiver TX phase compensation FIFO Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–160 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 557 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–73 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager for CPRI mode. Figure 4–73. MegaWizard Plug-In Manager - ALT2GXB (RX Analog/Cal Blk) Altera Corporation 4–161 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 558 Stratix II GX (OCT). If checked, this option turns off the receiver Transceiver Architecture OCT. Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–162 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 559 Create Refer to the Stratix II GX Transceiver Architecture Calibration Blocks Overview chapter in volume 2 of the Stratix II GX section in the cal_blk_powerdown Device Handbook for information about this port. Stratix II GX Transceiver power down the calibration...
Page 560 CPRI Mode Figure 4–74 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager for CPRI mode. Figure 4–74. MegaWizard Plug-In Manager - ALT2GXB (TX Analog) 4–164 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 561 Stratix II GX ALT2GXB Megafunction User Guide Table 4–59 describes the available options on page 6 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–59. MegaWizard Plug-In Manager Options (Page 6 for CPRI Mode) (Part 1 of 2)
Page 562 Figure 4–75 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager for CPRI mode. Figure 4–75. MegaWizard Plug-In Manager - ALT2GXB (Reconfig) 4–166 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 563 Stratix II GX ALT2GXB Megafunction User Guide Table 4–60 describes the available options on page 7 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–60. MegaWizard Plug-In Manager Options (Page 7 for CPRI Mode) ALT2GXB Setting...
Page 564 PLLs in its transceiver Reconfiguration block. The information regarding which PLL it chapter in volume 2 of listens to is stored in the MIF. the Stratix II GX Device Handbook. 4–168 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 565 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–77 shows page 9 of the ALT2GXB MegaWizard Plug-In Manager for CPRI mode. This page appears only if the Channel Internals and the Enable Channel and Transmitter PLL Reconfiguration options are selected on the Reconfig page (Page 7).
Page 566 PLL, these Reconfiguration chapter options allow you to instruct the MegaWizard about in volume 2 of the Stratix II GX Device Handbook. pre-divider on input reference clocks. REFCLK 4–170 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 567 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–78 shows page 10 of the ALT2GXB MegaWizard Plug-In Manager for CPRI mode. This page appears only when the Channel Internals or Channel Interface options are selected in the Reconfig page (Page 7).
Page 568 Stratix II GX Dynamic corresponding control port depending on what protocol(s) you intend to Reconfiguration chapter dynamically reconfigure the transceiver to. in volume 2 of the Stratix II GX Device Handbook. 4–172 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 569 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–79 shows page 11 of the ALT2GXB MegaWizard Plug-In Manager for CPRI mode. Figure 4–79. MegaWizard Plug-In Manager - ALT2GXB (Loopback) Altera Corporation 4–173 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 570 This option is not available in CPRI mode. Loopback Modes section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–174 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 571 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–80 shows page 12 of the ALT2GXB MegaWizard Plug-In Manager for CPRI mode. If the Enforce default settings for this protocol option is selected, this page does not appear in the MegaWizard.
Page 572 This option reverses the bit order of the data bits at the input of the transmitter at a byte level to support MSBit to LSBit transmission protocols. The default transmission order is LSBit to MSBit. 4–176 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 573 Stratix II GX ALT2GXB Megafunction User Guide Table 4–65. MegaWizard Plug-In Manager Options (Page 12 for CPRI Mode) (Part 2 of 2) ALT2GXB Setting Description Reference Enable Transmitter bit reversal This option inverts (flips) the bit order of the data...
Page 574 CPRI Mode Figure 4–81 shows page 13 of the ALT2GXB MegaWizard Plug-In Manager for CPRI mode. Figure 4–81. MegaWizard Plug-In Manager - ALT2GXB (CPRI 2) 4–178 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 575 Stratix II GX ALT2GXB Megafunction User Guide Table 4–66 describes the available options on page 13 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–66. MegaWizard Plug-In Manager Options (Page 13 for CPRI Mode) (Part 1 of 3)
Page 576 Stratix II GX Transceiver Architecture Word Aligner section in Create output rx_syncstatus Overview chapter in volume 2 of the Stratix II GX Stratix II GX port for pattern detector and Device Handbook for information about this port. Transceiver Architecture word aligner...
Page 577 Refer to the Stratix II GX Transceiver Architecture Word Aligner section in Create rx_patterndetect Overview chapter in volume 2 of the Stratix II GX Stratix II GX port to indicate pattern detected Device Handbook for information about this port. Transceiver Architecture Overview...
Page 578 The Generate Netlist option generates a netlist for third party EDA synthesis tool to be able to estimate timing and resource utilization for the ALT2GXB instance. Figure 4–82. MegaWizard Plug-In Manager - ALT2GXB (EDA) 4–182 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 579 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–83 shows page 15 (the last page) of the MegaWizard Plug-In Manager for the CPRI protocol set up. You can select optional files on this page. After you make your selections, click Finish to generate the files.
Page 580 SDI Mode Figure 4–84 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager for SDI mode. Figure 4–84. MegaWizard Plug-In Manager - ALT2GXB (General) 4–184 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 581 Stratix II GX ALT2GXB Megafunction User Guide Table 4–67 describes the available options on page 3 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–67. MegaWizard Plug-In Manager Options (Page 3 for SDI Mode) (Part 1 of 2)
Page 582 Receiver digital reset port. Resets the PCS portion Reset Control and Power Create rx_digitalreset of the receiver. Altera recommends using this port Down section in the port for the digital portion of along with logic to implement the recommended Stratix II GX Transceiver the receiver reset sequence.
Page 583 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–85 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager for SDI mode. Figure 4–85. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports) Altera Corporation 4–187 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 584 Stratix II GX Transceiver Architecture Reset Control and Power Create port gxb_powerdown Overview chapter in volume 2 of the Stratix II GX Down section in the to power down the Quad Device Handbook for information about this port. Stratix II GX Transceiver Architecture Overview...
Page 585 Clock Multiplier Unit Create pll_locked port to Overview chapter in volume 2 of the Stratix II GX section in the indicate PLL is in lock with the Device Handbook for information about this port. Stratix II GX Transceiver reference input clock...
Page 586 FIFO with a non-transceiver PLD clock. Stratix II GX Transceiver TX phase compensation FIFO Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–190 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 587 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–86 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager for SDI mode. Figure 4–86. MegaWizard Plug-In Manager - ALT2GXB (RX Analog/Cal Blk) Altera Corporation 4–191 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 588 Stratix II GX (OCT). If checked, this option turns off the receiver Transceiver Architecture OCT. Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–192 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 589 Create Refer to the Stratix II GX Transceiver Architecture Calibration Blocks Overview chapter in volume 2 of the Stratix II GX section in the cal_blk_powerdown Device Handbook for information about this port. Stratix II GX Transceiver power down the calibration...
Page 590 SDI Mode Figure 4–87 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager for SDI mode. Figure 4–87. MegaWizard Plug-In Manager - ALT2GXB (TX Analog) 4–194 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 591 Stratix II GX ALT2GXB Megafunction User Guide Table 4–70 describes the available options on page 6 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–70. MegaWizard Plug-In Manager Options (Page 6 for SDI Mode) (Part 1 of 2)
Page 592 Figure 4–75 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager for SDI mode. Figure 4–88. MegaWizard Plug-In Manager - ALT2GXB (Reconfig) 4–196 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 593 Stratix II GX ALT2GXB Megafunction User Guide Table 4–71 describes the available options on page 7 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–71. MegaWizard Plug-In Manager Options (Page 7 for SDI Mode) ALT2GXB Setting...
Page 594 PLLs in its transceiver Reconfiguration block. The information regarding which PLL it chapter in volume 2 of listens to is stored in the MIF. the Stratix II GX Device Handbook. 4–198 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 595 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–90 shows page 9 of the ALT2GXB MegaWizard Plug-In Manager for SDI mode. This page appears only if the Channel Internals and Enable Channel and Transmitter PLL Reconfiguration options are selected on the Reconfig page (Page 7).
Page 596 PLL, these Reconfiguration chapter options allow you to instruct the MegaWizard about in volume 2 of the Stratix II GX Device Handbook. pre-divider on input reference clocks. REFCLK 4–200 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 597 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–91 shows page 10 of the ALT2GXB MegaWizard Plug-In Manager for SDI mode. This page appears only when the Channel Internals or Channel Interface options are selected in the Reconfig page (Page 7).
Page 598 Stratix II GX Dynamic corresponding control port depending on what protocol(s) you intend to Reconfiguration chapter dynamically reconfigure the transceiver to. in volume 2 of the Stratix II GX Device Handbook. 4–202 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 599 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–92 shows page 11 of the ALT2GXB MegaWizard Plug-In Manager for SDI mode. Figure 4–92. MegaWizard Plug-In Manager - ALT2GXB (Loopback) Altera Corporation 4–203 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 600 This option is not available in SDI mode. Loopback Modes section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–204 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 601 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–93 shows page 12 of the ALT2GXB MegaWizard Plug-In Manager for SDI mode. If the Enforce default settings for this protocol option is selected, this page does not appear in the MegaWizard.
Page 602 This option reverses the bit order of the data bits at the input of the transmitter at a byte level to support MSBit to LSBit transmission protocols. The default transmission order is LSBit to MSBit. 4–206 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 603 Stratix II GX ALT2GXB Megafunction User Guide Table 4–76. MegaWizard Plug-In Manager Options (Page 12 for SDI Mode) (Part 2 of 2) ALT2GXB Setting Description Reference Enable Transmitter bit reversal This option inverts (flips) the bit order of the data...
Page 604 SDI Mode Figure 4–94 shows page 13 of the ALT2GXB MegaWizard Plug-In Manager for SDI mode. Figure 4–94. MegaWizard Plug-In Manager - ALT2GXB (SDI 2) 4–208 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 605 Stratix II GX ALT2GXB Megafunction User Guide Table 4–77 describes the available options on page 13 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–77. MegaWizard Plug-In Manager Options (Page 13 for SDI Mode) (Part 1 of 3)
Page 606 Stratix II GX Transceiver Architecture Word Aligner section in Create output rx_syncstatus Overview chapter in volume 2 of the Stratix II GX Stratix II GX port for pattern detector and Device Handbook for information about this port. Transceiver Architecture word aligner...
Page 607 Refer to the Stratix II GX Transceiver Architecture Word Aligner section in Create rx_patterndetect Overview chapter in volume 2 of the Stratix II GX Stratix II GX port to indicate pattern detected Device Handbook for information about this port. Transceiver Architecture Overview...
Page 608 The Generate Netlist option generates a netlist for third party EDA synthesis tool to be able to estimate timing and resource utilization for the ALT2GXB instance. Figure 4–95. MegaWizard Plug-In Manager - ALT2GXB (EDA) 4–212 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 609 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–83 shows page 15 (the last page) of the MegaWizard Plug-In Manager for the SDI protocol set up. You can select optional files on this page. After you make your selections, click Finish to generate the files.
Page 610 Which subprotocol will you This option is not available in Serial RapidIO mode. be using? Enforce default settings for This option is not available in Serial RapidIO mode. this protocol 4–214 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 611 Stratix II GX ALT2GXB Megafunction User Guide Table 4–78. MegaWizard Plug-In Manager Options (Page 3 for Serial RapidIO Mode) (Part 2 of 2) ALT2GXB Setting Description Reference What is the operation mode? The available operation modes are receiver only, transmitter only, and receiver and transmitter.
Page 612 Serial RapidIO Mode Figure 4–98 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager for Serial RapidIO mode. Figure 4–98. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports) 4–216 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 613 Stratix II GX Transceiver Architecture Reset Control and Power Create gxb_powerdown Overview chapter in volume 2 of the Stratix II GX Down section in the port to power down the Device Handbook for information about this port. Stratix II GX Transceiver...
Page 614 Clock Multiplier Unit Create pll_locked port Overview chapter in volume 2 of the Stratix II GX section in the to indicate PLL is in lock with Device Handbook for information about this port. Stratix II GX Transceiver the reference input clock...
Page 615 Stratix II GX ALT2GXB Megafunction User Guide Table 4–79. MegaWizard Plug-In Manager Options (Page 4 for Serial RapidIO Mode) (Part 3 of 3) ALT2GXB Setting Description Reference Create This optional output port indicates Receiver Phase Receiver Phase Compensation FIFO overflow/underrun condition.
Page 616 Serial RapidIO Mode Figure 4–99 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager for Serial RapidIO mode. Figure 4–99. MegaWizard Plug-In Manager - ALT2GXB (RX Analog/Cal Blk) 4–220 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 617 Stratix II GX ALT2GXB Megafunction User Guide Table 4–80 describes the available options on page 5 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–80. MegaWizard Plug-In Manager Options (Page 5 for Serial RapidIO Mode) (Part 1 of 2)
Page 618 Create active low Refer to the Stratix II GX Transceiver Architecture Calibration Blocks Overview chapter in volume 2 of the Stratix II GX section in the cal_blk_powerdown Device Handbook for information about this port. Stratix II GX power down the calibration...
Page 619 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–100 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager for Serial RapidIO mode. Figure 4–100. MegaWizard Plug-In Manager - ALT2GXB (TX Analog) Altera Corporation 4–223 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 620 Transmitter Buffer section setting (% of V transmitter buffer using pre-tap. in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. 4–224 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 621 Stratix II GX ALT2GXB Megafunction User Guide Table 4–81. MegaWizard Plug-In Manager Options (Page 6 for Serial RapidIO Mode) (Part 2 of 2) ALT2GXB Setting Description Reference Pre-emphasis first post-tap This option sets the amount of pre-emphasis on the setting (% of V transmitter buffer using first post-tap.
Page 622 The range of 0—156 is the Stratix II GX the logical channel address, based purely on the number Device Handbook. of possible ALT2GXB instances. 4–226 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 623 Stratix II GX ALT2GXB Megafunction User Guide Figure 4–102 shows page 8 of the ALT2GXB MegaWizard Plug-In Manager for Serial RapidIO mode. This page appears only if the Channel Internals and the Enable Channel and Transmitter PLL Reconfiguration option is selected in the Reconfig page (Page 7).
Page 624 Internals and the Enable Channel and Transmitter PLL Reconfiguration options are selected in the Reconfig page (Page 7). Figure 4–103. MegaWizard Plug-In Manager - ALT2GXB (Reconfig Clks 1) 4–228 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 625 Stratix II GX ALT2GXB Megafunction User Guide Table 4–84 describes the available options on page 9 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–84. MegaWizard Plug-In Manager Options (Page 9 for Serial RapidIO Mode) ALT2GXB Setting...
Page 626 Share a single transmitter core clock between Reconfiguration transmitters chapter in volume 2 of ● Use the respective channel transmitter core clocks the Stratix II GX Device Handbook. 4–230 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 627 Stratix II GX ALT2GXB Megafunction User Guide Table 4–85. MegaWizard Plug-In Manager Options (Page 10 for Serial RapidIO Mode) (Part 2 of 2) ALT2GXB Setting Description Reference Create This optional input port allows you to dynamically Word Aligner section in...
Page 628 Serial RapidIO Mode Figure 4–105 shows page 11 of the ALT2GXB MegaWizard Plug-In Manager for Serial RapidIO mode. Figure 4–105. MegaWizard Plug-In Manager - ALT2GXB (Loopback) 4–232 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 629 Stratix II GX ALT2GXB Megafunction User Guide Table 4–86 describes the available options on page 11 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–86. MegaWizard Plug-In Manager Options (Page 11 for Serial RapidIO Mode) ALT2GXB Setting...
Page 630 Serial RapidIO Mode Figure 4–106 shows page 12 of the MegaWizard Plug-In Manager for the Serial RapidIO protocol set up. Figure 4–106. MegaWizard Plug-In Manager - ALT2GXB (SR I/O 1) 4–234 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 631 This option is not available in Serial RapidIO Byte Ordering Block section in mode. Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook. Enable 8B/10B The 8B/10B decoder/encoder is always enabled 8B/10B Encoder section in the decoder/encoder in Serial RapidIO mode.
Page 632 Serial RapidIO Mode Figure 4–107 shows page 13 of the MegaWizard Plug-In Manager for the Serial RapidIO protocol set up. Figure 4–107. MegaWizard Plug-In Manager - ALT2GXB (SR I/O 2) 4–236 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 633 Stratix II GX ALT2GXB Megafunction User Guide Table 4–88 describes the available options on page 13 of the MegaWizard Plug-In Manager for your ALT2GXB custom megafunction variation. Table 4–88. MegaWizard Plug-In Manager Options (Page 13 for Serial RapidIO Mode) (Part 1 of 3)
Page 634 Architecture Overview chapter in volume 2 of the Stratix II GX Transceiver output port for pattern Stratix II GX Device Handbook for information Architecture Overview detector and word aligner about this port. chapter in volume 2 of the Stratix II GX Device Handbook.
Page 635 Stratix II GX ALT2GXB Megafunction User Guide Table 4–88. MegaWizard Plug-In Manager Options (Page 13 for Serial RapidIO Mode) (Part 3 of 3) ALT2GXB Setting Description Reference Refer to the Stratix II GX Transceiver 8B/10B Decoder section in Create rx_errdetect...
Page 636 The Generate Netlist option generates a netlist for the third party EDA synthesis tool to estimate timing and resource utilization for the ALT2GXB instance. Figure 4–108. MegaWizard Plug-In Manager - ALT2GXB (EDA) 4–240 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 637 Referenced This chapter references the following documents: Documents ■ Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook. ■ Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook.
Page 638 Updated “Reference” column in Table 4–2. Updated Figure 4–22. — Formerly chapter 3. The chapter number changed — due to the addition of the Stratix II GX Dynamic Reconfiguration chapter. February 2007 Added the “Document Revision History” section to —...
Page 639 Changes Made Summary of Changes Version December Added XAUI, GIGE, and SONET sections. — 2005, v2.0 October 2005 Added chapter to the Stratix II GX Device — v1.0 Handbook. Altera Corporation 4–243 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 640 Document Revision History 4–244 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 641 Stratix II GX ALT2GXB Megafunction User Guide Altera Corporation 4–245 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 642 Document Revision History 4–246 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 643 5. Stratix II GX ALT2GXB_RECONFIG Megafunction User Guide SIIGX52006-1.4 Introduction ® ® The MegaWizard Plug-In Manager in the Quartus II software creates or modifies design files that contain custom megafunction variations. These auto-generated MegaWizard files can then be instantiated in a design file.
Page 644 Select the following options (click Next when you are done): ■ ALT2GXB_RECONFIG megafunction option, under the I/O folder. ■ Stratix II GX as the device family. ■ Your desired type of output file format (Verilog, VHDL, or AHDL). ■ Your desired file name.
Page 645 Stratix II GX ALT2GXB_RECONFIG Megafunction User Guide Figure 5–3 shows page 3 of the ALT2GXB_RECONFIG MegaWizard Plug-In Manager. From the drop-down menu, select the number of channels controlled by the reconfig controller. Check off the reconfig controller features that you would like to activate; for example, Analog controls, Channel Reconfiguration, change the local divider values of the transmitter or Channel and TX PLL reconfiguration.
Page 646 The resource estimate is shown in the bottom left of page 3 of the MegaWizard. 5–4 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 647 Stratix II GX ALT2GXB_RECONFIG Megafunction User Guide Table 5–1. MegaWizard Plug-In Manager Options (Page 3) (Part 2 of 2) ALT2GXB_RECONFIG Setting Description Reference What are the features to be Three available selections are: Stratix II GX Dynamic reconfigured by the reconfig Analog Controls –...
Page 648 Table 5–2 describes the available options on page 4 of the MegaWizard Plug-In Manager for your ALT2GXB_RECONFIG custom megafunction variation. Make your selections on page 4 and click Next. 5–6 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 649 Stratix II GX ALT2GXB_RECONFIG Megafunction User Guide Table 5–2. MegaWizard Plug-In Manager Options (Page 4) (Part 1 of 2) ALT2GXB_RECONFIG Setting Description Reference Use the same control signal for Figure 5–4, this option is grayed out because it Dynamic Reconfiguration all channels (grayed out in is not applicable for a one-channel instance.
Page 650 The read out option enable is not independent of write control. Read and write cannot be performed simultaneously into these PMA read control signals and PMA write control signals. 5–8 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 651 Stratix II GX ALT2GXB_RECONFIG Megafunction User Guide Figure 5–5 shows page 5 of the ALT2GXB_RECONFIG MegaWizard Plug-In Manager. Page 5 appears only if Channel Reconfiguration is selected in the "What are the features to be reconfigured by the reconfig controller?" setting on page 3.
Page 652 When asserted, this optional control signal Stratix II GX Dynamic reset_reconfig_address resets the current reconfiguration address to 0. Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook. 5–10 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 653 2 of the Stratix II GX Device For more information, refer to the “Logical Handbook. TX PLL Select” section in the Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook. Altera Corporation 5–11...
Page 654 Table 5–4 describes the available options on page 6 of the MegaWizard Plug-In Manager for your ALT2GXB_RECONFIG custom megafunction variation. Make your selections on page 6 and click Next. 5–12 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 655 Stratix II GX ALT2GXB_RECONFIG Megafunction User Guide Table 5–4. MegaWizard Plug-In Manager Options (Page 6) ALT2GXB_RECONFIG Setting Description Reference Enable illegal mode checking When this option is selected, the Stratix II GX Dynamic ALT2GXB_RECONFIG MegaWizard provides the Reconfiguration chapter in volume 2 of output port.
Page 656 Generate a netlist for synthesis Selecting this option generates a netlist file that area and timing estimation third party synthesis tools can use to estimate the timing and resource usage 5–14 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 657 Figure 5–8. MegaWizard Plug-In Manager - ALT2GXB_RECONFIG (Summary) Referenced This chapter references the following document: Document ■ Stratix II GX Dynamic Reconfiguration chapter in volume 2 of the Stratix II GX Device Handbook Altera Corporation 5–15 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 658 April 2006, Updated all the MegaWizard Plug-In — v1.1 Manager figures to match the Quartus II software GUI. February 2006, Added chapter to the Stratix II GX Device — v1.0 Handbook. 5–16 Altera Corporation Stratix II GX Device Handbook, Volume 2...
Page 659 Table 6–1 shows the transceiver blocks for Stratix II GX and Stratix GX devices and compares their features. Blocks Table 6–1. Stratix II GX Features Versus Stratix GX Features (Part 1 of 2) Blocks Features Stratix GX Stratix II GX Data rate 500 Mbps to 3.1875 Gbps 600 Mbps to 6.375 Gbps...
Page 660 Transceiver Blocks Table 6–1. Stratix II GX Features Versus Stratix GX Features (Part 2 of 2) Blocks Features Stratix GX Stratix II GX Synchronization SM GIGE and XAUI only Available in Basic single-width, PIPE, XAUI, and GIGE modes 32-bit pattern...
Page 661 (abcdei) and a 4-bit sub-block (fghj), as shown in Figure 6–2. Figure 6–2. 10-Bit Grouping of 6-bit and 4-Bit Sub-Blocks 10-Bit Code 10-Bit Code D28.1 (3C hex) 4-Bit Block 4-Bit Block 6-Bit Block 6-Bit Block Altera Corporation 6–3 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 662 Table 6–2. Supported K Codes (Part 1 of 2) 8-Bit Code 10-Bit Code RD- 10-Bit Code RD+ K Code Octal Value HGF_EDCBA abcdei_fghj abcdei_fghj K28.0 8’b000_11100 10’b001111_0100 10’b110000_1011 K28.1 8’b001_11100 10’b001111_1001 10’b110000_0110 K28.2 8’b010_11100 10’b001111_0101 10’b110000_1010 6–4 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 663 D12.0 000 01100 001101 1011 001101 0100 D13.0 000 01101 101100 1011 101100 0100 D14.0 000 01110 011100 1011 011100 0100 D15.0 000 01111 010111 0100 101000 1011 Altera Corporation 6–5 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 664 D13.1 001 01101 101100 1001 101100 1001 D14.1 001 01110 011100 1001 011100 1001 D15.1 001 01111 010111 1001 101000 1001 D16.1 001 10000 011011 1001 100100 1001 6–6 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 665 D14.2 010 01110 011100 0101 011100 0101 D15.2 010 01111 010111 0101 101000 0101 D16.2 010 10000 011011 0101 100100 0101 D17.2 010 10001 100011 0101 100011 0101 Altera Corporation 6–7 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 666 D15.3 011 01111 010111 0011 101000 1100 D16.3 011 10000 011011 0011 100100 1100 D17.3 011 10001 100011 1100 100011 0011 D18.3 011 10010 010011 1100 010011 0011 6–8 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 667 D16.4 100 10000 011011 0010 100100 1101 D17.4 100 10001 100011 1101 100011 0010 D18.4 100 10010 010011 1101 010011 0010 D19.4 100 10011 110010 1101 110010 0010 Altera Corporation 6–9 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 668 D17.5 101 10001 100011 1010 100011 1010 D18.5 101 10010 010011 1010 010011 1010 D19.5 101 10011 110010 1010 110010 1010 D20.5 101 10100 001011 1010 001011 1010 6–10 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 669 D18.6 110 10010 010011 0110 010011 0110 D19.6 110 10011 110010 0110 110010 0110 D20.6 110 10100 001011 0110 001011 0110 D21.6 110 10101 101010 0110 101010 0110 Altera Corporation 6–11 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 670 D19.7 111 10011 110010 1110 110010 0001 D20.7 111 10100 001011 0111 001011 0001 D21.7 111 10101 101010 1110 101010 0001 D22.7 111 10110 011010 1110 011010 0001 6–12 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...
Page 671 ● Removed “Appendix” from chapter title. — 2005, v2.0 ● Updated Tables 5–1 and 5–2. October 2005 Added chapter to the Stratix II GX Device — v1.0 Handbook. Altera Corporation 6–13 October 2007 Stratix II GX Device Handbook, Volume 2...
Page 672 Document Revision History 6–14 Altera Corporation Stratix II GX Device Handbook, Volume 2 October 2007...

Altera Stratix II GX User Manual

Mode.

Reconfiguration Feature

Reconfig_Fromgxb

Logical_Tx_Pll_Sel_En

Quick Links

Chapters

Summary of Contents for Altera Stratix II GX

Page 2: Stratix Ii Gx Device Handbook, Volume

Page 3: Figure

Page 4: Figure

Page 10: Pipe Interface

Page 11: Revision History

Page 13: Altera Corporation October

Page 36: Table Of Contents

Page 38: Pcie Lane

Page 39: Pcie Lane

Page 40: Altera Corporation October

Page 46: Note To Figure

Page 49: Note To Figure

Page 50: October

Page 110: Rate Matcher

Page 144: Bank

Page 219: Reverse Serial Loopback

Page 221: Parallel Loopback

Page 256: Reconfig_Clk

Page 261: Logical_Tx_Pll_Sel

Altera Stratix II GX User Manual

Mode.

Reconfiguration Feature

Reconfig_Fromgxb

Logical_Tx_Pll_Sel_En

Quick Links

Chapters

Related Manuals for Altera Stratix II GX

Summary of Contents for Altera Stratix II GX

Table of Contents