Altera UG-01080 Transceiver PHY IP Manuals

Manuals and User Guides for Altera UG-01080 Transceiver PHY IP. We have 1 Altera UG-01080 Transceiver PHY IP manual available for free PDF download: User Manual

Altera UG-01080 User Manual (702 pages)

Transceiver PHY IP Core

Brand: Altera | Category: Transceiver | Size: 4.82 MB

Table of Contents
2
Introduction to the Protocol-Specific and Native Transceiver Phys

12
Getting Started Overview

21
- Installation and Licensing of IP Cores
  21
- Design Flows
  22
- Megawizard Plug-In Manager Flow
  23
  - Specifying Parameters
    23
  - Simulate the IP Core
    24
10GBASE-R PHY IP Core

25
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option

57
1G/10 Gbps Ethernet PHY IP Core

110
- 1G/10Gbe PHY Release Information
  111
- Device Family Support
  112
- 1G/10 Gbe PHY Performance and Resource Utilization
  112
- Parameterizing the 1G/10Gbe PHY
  113
- 1Gbe Parameters
  113
- Speed Detection Parameters
  114
- PHY Analog Parameters
  115
- 1G/10Gbe PHY Interfaces
  116
- 1G/10Gbe PHY Clock and Reset Interfaces
  117
- 1G/10Gbe PHY Data Interfaces
  118
- XGMII Mapping to Standard SDR XGMII Data
  120
- Serial Data Interface
  121
- 1G/10Gbe Control and Status Interfaces
  121
- Register Interface Signals
  123
- 1G/10Gbe PHY Register Definitions
  124
- PMA Registers
  125
- PCS Registers
  126
- 1G/10 Gbe GMII PCS Registers
  127
- PMA Registers
  129
- 1G/10Gbe Dynamic Reconfiguration from 1G to 10Gbe
  130
- 1G/10Gbe PHY Arbitration Logic Requirements
  131
- 1G/10Gbe PHY State Machine Logic Requirements
  132
- Editing a 1G/10Gbe MIF File
  132
- Creating a 1G/10Gbe Design
  133
- Dynamic Reconfiguration Interface Signals
  134
- 10 Gbps Ethernet PHY IP Core
  136
- Design Example
  138
- Simulation Support
  139
- Timequest Timing Constraints
  139
- Acronyms
  139
XAUI PHY IP Core

141
Interlaken PHY IP Core

168
PHY IP Core for PCI Express (PIPE)

189
Custom PHY IP Core

214
- Device Family Support
  215
- Performance and Resource Utilization
  215
- Parameterizing the Custom PHY
  216
  - General Options Parameters
    216
  - Word Alignment Parameters
    220
  - Rate Match FIFO Parameters
    222
  - 8B/10B Encoder and Decoder Parameters
    223
  - Byte Order Parameters
    224
  - PLL Reconfiguration Parameters
    227
  - Analog Parameters
    229
  - Presets for Ethernet
    229
- Interfaces
  232
  - Data Interfaces
    232
  - Clock Interface
    236
  - Optional Status Interface
    237
  - Optional Reset Control and Status Interface
    239
  - Register Interface and Register Descriptions
    240
  - Custom PHY IP Core Registers
    242
  - SDC Timing Constraints
    246
  - Dynamic Reconfiguration
    246
Low Latency PHY IP Core

248
- Device Family Support
  249
- Performance and Resource Utilization
  249
- Parameterizing the Low Latency PHY
  250
- General Options Parameters
  251
- Additional Options Parameters
  254
- PLL Reconfiguration Parameters
  257
- Low Latency PHY Analog Parameters
  259
- Low Latency PHY Interfaces
  260
- Low Latency PHY Data Interfaces
  260
- Optional Status Interface
  262
- Low Latency PHY Clock Interface
  262
- Optional Reset Control and Status Interface
  263
- Register Interface and Register Descriptions
  264
- Dynamic Reconfiguration
  266
- SDC Timing Constraints
  267
- Simulation Files and Example Testbench
  268
Deterministic Latency PHY IP Core

269
Stratix V Transceiver Native PHY IP Core

299
Arria V Transceiver Native PHY IP Core

376
- Device Family Support
  377
- Performance and Resource Utilization
  378
- Parameterizing the Arria V Native PHY
  378
- General Parameters
  378
- PMA Parameters
  379
  - TX PMA Parameters
    380
  - TX PLL Parameters
    381
  - RX PMA Parameters
    383
- Standard PCS Parameters
  385
  - Phase Compensation FIFO
    387
  - Byte Ordering Block Parameters
    388
  - Byte Serializer and Deserializer
    389
  - 8B/10B
    390
  - Rate Match FIFO
    390
  - Word Aligner and Bitslip Parameters
    393
  - Bit Reversal and Polarity Inversion
    395
- Interfaces
  398
  - Common Interface Ports
    398
  - Standard PCS Interface Ports
    404
- SDC Timing Constraints
  409
- Dynamic Reconfiguration
  410
- Simulation Support
  411
Arria V GZ Transceiver Native PHY IP Core

412
Cyclone V Transceiver Native PHY IP Core Overview

484
- Cyclone Device Family Support
  485
- Cyclone V Native PHY Performance and Resource Utilization
  485
- Parameterizing the Cyclone V Native PHY
  485
- General Parameters
  486
- PMA Parameters
  487
  - TX PMA Parameters
    488
  - TX PLL Parameters
    489
  - RX PMA Parameters
    490
- Standard PCS Parameters
  492
  - Phase Compensation FIFO
    494
  - Byte Ordering Block Parameters
    495
  - Byte Serializer and Deserializer
    497
  - 8B/10B
    497
  - Rate Match FIFO
    498
  - Word Aligner and Bitslip Parameters
    501
  - Bit Reversal and Polarity Inversion
    503
- Interfaces
  505
  - Common Interface Ports
    505
  - Cyclone V Standard PCS Interface Ports
    511
- SDC Timing Constraints
  515
- Dynamic Reconfiguration
  516
- Simulation Support
  517
Transceiver Reconfiguration Controller IP Core Overview

518
Transceiver PHY Reset Controller IP Core

578
Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices

590
- Parameterizing the Transceiver PLL PHY
  592
- Transceiver PLL Parameters
  592
- Transceiver PLL Signals
  593
Analog Parameters Set Using QSF Assignments

595
Migrating from Stratix IV to Stratix V Devices Overview

647
Additional Information for the Transceiver PHY IP Core

662
- Revision History for Previous Releases of the Transceiver PHY IP Core
  666
- How to Contact Altera
  702

Altera Categories

Motherboard Microcontrollers Computer Hardware Transceiver Media Converter

More Altera Manuals

Altera UG-01080 Transceiver PHY IP Manuals

Altera UG-01080 User Manual (702 pages)

Table of Contents

Introduction to the Protocol-Specific and Native Transceiver Phys

Getting Started Overview

10GBASE-R PHY IP Core

Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option

1G/10 Gbps Ethernet PHY IP Core

XAUI PHY IP Core

Interlaken PHY IP Core

PHY IP Core for PCI Express (PIPE)

Custom PHY IP Core

Low Latency PHY IP Core

Deterministic Latency PHY IP Core

Stratix V Transceiver Native PHY IP Core

6/×N Bonded Clocking

Arria V Transceiver Native PHY IP Core

Arria V GZ Transceiver Native PHY IP Core

Cyclone V Transceiver Native PHY IP Core Overview

Transceiver Reconfiguration Controller IP Core Overview

Transceiver PHY Reset Controller IP Core

Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices

Analog Parameters Set Using QSF Assignments

Migrating from Stratix IV to Stratix V Devices Overview

Additional Information for the Transceiver PHY IP Core

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Altera Categories