Altera PHY IP Core User Manual page 154

9–12
Table 9–10. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3)
QSF Assignment Name
XCVR_RX_LINEAR_EQUALIZER_
CONTROL
XCVR_RX_COMMON_MODE_
VOLTAGE
XCVR_RX_ENABLE_LINEAR_
EQUALIZER_PCIEMODE
XCVR_RX_EQ_BW_SEL
XCVR_RX_SD_ENABLE
XCVR_RX_SD_OFF
XCVR_RX_SD_ON
XCVR_RX_SD_THRESHOLD
Altera Transceiver PHY IP Core
User Guide
Pin Planner and
Assignment Editor
Name
Static control for the continuous time
equalizer in the receiver buffer. The
Receiver Linear Equalizer
equalizer has 16 distinct settings from
Control
0 –15 corresponding to the increasing
AC gain.
Analog Parameter with Computed Default Value
Receiver Buffer Common Receiver buffer common-mode
Mode Voltage voltage.
If enabled equalizer gain control is
driven by the PCS block for PCI
Receiver Linear Equalizer Express. If disabled equalizer gain
Control (PCI Express) control is determined by the
XCVR_RX_LINEAR_EQUALIZER_SETT
ING assignment.
Sets the gain peaking frequency for the
Receiver Equalizer Gain equalizer. For data-rates of less than
Bandwidth Select 6.5Gbps set to HALF. For higher data-
rates set to FULL.
Receiver Signal Detection Enables or disables the receiver signal
Unit Enable/Disable detection unit.
Receiver Cycle Count Number of parallel cycles to wait
Before Signal Detect Block before the signal detect block declares
Declares Loss Of Signal loss of signal.
Number of parallel cycles to wait
Receiver Cycle Count Before
Signal Detect Block Declares before the signal detect block declares
Presence Of Signal
presence of signal.
Receiver Signal Detection Specifies signal detection voltage
Voltage Threshold threshold level.
Chapter 9: Deterministic Latency PHY IP Core
Description
VTT_0P80V
VTT_0P75V
VTT_0P70V
VTT_0P65V
VTT_0P60V
VTT_0P55V
VTT_0P50V
VTT_0P35V
VTT_PUP
VTT_PDN
TRISTATE1
VTT_PDN_
STRONG
VTT_PUP_
STRONG
TRISTATE2
TRISTATE3
TRISTATE4
March 2012 Altera Corporation
Parameter Settings
Options Assign To
1 –16 Pin
_WEAK
Pin
WEAK
TRUE
Pin
FALSE
FULL
Pin
HALF
TRUE
Pin
FALSE
Pin
0–29
Pin
0–16
Pin
0 –7