Altera PHY IP Core User Manual page 152

9–10
Table 9–9
place holders for the values that match your electrical board specification. In
Table
Table 9–9. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 2)
QSF Assignment Name
XCVR_IO_PIN_TERMINATION
XCVR_REFCLK_PIN_
TERMINATION
XCVR_RX_BYPASS_EQ_
STAGES_234
XCVR_TX_SLEW_RATE_CTRL
Altera Transceiver PHY IP Core
User Guide
lists the analog parameters for Stratix V devices whose original values are
9–9, the default value of an analog parameter is shown in bold type.
Pin Planner and
Assignment Editor
Name
Specifies the intended on-chip
termination value for the specified
Transceiver I/O Pin
transceiver pin. Use External Resistor
Termination
if you intend to use off-chip
termination.
Transceiver Dedicated Specifies the intended termination
Refclk Pin Termination value for the specified refclk pin.
Bypass continuous time equalizer
stages 2, 3, and 4 to save power. This
Receiver Equalizer Stage 2, setting eliminates significant AC gain
3, 4 Bypass on the equalizer and is appropriate for
chip-to-chip short range
communication on a PCB.
Specifies the slew rate of the output
Transmitter Slew Rate signal. The valid values span from the
Control slowest rate to fastest rate with 1
representing the slowest rate.
Chapter 9: Deterministic Latency PHY IP Core
Description
100_OHMS
120_OHMS
150_OHMS
EXTERNAL_
RESISTOR
DC_COUPLING_
INTERNAL_100
DC_COUPLING_
EXTERNAL_
RESISTOR
AC_COUPLING
ALL_STAGES_
March 2012 Altera Corporation
Parameter Settings
Assign
Options
To
85_OHMS
Pin
_OHM
Pin
ENABLED
Pin
BYPASS_
STAGES
Pin
1–5