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Altera PHY IP Core User Manual

Altera PHY IP Core User Manual

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Altera Transceiver PHY IP Core User Guide
Altera Transceiver PHY IP Core

User Guide

101 Innovation Drive
San Jose, CA 95134
www.altera.com
Document last updated for Altera Complete Design Suite version:
11.1 SP2
UG-01080-1.6
Document publication date:
March 2012
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Summary of Contents for Altera PHY IP Core

  • Page 1: User Guide

    Altera Transceiver PHY IP Core User Guide Altera Transceiver PHY IP Core User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Document last updated for Altera Complete Design Suite version: 11.1 SP2 UG-01080-1.6 Document publication date: March 2012 Feedback Subscribe...
  • Page 2 © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.

  • Page 3: Table Of Contents

    Simulate the IP Core ..............2–4 Chapter 3. 10GBASE-R PHY IP Core Release Information .
  • Page 4 Simulation Files and Example Testbench ..........5–16 Chapter 6. PHY IP Core for PCI Express (PIPE) Device Family Support .
  • Page 5 Simulation Files and Example Testbench ..........7–24 Chapter 8. Low Latency PHY IP Core Device Family Support .
  • Page 6 Streamer Based Reconfiguration ........... . 10–28 March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...
  • Page 7 Understanding Logical Channel Numbering ..........10–31 Two PHY IP Core Instances Each with Four Bonded Channels ......10–34 One PHY IP Core Instance with Eight Bonded Channels .
  • Page 8 Contents Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...

  • Page 9: Chapter 1. Introduction

    1. Introduction The Altera ® Transceiver PHY IP Core User Guide describes the following protocol-specific PHYs: 10GBASE-R PHY IP Core ■ ■ XAUI PHY IP Core ■ Interlaken PHY IP Core ■ PHY IP Core for PCI Express (PIPE) Custom PHY IP Core ■...

  • Page 10: Pcs

    PHY IP cores. In addition, Figure 1–1 shows the Altera Transceiver Reconfiguration Controller IP core that is instantiated separately in Stratix V devices. Figure 1–1. Altera Modular PHY Design Stratix V Device...

  • Page 11: Pma

    CDR logic for each RX channel. Reset Controller A transceiver reset controller is included as part of each PHY IP core. This embedded reset controller ensures reliable transceiver link initialization. The reset controller initializes the both the TX and RX channels. You can disable the automatic reset controller in the Custom and Low Latency Transceiver PHYs.

  • Page 12: Running A Simulation Testbench

    Running a Simulation Testbench Running a Simulation Testbench When you generate your transceiver PHY IP core, the Quartus II software generates the HDL files that define your parameterized IP core. In addition, the Quartus II software generates an example Tcl script to compile and simulate your design in ModelSim.

  • Page 13: Unsupported Features

    The transceiver PHY IP cores do not support the NativeLink feature in the Quartus II software. Unsupported Features The protocol-specific PHYs are not supported in SOPC Builder or Qsys in the current release. March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...
  • Page 14 1–6 Chapter 1: Introduction Unsupported Features Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...

  • Page 15: Chapter 2. Getting Started

    This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera IP core. The Altera IP Library is installed as part of the Quartus II installation process. You can select and parameterize any Altera IP core from the library.

  • Page 16: Megawizard Plug-In Manager Flow

    Figure 2–2: (1) Altera IP cores may or may not support the Qsys and SOPC Builder design flows. The MegaWizard Plug-In Manager flow offers the following advantages: Allows you to parameterize an IP core variant and instantiate into an existing ■...
  • Page 17 Tools menu, and follow the prompts in the MegaWizard Plug-In Manager interface to create or edit a custom IP core variation. 3. To select a specific Altera IP core, click the IP core in the Installed Plug-Ins list in the MegaWizard Plug-In Manager.

  • Page 18: Simulate The Ip Core

    For a complete list of models or libraries required to simulate your IP core, refer to the scripts provided with the testbench. For more information about simulating Altera IP cores, refer to Simulating Altera Designs in volume 3 of the Quartus II Handbook.
  • Page 19 10GBASE-R PHY IP core operates independently. Figure 3–1 shows the 10GBASE-R PHY IP core available for Stratix V devices. Both the PCS and PMA of the 10GBASE-R PHY are implemented as hard IP blocks in Stratix V devices, saving FPGA resources.

  • Page 20: Chapter 3. 10Gbase-R Phy Ip Core

    Bridge Avalon-MM connections Transceiver Reconfig Controller Release Information Table 3–1 provides information about this release of the 10GBASE-R PHY IP core. Table 3–1. 10GBASE-R Release Information (Part 1 of 2) Item Description Version 11.1 Release Date November 2011 IP-10GBASERPCS (primary)

  • Page 21: Device Family Support

    (1) No ordering codes or license files are required for Stratix V devices. Device Family Support IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: Final support—Verified with final timing models for this device.

  • Page 22: Stratix V Devices

    “Low Latency PHY IP Core” Parameter Settings To configure the 10GBASE-R PHY IP core in the parameter editor, click Installed Plug-Ins > Interfaces >Ethernet> 10GBASE-R PHY v11.1. The 10GBASE-R PHY IP core is available for the Stratix IV or Stratix V device family.

  • Page 23: Analog Options

    For Stratix IV devices, if you turn this option on, the PMA controller and reconfiguration block are external, rather than included 10GBASE-R PHY IP core, allowing you to use the same PMA Use external PMA control and controller and reconfiguration IP cores for other protocols in the...

  • Page 24: Stratix V Devices

    Proxy—These parameters have default values that are place holders. The Quartus II software selects these initial default values based on your design; however, Altera recommends that you replace these defaults with values that match your electrical board specification. Altera Transceiver PHY IP Core...
  • Page 25 Chapter 3: 10GBASE-R PHY IP Core 3–7 Parameter Settings Table 3–7 lists the analog parameters for Stratix V devices whose original values are place holders for the values that match your electrical board specification. In Table 3–7, the default value of an analog parameter is shown in bold type.
  • Page 26 3–8 Chapter 3: 10GBASE-R PHY IP Core Parameter Settings Table 3–7. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 2) Pin Planner and Assign QSF Assignment Name Assignment Editor Description Options Name Configure the VCCA_GXB voltage for a GXB I/O pin by specifying the intended VCCA_GXB voltage for a GXB I/O pin.
  • Page 27 Chapter 3: 10GBASE-R PHY IP Core 3–9 Parameter Settings Table 3–8. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3) Pin Planner and QSF Assignment Name Assignment Editor Description Options Assign To Name Static control for the continuous time equalizer in the receiver buffer.
  • Page 28 3–10 Chapter 3: 10GBASE-R PHY IP Core Parameter Settings Table 3–8. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3) Pin Planner and QSF Assignment Name Assignment Editor Description Options Assign To Name VOLT_0P80V VOLT_0P75V VOLT_0P70V VOLT_0P65V...

  • Page 29: Interfaces

    Assignment Editor in Quartus II Help. For more information about Quartus II Settings, refer to Quartus II Settings File Manual. Interfaces This section describes interfaces of the 10GBASE-R PHY IP Core. It includes the following topics: Ports ■ Register Interface ■...

  • Page 30: Sdr Xgmii Tx Interface

    3–12 Chapter 3: 10GBASE-R PHY IP Core Interfaces SDR XGMII TX Interface Table 3–9 describes the signals in the SDR XGMII TX interface. These signals are driven from the MAC to the PCS. This is an Avalon-ST sink interface. Table 3–9. SDR XGMII TX Inputs...

  • Page 31: Sdr Xgmii Rx Interface

    Chapter 3: 10GBASE-R PHY IP Core 3–13 Interfaces Table 3–10. Mapping from XGMII TX Bus to XGMII SDR Bus (Part 2 of 2) Signal Name XGMII Signal Name Description Lane 5 control xgmii_tx_dc[53] xgmii_sdr_ctrl[5] Lane 6 data xgmii_tx_dc[61:54] xgmii_sdr_data[55:48] Lane 6 control...

  • Page 32: Status Interface

    3–14 Chapter 3: 10GBASE-R PHY IP Core Interfaces Table 3–12 provides the mapping from the XGMII RX interface to the XGMII SDR interface. Table 3–12. Mapping from XGMII RX Bus to the XGMII SDR Bus Signal Name XGMII Signal Name...
  • Page 33 Chapter 3: 10GBASE-R PHY IP Core 3–15 Interfaces The PCS runs at 257.8125 MHz using the pma_rx_clock provided by the PMA. You must provide the PMA a input reference clock running at 644.53725 MHz to generate the 257.8125 MHz clock.
  • Page 34 3–16 Chapter 3: 10GBASE-R PHY IP Core Interfaces Figure 3–5 illustrates the clock generation and distribution for Stratix V devices. Figure 3–5. Stratix V Clock Generation and Distribution 10GBASE-R Hard IP Transceiver Channel - Stratix V 10.3125 Gbps serial TX PCS...

  • Page 35: Serial Interface

    Chapter 3: 10GBASE-R PHY IP Core 3–17 Interfaces Serial Interface Table 3–15 describes the input and outputs of the transceiver. Table 3–15. Transceiver Serial Interface Signal Name Direction Description Differential high speed serial input data using the PCML I/O standard.

  • Page 36: Register Descriptions

    3–18 Chapter 3: 10GBASE-R PHY IP Core Interfaces Register Descriptions Table 3–17 specifies the registers that you can access over the Avalon-MM PHY management interface using word addresses and a 32-bit embedded processor. A single address space provides access to all registers.
  • Page 37 Chapter 3: 10GBASE-R PHY IP Core 3–19 Interfaces Table 3–17. 10GBASE-R Register Descriptions (Part 2 of 3) Word Name Description Addr You can use the reset_fine_control register to create your own reset sequence. The reset control module, illustrated in Figure 1–1 on page 1–2, performs a standard...

  • Page 38: Dynamic Reconfiguration

    Dynamic Reconfiguration for Stratix IV Devices Table 3–18 describes the additional top-level signals 10GBASE-R PHY IP core when the configuration includes external modules for PMA control and reconfiguration. You enable this configuration by turning on Use external PMA control and reconfig available for Stratix IV GT devices.

  • Page 39: Dynamic Reconfiguration For Stratix V Devices

    Chapter 3: 10GBASE-R PHY IP Core 3–21 Interfaces Table 3–18. External PMA and Reconfiguration Signals (Part 2 of 2) Signal Name Direction Description Input When asserted, powers down the calibration block. Active high. cal_blk_pdn Calibration clock. For Stratix IV devices only. It must be in the range...

  • Page 40: Timequest Timing Constraints

    3–22 Chapter 3: 10GBASE-R PHY IP Core TimeQuest Timing Constraints Although you must initially create a separate reconfiguration interface for each channel and TX PLL in your design, when the Quartus II software compiles your design, it reduces the number of reconfiguration interfaces by merging reconfiguration interfaces.
  • Page 41 Chapter 3: 10GBASE-R PHY IP Core 3–23 TimeQuest Timing Constraints Synopsys Design Constraints for Clocks (Continued) #************************************************************** # Create Generated Clocks #************************************************************** create_generated_clock -name pll_mac_clk -source [get_pins -compatibility_mode {*altpll_component|auto_generated|pll1|clk[0]}] create_generated_clock -name pma_tx_clk -source [get_pins -compatibility_mode {*siv_alt_pma|pma_direct|auto_generated|transmit_pcs0|clkout}] ************************************************************** ## Set Clock Latency...

  • Page 42: Simulation Files And Example Testbench

    # Set Input Transition #************************************************************** This .sdc file is only applicable to the 10GBASE-R PHY IP core when compiled in isolation. You can use it as a reference to help in creating your own .sdc file. Simulation Files and Example Testbench Refer to “Running a Simulation Testbench”...

  • Page 43: Chapter 4. Xaui Phy Ip Core

    XAUI extends the physical separation possible between the 10 Gbps Ethernet MAC function implemented in an Altera FPGA and the Ethernet standard PHY component on a PCB to one meter. The XAUI IP core accepts 72-bit data (single data rate–SDR XGMII) from the application layer at either 156.25 Mbps or 312.5 Mbps.

  • Page 44: Release Information

    Final support—Verified with final timing models for this device. ■ Preliminary support—Verified with preliminary timing models for this device. Table 4–2 shows the level of support offered by the XAUI IP core for Altera device families. Table 4–2. Device Family Support Device Family...

  • Page 45: Performance And Resource Utilization

    Parameter Settings To configure the XAUI IP core in the parameter editor, click Installed Plug-Ins > Interfaces >Ethernet> XAUI PHY v11.1. This section describes the XAUI PHY IP core parameters, which you can set using the parameter editor. Table 4–4 lists the settings available on General Options tab.

  • Page 46: Analog Options

    4–4 Chapter 4: XAUI PHY IP Core Parameter Settings Table 4–4. General Options (Part 2 of 2) Name Value Description The base data rate is the frequency of the clock input to the PLL. Select a base data rate that minimizes the number of PLLs required 1 ×...

  • Page 47: Stratix V Devices

    Proxy—These parameters have default values that are place holders. The Quartus II software selects these initial default values based on your design; however, Altera recommends that you replace these defaults with values that match your electrical board specification. Table 4–6 lists the analog parameters for Stratix V devices whose original values are place holders for the values that match your electrical board specification.
  • Page 48 4–6 Chapter 4: XAUI PHY IP Core Parameter Settings Table 4–6. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 2) Pin Planner and Assign QSF Assignment Name Assignment Editor Description Options Name Bypass continuous time equalizer ALL_STAGES_ stages 2, 3, and 4 to save power.
  • Page 49 Chapter 4: XAUI PHY IP Core 4–7 Parameter Settings Table 4–7 lists the analog parameters with global or computed default values. You may want to optimize some of these settings. In Table 4–7, the default value is shown in bold type. For computed analog parameters, the default value listed is for the initial setting, not the recomputed setting.
  • Page 50 4–8 Chapter 4: XAUI PHY IP Core Parameter Settings Table 4–7. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3) Pin Planner and QSF Assignment Name Assignment Editor Description Options Assign To Name Sets the gain peaking frequency for the...

  • Page 51: Advanced Options

    IP cores instantiated in each instance of the XAUI PHY IP core. If you turn this option off, the PMA signals remain internal to the core. The default setting is off. This option is available for Arria II GX, HardCopy IV and Stratix IV devices.

  • Page 52: Configurations

    XAUI IP core. As this figure illustrates, if your variant includes a single instantiation of the XAUI IP core, the transceiver reconfiguration control logic is included in the XAUI PHY IP core. For Stratix V devices the Transceiver Reconfiguration Controller must always be external. Refer to...

  • Page 53: Ports

    4–11 Interfaces Ports Figure 4–3 illustrates the top-level signals of the XAUI PHY IP core for the hard IP implementation. Figure 4–4 illustrates the top-level signals of the XAUI PHY IP core for the soft IP implementation. With the exception of the optional signals available for debugging and the signals for dynamic reconfiguration of the transceivers, the pinout of the two implementations is nearly identical.

  • Page 54: Sdr Xgmii Tx Interface

    Chapter 4: XAUI PHY IP Core Interfaces Figure 4–4 illustrates the top-level signals of the XAUI PHY IP core for the soft IP implementation for both the single and DDR rates. Figure 4–4. XAUI Top-Level Signals—Soft PCS and PMA XAUI Top-Level Signals...
  • Page 55 Chapter 4: XAUI PHY IP Core 4–13 Interfaces For the DDR XAUI variant, the start of control character (0xFB) is aligned to either byte 0 or byte 5. Figure 4–6 illustrates byte 0 alignment. Figure 4–6. Byte 0 Start of Frame Transmission Example...

  • Page 56: Sdr Xgmii Rx Interface

    4–14 Chapter 4: XAUI PHY IP Core Interfaces Table 4–9 describes the signals in the SDR TX XGMII interface. Table 4–9. SDR TX XGMII Interface Signal Name Direction Description Contains 4 lanes of data and control for XGMII. Each lane consists of 16 bits of data and 2 bits of control.

  • Page 57: Clocks, Reset, And Powerdown

    Chapter 4: XAUI PHY IP Core 4–15 Interfaces Clocks, Reset, and Powerdown Figure 4–8 illustrates the clock inputs and outputs for the XAUI IP cores with hard PCS and PMA blocks. Figure 4–8. Clock Inputs and Outputs, Hard PCS phy_mgmt_clk...

  • Page 58: Pma Channel Controller

    4–16 Chapter 4: XAUI PHY IP Core Interfaces PMA Channel Controller Table 4–13 describes the signals in this interface. Table 4–13. PMA Channel Controller Signals Signal Name Direction Description Powers down the calibration block. A high-to-low transition on this Input signal restarts calibration.

  • Page 59: Pma Control And Status Interface Signals-Hard Ip Implementation (Optional)

    XAUI PHY. In such cases, you can include the required signal in the top-level module of your XAUI PHY IP core. Table 4–15. Optional Control and Status Signals—Hard IP Implementation, Stratix IV GX Devices (Part 1 of 2)
  • Page 60 4–18 Chapter 4: XAUI PHY IP Core Interfaces Table 4–15. Optional Control and Status Signals—Hard IP Implementation, Stratix IV GX Devices (Part 2 of 2) Signal Name Direction Description Transceiver 8B/10B code group violation or disparity error indicator. If either signal is asserted, a code group violation or disparity error was detected on the associated received code group.

  • Page 61: Registers

    32-bit embedded processor. A single address space provides access to all registers. Writing to reserved or undefined register addresses may have undefined side effects. Table 4–17. XAUI PHY IP Core Registers (Part 1 of 5) Word Bits...
  • Page 62 4–20 Chapter 4: XAUI PHY IP Core Interfaces Table 4–17. XAUI PHY IP Core Registers (Part 2 of 5) Word Bits Register Name Description Addr Reset Control Registers–Automatic Reset Controller Bit mask for reset registers at addresses 0x042 and 0x044.
  • Page 63 Chapter 4: XAUI PHY IP Core 4–21 Interfaces Table 4–17. XAUI PHY IP Core Registers (Part 3 of 5) Word Bits Register Name Description Addr XAUI PCS [31:4] — Reserved — Inverts the polarity of corresponding bit on the RX interface.
  • Page 64 4–22 Chapter 4: XAUI PHY IP Core Interfaces Table 4–17. XAUI PHY IP Core Registers (Part 4 of 5) Word Bits Register Name Description Addr [31:8] — Reserved — Indicates a RX phase compensation FIFO overflow or underrun condition on the corresponding lane. Reading the...

  • Page 65: Dynamic Reconfiguration

    Chapter 4: XAUI PHY IP Core 4–23 Interfaces Table 4–17. XAUI PHY IP Core Registers (Part 5 of 5) Word Bits Register Name Description Addr [31:3] — Reserved — Indicates a TX phase compensation FIFO overflow or underrun condition on the corresponding lane. Reading the...

  • Page 66: Dynamic Reconfiguration For Stratix V Devices

    4–24 Chapter 4: XAUI PHY IP Core Simulation Files and Example Testbench Dynamic Reconfiguration for Stratix V Devices For Stratix V devices, each channel and each TX PLL have separate dynamic reconfiguration interfaces. The parameter editor provides informational messages on the connectivity of these interfaces.

  • Page 67: Chapter 5. Interlaken Phy Ip Core

    5. Interlaken PHY IP Core Interlaken is a high speed serial communication protocol for chip-to-chip packet transfers. The Altera Interlaken PHY IP core implements Interlaken Protocol Specification, Rev 1.2. It supports multiple instances, each with 1 to 24 lanes running at up to 10.3125 Gbps on Stratix V devices.

  • Page 68: Device Family Support

    Final support—Verified with final timing models for this device. ■ Preliminary support—Verified with preliminary timing models for this device. Table 5–1 shows the level of support offered by the Interlaken PHY IP core for Altera device families Table 5–1. Device Family Support Device Family Support Stratix V devices–Hard PCS + PMA...

  • Page 69: Advanced Options

    Chapter 5: Interlaken PHY IP Core 5–3 Parameter Settings Table 5–2. General Option (Part 2 of 2) Parameter Value Description Lane rate/<n> Lane rate/80 Lane rate/64 Lane rate/50 Lane rate/40 Specifies the frequency of the input reference clock. The default Lane rate/32 value for the Input clock frequency is the Lane rate /20;...

  • Page 70: Analog Settings

    Proxy—These parameters have default values that are place holders. The ■ Quartus II software selects these initial default values based on your design; however, Altera recommends that you replace these defaults with values that match your electrical board specification. Table 5–4 lists the analog parameters for Stratix V devices whose original values are place holders for the values that match your electrical board specification.
  • Page 71 Chapter 5: Interlaken PHY IP Core 5–5 Parameter Settings Table 5–4. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 2) Pin Planner and Assign QSF Assignment Name Assignment Editor Description Options Name Configure the VCCA_GXB voltage for a GXB I/O pin by specifying the intended VCCA_GXB voltage for a GXB I/O pin.
  • Page 72 5–6 Chapter 5: Interlaken PHY IP Core Parameter Settings Table 5–5. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3) Pin Planner and QSF Assignment Name Assignment Editor Description Options Assign To Name Static control for the continuous time equalizer in the receiver buffer.
  • Page 73 Chapter 5: Interlaken PHY IP Core 5–7 Parameter Settings Table 5–5. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3) Pin Planner and QSF Assignment Name Assignment Editor Description Options Assign To Name VOLT_0P80V VOLT_0P75V VOLT_0P70V VOLT_0P65V...

  • Page 74: Interfaces

    ■ Ports ■ Registers ■ Transceiver Reconfiguration Ports Figure 5–2 illustrates the top-level signals of the Interlaken PHY IP core. Figure 5–2. Top-Level Interlaken PHY Signals Interlaken Top-Level Signals tx_serial_data<n> tx_parallel_data<n>[65:0] High Speed rx_serial_data<n> tx_ready Serial I/O Avalon-ST tx_datain_bp<n>...

  • Page 75: Avalon-St Tx Interface

    Chapter 5: Interlaken PHY IP Core 5–9 Interfaces For more information about _hw.tcl, files refer to the Component Interface Tcl Reference chapter in volume 1 of the Quartus II Handbook. The following sections describe the signals in each interface. Avalon-ST TX Interface Table 5–6...

  • Page 76: Avalon-St Rx Interface

    5–10 Chapter 5: Interlaken PHY IP Core Interfaces Table 5–6. Avalon-ST TX Signals Signal Name Direction Description Output clock from the TX PCS. The frequency of this clock equals the Output tx_clkout Lane rate divided by 40, which is the PMA serialization factor.
  • Page 77 Chapter 5: Interlaken PHY IP Core 5–11 Interfaces Table 5–7. Avalon-ST RX Signals (Part 2 of 3) Signal Name Direction Description This is an active-high synchronous status signal indicating that block lock (frame synchronization) and frame lock (metaframe boundary delineation) have been achieved. The Interlaken MAC should use this signal to indicate that Metaframe synchronization has been achieved for this lane.

  • Page 78: Pll Interface

    Signal Name Direction Description When enabled tx_coreclkin is available as input port which drives the write side of TX FIFO. Altera recommends using this clock to Input reduce clock skew. When disabled, tx_cllkout drives the write side tx_coreclkin the TX FIFO. tx_clkout must be used when the number of lanes is greater than 1.

  • Page 79: Registers

    Chapter 5: Interlaken PHY IP Core 5–13 Interfaces Registers The Avalon-MM PHY management interface provides access to the Interlaken PCS and PMA registers, resets, error handling, and serial loopback controls. You can use an embedded controller acting as an Avalon-MM master to send read and write commands to this Avalon-MM slave interface.
  • Page 80 5–14 Chapter 5: Interlaken PHY IP Core Interfaces Table 5–12. Interlaken PHY Registers (Part 2 of 3) Word Bits Register Name Description Addr Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module. The reset affects channels enabled in the reset_control (write) reset_ch_bitmask.

  • Page 81: Transceiver Reconfiguration

    Chapter 5: Interlaken PHY IP Core 5–15 Interfaces Table 5–12. Interlaken PHY Registers (Part 3 of 3) Word Bits Register Name Description Addr Stratix V Device Registers Asserted by the CRC32 checker to indicate a CRC error in [27] the corresponding RX lane.

  • Page 82: Timequest Timing Constraints

    5–16 Chapter 5: Interlaken PHY IP Core TimeQuest Timing Constraints Table 5–13 describes the signals in the reconfiguration interface. This interface uses the Avalon-MM PHY Management interface clock. Table 5–13. Reconfiguration Interface Signal Name Direction Description Reconfiguration signals from the Transceiver Reconfiguration Controller.

  • Page 83: Chapter 6. Phy Ip Core For Pci Express (Pipe)

    6. PHY IP Core for PCI Express (PIPE) The Altera PHY IP core for PCI Express (PIPE) implements physical coding sublayer (PCS) and physical media attachment (PMA) modules as defined by the Intel PHY Interface for PCI Express (PIPE) Architecture specification.

  • Page 84: Resource Utilization

    Gen2 ×8 Parameter Settings To configure the PHY IP core for PCI Express in the parameter editor, click Installed Plug-Ins > Interfaces > PCI Express > PHY IP Core for PCI Express (PIPE) v11.1. This PHY IP core is only available when you select the Stratix V device family.

  • Page 85: Analog Options

    Proxy—These parameters have default values that are place holders. The Quartus II software selects these initial default values based on your design; however, Altera recommends that you replace these defaults with values that match your electrical board specification. March 2012 Altera Corporation...
  • Page 86 6–4 Chapter 6: PHY IP Core for PCI Express (PIPE) Parameter Settings Table 6–4 lists the analog parameters for Stratix V devices whose original values are place holders for the values that match your electrical board specification. In Table 6–4, the default value of an analog parameter is shown in bold type.
  • Page 87 Chapter 6: PHY IP Core for PCI Express (PIPE) 6–5 Parameter Settings Table 6–4. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 2) Pin Planner and Assign QSF Assignment Name Assignment Editor Description Options Name Configure the VCCA_GXB voltage for a GXB I/O pin by specifying the intended VCCA_GXB voltage for a GXB I/O pin.
  • Page 88 6–6 Chapter 6: PHY IP Core for PCI Express (PIPE) Parameter Settings Table 6–5. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3) Pin Planner and QSF Assignment Name Assignment Editor Description Options Assign To Name Static control for the continuous time equalizer in the receiver buffer.
  • Page 89 Chapter 6: PHY IP Core for PCI Express (PIPE) 6–7 Parameter Settings Table 6–5. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3) Pin Planner and QSF Assignment Name Assignment Editor Description Options Assign To Name VOLT_0P80V...

  • Page 90: Interfaces

    Quartus II Help. For more information about Quartus II Settings, refer to Quartus II Settings File Manual. Interfaces This section describes interfaces of the PHY IP Core for PCI Express (PIPE). It includes the following topics: Ports ■ Registers ■...

  • Page 91: Avalon-St Tx Input Data From The Phymac

    Chapter 6: PHY IP Core for PCI Express (PIPE) 6–9 Interfaces The block diagram shown in the GUI labels the external pins with the interface type and places the interface name inside the box. The interface type and name are used in the _hw.tcl file.

  • Page 92: Pipe Interface

    6–10 Chapter 6: PHY IP Core for PCI Express (PIPE) Interfaces PIPE Interface Table 6–8 describes the signals in the PIPE interface. Table 6–8. PIPE Interface (Part 1 of 2) Signal Name Direction Description This is the 100 MHz input reference clock source for the PHY PLL. You can...
  • Page 93 Chapter 6: PHY IP Core for PCI Express (PIPE) 6–11 Interfaces Table 6–8. PIPE Interface (Part 2 of 2) Signal Name Direction Description This signal requests the PHY to change its power state to the specified state. The following encodings are defined: 2b’00–...

  • Page 94: Transceiver Serial Interface

    6–12 Chapter 6: PHY IP Core for PCI Express (PIPE) Interfaces Figure 6–3 illustrates the pipe_pclk switching from Gen1 to Gen2 and back to Gen1. Figure 6–3. Rate Switch from Gen1 to Gen2 250 MHz (Gen1) 500 MHz (Gen2) 250 MHz (Gen1)

  • Page 95: Registers

    (1) <n> is the number of lanes. <d> is the deserialization factor. <p> is the number of PLLs. Registers The Avalon-MM PHY management interface provides access to the PHY IP Core for PCI Express PCS and PMA features that are not part of the standard PIPE interface.

  • Page 96: Register Descriptions

    100–125 MHz to meet the specification for the transceiver reconfiguration clock. Global reset signal that resets the entire PHY IP core. Changed definition Input phy_mgmt_clk_reset of phy_mgmt_clk_reset. This signal is active high and level sensitive.
  • Page 97 Chapter 6: PHY IP Core for PCI Express (PIPE) 6–15 Interfaces Table 6–12. PCI Express PHY (PIPE) IP Core Registers (Part 2 of 4) Word Bits Register Name Description Addr Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module.
  • Page 98 6–16 Chapter 6: PHY IP Core for PCI Express (PIPE) Interfaces Table 6–12. PCI Express PHY (PIPE) IP Core Registers (Part 3 of 4) Word Bits Register Name Description Addr When asserted, indicates that the RX CDR PLL is locked...

  • Page 99: Dynamic Reconfiguration

    Chapter 6: PHY IP Core for PCI Express (PIPE) 6–17 Interfaces Table 6–12. PCI Express PHY (PIPE) IP Core Registers (Part 4 of 4) Word Bits Register Name Description Addr [31:4] Reserved — When set, the word alignment logic operates in bitslip mode.

  • Page 100: Simulation Files And Example Testbench

    6–18 Chapter 6: PHY IP Core for PCI Express (PIPE) Simulation Files and Example Testbench For Stratix V devices, each channel and each TX PLL have separate dynamic reconfiguration interfaces. The parameter editor provides informational messages on the connectivity of these interfaces.

  • Page 101: Chapter 7. Custom Phy Ip Core

    7. Custom PHY IP Core The Altera Custom PHY IP core is a generic PHY that you can customize for use in Arria V or Stratix V FPGAs. You can connect your application’s MAC-layer logic to the Custom PHY to transmit and receive data at rates of 0.611–6.5536 Gbps for Arria V devices or 0.622–8.5 Gbps for Stratix V devices.

  • Page 102: Device Family Support

    Final support—Verified with final timing models for this device. Preliminary support—Verified with preliminary timing models for this device. ■ Table 7–1 shows the level of support offered by the Custom PHY IP core for Altera device families. Table 7–1. Device Family Support Device Family Support Stratix V devices–Hard PCS and PMA...

  • Page 103: Parameter Settings

    Parameter Settings Parameter Settings To configure the Custom PHY IP core in the parameter editor, click Installed Plug-Ins > Interfaces > Transceiver PHY > Custom PHY v11.1. You can use the tabs on the parameter editor to select the options required for the protocol. Presets are available for the 1.25 Gbps Ethernet (1.25GbE) protocol.
  • Page 104 7–4 Chapter 7: Custom PHY IP Core Parameter Settings Table 7–3. General Options (Part 2 of 3) Name Value Description The PCS-PMA interface width depends on the FPGA fabric transceiver interface width and whether 8B/10B is enabled. The following combinations are available:...
  • Page 105 On/Off This option is typically required if you are planning to import your Custom PHY IP core into a Qsys system. When On, the automatic reset controller resets your design at power up. When Off you can design you own reset logic using...

  • Page 106: Word Alignment

    7–6 Chapter 7: Custom PHY IP Core Parameter Settings Word Alignment The word aligner restores word boundaries of received data based on a predefined alignment pattern. This pattern can be 7, 8, 10, 16, 20, or 32 bits long. The word alignment module searches for a programmed pattern to identify the correct boundary for the incoming stream.

  • Page 107: Rate Match Fifo

    Chapter 7: Custom PHY IP Core 7–7 Parameter Settings Table 7–6 provides more information about the word alignment function. Table 7–6. Word Aligner Options Word PMA-PCS Word Alignment Configuration Interface Alignment Word Alignment Behavior Pattern Width (bits) Mode Length (bits) Manual User-controlled signal starts alignment process.

  • Page 108: 8B/10B Encoder And Decoder

    7–8 Chapter 7: Custom PHY IP Core Parameter Settings Table 7–7. Rate Match FIFO Options (Part 2 of 2) Name Value Description Rate match 0010111100 Enter a 10-bit skip pattern (bits 10–19) and a 10-bit control pattern insertion/deletion -ve (bits 0–9). The skip pattern must have neutral disparity.

  • Page 109: Pll Reconfiguration

    Chapter 7: Custom PHY IP Core 7–9 Parameter Settings Table 7–9. Byte Order Options Name Value Description Specifies the pattern that identifies the SOP. For 16-bit byte ordering pattern you must include a 2-bit pad so that Byte ordering pattern 11111011 the pattern entered is in the following format: 00 <pattern>...

  • Page 110: Analog Options

    Proxy—These parameters have default values that are place holders. The Quartus II software selects these initial default values based on your design; however, Altera recommends that you replace these defaults with values that match your electrical board specification. Table 7–11 lists the analog parameters for Stratix V devices whose original values are place holders for the values that match your electrical board specification.
  • Page 111 Chapter 7: Custom PHY IP Core 7–11 Parameter Settings Table 7–11. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 2) Pin Planner and Assign QSF Assignment Name Assignment Editor Description Options Name Bypass continuous time equalizer ALL_STAGES_ stages 2, 3, and 4 to save power.
  • Page 112 7–12 Chapter 7: Custom PHY IP Core Parameter Settings Table 7–12 lists the analog parameters with global or computed default values. You may want to optimize some of these settings. In Table 7–12, the default value is shown in bold type. For computed analog parameters, the default value listed is for the initial setting, not the recomputed setting.
  • Page 113 Chapter 7: Custom PHY IP Core 7–13 Parameter Settings Table 7–12. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3) Pin Planner and QSF Assignment Name Assignment Editor Description Options Assign To Name Sets the gain peaking frequency for the...

  • Page 114: Presets For Ethernet

    7–14 Chapter 7: Custom PHY IP Core Parameter Settings Table 7–12. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3) Pin Planner and QSF Assignment Name Assignment Editor Description Options Assign To Name Differential output voltage setting. The...

  • Page 115: Interfaces

    ■ ■ Register Interface ■ Dynamic Reconfiguration Ports Figure 7–2 illustrates the top-level signals of the Custom PHY IP core. The variables in Figure 7–2 represent the following parameters: March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...
  • Page 116 7–16 Chapter 7: Custom PHY IP Core Interfaces ■ <n>—The number of lanes ■ <w>—The width of the FPGA fabric to transceiver interface per lane <s>— The symbol size ■ ■ <p>—The number of PLLs Figure 7–2. Custom PHY Top-Level Signals Custom PHY Top-Level Signals tx_parallel_data[<n><w>-1>:0]...

  • Page 117: Avalon-St Tx Input Data From The Mac

    Table 7–15. Avalon-ST RX Interface Signal Name Direction Description This is RX parallel data driven from the Custom PHY IP core. The ready latency on this interface is 0, so that the MAC must be able Source rx_parallel_data[<n><w>-1:0] to accept data as soon as the PHY comes out of reset. Data driven from this interface is always valid.

  • Page 118: Clock Interface

    7–18 Chapter 7: Custom PHY IP Core Interfaces Clock Interface Table 7–16 describes optional and required clocks for the Custom PHY. The input reference clock, pll_ref_clk, drives a PLL inside the PHY-layer block, and a PLL output clock, rx_clkout (described in Table 7–15 on page...

  • Page 119: Reset Control And Status (Optional)

    Chapter 7: Custom PHY IP Core 7–19 Interfaces Table 7–18. Serial Interface and Status Signals (Part 2 of 2) Signal Name Direction Signal Name Indicates presence or absence of synchronization on the RX interface. Asserted when word aligner identifies the word Output rx_syncstatus[<n>(<w>/<s>)-1:0]...

  • Page 120: Register Interface

    7–20 Chapter 7: Custom PHY IP Core Interfaces Table 7–19. Avalon-ST RX Interface (Part 2 of 2) Signal Name Direction Description Input When asserted, resets the RX PCS. rx_digitalreset[<n>-1:0] Input When asserted, resets the RX CDR. rx_analogreset[<n>-1:0] When asserted, indicates that the RX channel is being calibrated. You Output rx_cal_busy[<n>-1:0]...

  • Page 121: Register Descriptions

    32-bit embedded processor. A single address space provides access to all registers. Writing to reserved or undefined register addresses may have undefined side effects. Table 7–21. Custom PHY IP Core Registers (Part 1 of 3) Word Bits...
  • Page 122 7–22 Chapter 7: Custom PHY IP Core Interfaces Table 7–21. Custom PHY IP Core Registers (Part 2 of 3) Word Bits Register Name Description Addr Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module. The reset affects channels enabled in the reset_control (write) reset_ch_bitmask.
  • Page 123 Chapter 7: Custom PHY IP Core 7–23 Interfaces Table 7–21. Custom PHY IP Core Registers (Part 3 of 3) Word Bits Register Name Description Addr When 1, indicates that the RX CDR PLL is locked to the RX 0x066 [31:0]...

  • Page 124: Dynamic Reconfiguration

    7–24 Chapter 7: Custom PHY IP Core Simulation Files and Example Testbench Dynamic Reconfiguration As silicon progresses towards smaller process nodes, circuit performance is affected more by variations due to process, voltage, and temperature (PVT). These process variations result in analog voltages that can be offset from required ranges. The calibration performed by the dynamic reconfiguration interface compensates for variations due to PVT.

  • Page 125: Chapter 8. Low Latency Phy Ip Core

    Avalon-MM Controller Control & Status Because the Low latency PHY IP core bypasses much of the PCS, it minimizes the PCS latency. For more detailed information about the Low Latency datapath and clocking, refer to the refer to the “Stratix V GX Device Configurations” section in the...

  • Page 126: Performance And Resource Utilization

    8–2 Chapter 8: Low Latency PHY IP Core Performance and Resource Utilization Table 8–1 shows the level of support offered by the PMA IP core for Altera device families. Table 8–1. Device Family Support Device Family Support Stratix V devices...

  • Page 127: Parameter Settings

    Parameter Settings Parameter Settings To configure the Low Latency PHY IP core in the MegaWizard Plug-In Manager, click Installed Plug-Ins > Interfaces > Transceiver PHY > Low Latency PHY v11.1. For more information about using the MegaWizard Plug-In Manager refer to...
  • Page 128 8–4 Chapter 8: Low Latency PHY IP Core Parameter Settings Table 8–3. General Options Name Value Description This option indicates the parallel data fabric transceiver interface FPGA fabric transceiver 8, 10, 16, 20, 32, width. GT datapath supports a single width of 128 bits. Refer...

  • Page 129: Additional Options

    For the GT datapath, if you are using different reference clock pins for the TX and RX channels, you must instantiate two separate Low Latency PHY IP core instances for TX and RX channels. The reference clock pins for each channel must reside in the same transceiver bank.

  • Page 130: Pll Reconfiguration Options

    Avalon data interfaces On/Off This option is typically required if you are planning to import your Low Latency Transceiver PHY IP core into a Qsys system. All bits Specifies the number of bits that are in the smallest unit of data.
  • Page 131 Chapter 8: Low Latency PHY IP Core 8–7 Parameter Settings The PLL reconfiguration options are not available for the GT datapath. Table 8–6. PLL Reconfigurations Name Value Description You must enable this option if you plan to reconfigure the PLLs in...

  • Page 132: Analog Options

    Proxy—These parameters have default values that are place holders. The ■ Quartus II software selects these initial default values based on your design; however, Altera recommends that you replace these defaults with values that match your electrical board specification. Table 8–7 lists the analog parameters for Stratix V devices whose original values are place holders for the values that match your electrical board specification.
  • Page 133 Chapter 8: Low Latency PHY IP Core 8–9 Parameter Settings Table 8–7. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 2) Pin Planner and Assign QSF Assignment Name Assignment Editor Description Options Name Configure the VCCA_GXB voltage for a GXB I/O pin by specifying the intended VCCA_GXB voltage for a GXB I/O pin.
  • Page 134 8–10 Chapter 8: Low Latency PHY IP Core Parameter Settings Table 8–8. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3) Pin Planner and QSF Assignment Name Assignment Editor Description Options Assign To Name Static control for the continuous time equalizer in the receiver buffer.
  • Page 135 Chapter 8: Low Latency PHY IP Core 8–11 Parameter Settings Table 8–8. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3) Pin Planner and QSF Assignment Name Assignment Editor Description Options Assign To Name VOLT_0P80V VOLT_0P75V VOLT_0P70V...

  • Page 136: Interfaces

    ■ Register Interface ■ Dynamic Reconfiguration Ports Figure 8–2 illustrates the top-level signals of the Custom PHY IP core. The variables in Figure 8–2 represent the following parameters: ■ <n>—The number of lanes ■ <w>—The width of the FPGA fabric to transceiver interface per lane Figure 8–2.

  • Page 137: Avalon-St Tx And Rx Data Interface To The Fpga Fabric

    MAC. This signal is Output tx_ready[<n>-1:0] available if you select Enable embedded reset control on the Additional Options tab. This is RX parallel data driven by the Low Latency PHY IP core. Source rx_parallel_data[<n><w>-1:0] Data driven from this interface is always valid. Output Low speed clock recovered from the serial data.

  • Page 138: Optional Status Interface

    8–14 Chapter 8: Low Latency PHY IP Core Interfaces Optional Status Interface Table 8–11 describes the signals that comprise the optional status interface. Table 8–11. Optional Status Interface Signal Name Direction Description When asserted, indicates that the RX CDR is locked to incoming data.

  • Page 139: Register Interface

    Chapter 8: Low Latency PHY IP Core 8–15 Interfaces Table 8–13. Avalon-ST RX Interface (Part 2 of 2) Signal Name Direction Description Input When asserted, resets the RX CDR. rx_analogreset[<n>-1:0] When asserted, indicates that the RX channel is being calibrated. You Output rx_cal_busy[<n>-1:0]...

  • Page 140: Register Descriptions

    PHY Management Interface using word addresses and a 32-bit embedded processor. Writing to reserved or undefined register addresses may have undefined side effects. Table 8–15. Low Latency PHY IP Core Registers (Part 1 of 2) Word Bits...

  • Page 141: Dynamic Reconfiguration

    Chapter 8: Low Latency PHY IP Core 8–17 Simulation Files and Example Testbench Table 8–15. Low Latency PHY IP Core Registers (Part 2 of 2) Word Bits Register Name Description Addr When asserted, indicates that the RX CDR PLL is...
  • Page 142 8–18 Chapter 8: Low Latency PHY IP Core Simulation Files and Example Testbench Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...

  • Page 143: Chapter 9. Deterministic Latency Phy Ip Core

    9. Deterministic Latency PHY IP Core The Altera Deterministic Latency PHY IP Core targets protocols that require a datapath with deterministic latency. Deterministic latency enables accurate delay measurements and known timing for the transmit (TX) and receive (RX) datapaths as required in applications such as wireless communication systems, emerging Ethernet standards, and test and measurement equipment.

  • Page 144: Auto-Negotiation

    This is a standard, memory-mapped protocol that is normally used to read and write registers and memory. The transceiver reconfiguration interface connects to the Altera Transceiver Reconfiguration Controller IP core which can dynamically reconfigure transceiver settings. Finally, the PMA transmits and receives serial data which connects to an optical link.

  • Page 145: Achieving Deterministic Latency

    9–2: (1) The TX and RX Phase Compensation FIFOs always operate in register mode. In the current release, Altera recommends that you use a delay estimate FIFO to measure the phase difference between the tx_clkout and rx_clkout, and the clock output of the PLL to ensure the delay through the FIFO to a certain accuracy.

  • Page 146: Delay Numbers

    9–4 Chapter 9: Deterministic Latency PHY IP Core For RE RX_latency_RE = <RX PCS latency in parallel clock cycles> + (<RX PMA latency in UI> + <PMA uncertainty reported by wordalignment_boundary[5]>) TX_latency_RE = <TX PCS latency in parallel clock cycles>...

  • Page 147: Device Family Support

    Final support—Verified with final timing models for this device. ■ Preliminary support—Verified with preliminary timing models for this device. Table 9–5 shows the level of support offered by the Deterministic Latency PHY IP core for Altera device families. Table 9–5. Device Family Support Device Family...

  • Page 148: Parameter Settings

    Parameter Settings Parameter Settings To configure the Deterministic Latency PHY IP core in the parameter editor, click Installed Plug-Ins > Interfaces > Transceiver PHY > Deterministic Latency PHY v11.1. You can use the tabs on the parameter editor to select the options required for the protocol.
  • Page 149 Chapter 9: Deterministic Latency PHY IP Core 9–7 Parameter Settings Table 9–6. General Options (Part 2 of 2) Name Value Description For systems that transmit and receive data at more than one data rate, select a base data rate that minimizes the number of PLLs required to generate the clocks for data transmission.

  • Page 150: Additional Options

    9–8 Chapter 9: Deterministic Latency PHY IP Core Parameter Settings Additional Options Table 9–8 lists the settings available on the Additional Options tab. Table 9–8. Additional Options (Part 1 of 2) Name Value Description The word aligner restores word boundaries of received data based on a predefined alignment pattern.

  • Page 151: Analog Options

    Proxy—These parameters have default values that are place holders. The ■ Quartus II software selects these initial default values based on your design; however, Altera recommends that you replace these defaults with values that match your electrical board specification. March 2012 Altera Corporation...
  • Page 152 9–10 Chapter 9: Deterministic Latency PHY IP Core Parameter Settings Table 9–9 lists the analog parameters for Stratix V devices whose original values are place holders for the values that match your electrical board specification. In Table 9–9, the default value of an analog parameter is shown in bold type.
  • Page 153 Chapter 9: Deterministic Latency PHY IP Core 9–11 Parameter Settings Table 9–9. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 2) Pin Planner and Assign QSF Assignment Name Assignment Editor Description Options Name Configure the VCCA_GXB voltage for a GXB I/O pin by specifying the intended VCCA_GXB voltage for a GXB I/O pin.
  • Page 154 9–12 Chapter 9: Deterministic Latency PHY IP Core Parameter Settings Table 9–10. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3) Pin Planner and QSF Assignment Name Assignment Editor Description Options Assign To Name Static control for the continuous time equalizer in the receiver buffer.
  • Page 155 Chapter 9: Deterministic Latency PHY IP Core 9–13 Parameter Settings Table 9–10. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3) Pin Planner and QSF Assignment Name Assignment Editor Description Options Assign To Name VOLT_0P80V VOLT_0P75V VOLT_0P70V...

  • Page 156: Interfaces

    ■ Register Interface ■ Dynamic Reconfiguration ■ Ports Figure 9–3 illustrates the top-level signals of the Deterministic Latency PHY IP core. The variables in Figure 9–3 represent the following parameters: <n>—The number of lanes ■ ■ <w>—The width of the FPGA fabric to transceiver interface per lane ■...
  • Page 157 Chapter 9: Deterministic Latency PHY IP Core 9–15 Interfaces ■ <p>—The number of PLLs Figure 9–3. Deterministic Latency PHY Top-Level Signals Deterministic PHY Top-Level Signals tx_parallel_data[<n><w>-1>:0] tx_serial_data[<n>-1:0] High Speed Avalon-ST Tx tx_clkout[<n>-1:0] rx_serial_data[<n>-1:0] Serial I/O from MAC tx_datak[(<n>(<w>/<s>)-1:0] tx_ready rx_parallel_data[(<n><w>)-1:0]...

  • Page 158: Avalon-St Tx Input Data From The Mac

    9–16 Chapter 9: Deterministic Latency PHY IP Core Interfaces Avalon-ST TX Input Data from the MAC Table 9–11 describes the signals in the Avalon-ST input interface. These signals are driven from the MAC to the PCS. This is an Avalon sink interface.

  • Page 159: Transceiver Serial Data Interface

    Chapter 9: Deterministic Latency PHY IP Core 9–17 Interfaces Transceiver Serial Data Interface Table 9–14 describes the differential serial data interface and the status signals for the transceiver serial data interface. Table 9–14. Serial Interface and Status Signals Signal Name...

  • Page 160: Optional Reset Control And Status

    9–18 Chapter 9: Deterministic Latency PHY IP Core Interfaces Table 9–15. Serial Interface and Status Signals (Part 2 of 2) Signal Name Direction Signal Name When asserted, the receiver CDR is in to lock-to-data mode. When deasserted, the receiver CDR lock mode Output rx_is_lockedtodata[(<n>(<d>/<s>)-1:0]...
  • Page 161 Chapter 9: Deterministic Latency PHY IP Core 9–19 Interfaces Figure 9–4 illustrates the role of the PHY Management module in the Deterministic Latency PHY. Figure 9–4. Deterministic Latency PHY IP Core Deterministic PHY IP Core Deterministic PHY PCS and PMA...

  • Page 162: Register Descriptions

    32-bit embedded processor. A single address space provides access to all registers. Writing to reserved or undefined register addresses may have undefined side effects. Table 9–18. Deterministic Latency PHY IP Core Registers (Part 1 of 3) Word Bits...
  • Page 163 Chapter 9: Deterministic Latency PHY IP Core 9–21 Interfaces Table 9–18. Deterministic Latency PHY IP Core Registers (Part 2 of 3) Word Bits Register Name Description Addr Reset Controls –Manual Mode You can use the reset_fine_control register to create your own reset sequence. In manual mode, only the TX...

  • Page 164: Dynamic Reconfiguration

    9–22 Chapter 9: Deterministic Latency PHY IP Core Interfaces Table 9–18. Deterministic Latency PHY IP Core Registers (Part 3 of 3) Word Bits Register Name Description Addr [31:1] Reserved. pcs8g_tx_status 0x082 Reserved — [31:6] Reserved. pcs8g_tx_control Sets the number of bits that the TX bit slipper needs to slip.

  • Page 165: Channel Placement And Utilization

    Controller. <n> grows linearly with the number of reconfiguration reconfig_from_xcvr[(<n>46)-1:0] interfaces. Channel Placement and Utilization The Deterministic Latency PHY IP core has the following restriction on channel placement: ■ Channels 0–2 in transceiver banks GXB_L0 and GSB_R0 of Arria V devices are not available for deterministic latency protocols.

  • Page 166: Simulation Files And Example Testbench

    Quartus II software creates automatically when you generate your Deterministic Latency PHY IP core. This chapter provides additional information about the document and Altera. Altera Transceiver PHY IP Core March 2012 Altera Corporation...

  • Page 167: Chapter 10. Transceiver Reconfiguration Controller

    10. Transceiver Reconfiguration Controller The Altera Transceiver Reconfiguration Controller dynamically reconfigures the analog, channel, and TX PLL settings in Stratix V GX devices. Because the Stratix V FPGA is a 28-nm device, circuit performance is affected by variations due to process, voltage, and temperature (PVT).
  • Page 168 ■ “Reconfiguration Controller to PHY IP Connectivity” on page 10–37 ■ “Merging TX PLLs In Multiple Transceiver PHY Instances” on page 10–38 ■ “Loopback Modes” on page 10–39 ■ Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...

  • Page 169: System Overview

    ■ Register Based—In this access mode you can directly reconfigure a transceiver PHY IP core using the Transceiver Reconfiguration Controller’s reconfiguration management interface. You initiate reconfiguration using a series of Avalon-MM reads and writes to the appropriate registers of the Transceiver Reconfiguration Controller.

  • Page 170: Device Family Support

    The streaming mode uses a memory initialization file (.mif) to stream an update to the transceiver PHY IP core. The .mif file can contain changes for many settings. For example, a single .mif file might contain changes to the PCS datapath settings, clock settings, and PLL parameters.

  • Page 171: Performance And Resource Utilization

    Library, type Transc in the Search Box. Qsys filters all available components for this text string and displays the Transceiver Reconfiguration Controller which is in the Interface Protocols >Transceiver PHY category. March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...
  • Page 172 When enabled, this circuitry improves the duty cycle of the Enable duty cycle calibration On/Off transceiver PHY IP core transmitters. When enabled, an algorithm that improves the signal integrity of Enable auxiliary transmit (ATX) On/Off the ATX PLL is included in the Transceiver Reconfiguration PLL calibration Controller IP core.

  • Page 173: Interfaces

    When asserted, signals an Avalon-MM read request. reconfig_mif_read Input The read data. reconfig_mif_readdata[15:0] When asserted, indicates that the MIF Avalon-MM slave is not Input reconfig_mif_waitrequest ready to respond to a read request. March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...

  • Page 174: Transceiver Reconfiguration Interface

    Description Parallel reconfiguration bus from the Transceiver Output reconfig_to_xcvr[(<n>×70)-1:0] Reconfiguration Controller to the PHY IP core. Parallel reconfiguration bus from the PHY IP core to the Input reconfig_from_xcvr[(<n>×46)-1:0] Transceiver Reconfiguration Controller. When asserted, indicates that a reconfiguration operation is in progress and no further reconfiguration operations should be performed.

  • Page 175: Reconfiguration Controller Memory Map

    7’h08–7’h0C “PMA Analog Controls” on page 10–11 7’h10–7’h14 “EyeQ” on page 10–12 7’h18–7’h1C “DFE” on page 10–14 7’h28–7’h2C “AEQ” on page 10–16 7’h30–7’h34 “ATX PLL Calibration” on page 10–17 March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...

  • Page 176: Transceiver Calibration Functions

    Transceiver Calibration Functions The Transceiver Reconfiguration Controller supports various calibration functions to enhance the performance and operation of any connected transceiver PHY IP core. This section describes the functionality of each calibration function. Refer to Table 10–3 on page 10–5 for the resource utilization of these calibration functions.

  • Page 177: Pma Analog Controls

    [5:0] pma offset reconfigured. Table 10–10 describes the valid offset values. Reconfiguration data for the PMA analog settings. Refer to 7’h0C [6:0] data Table 10–10 for valid data values. March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...

  • Page 178: Eyeq

    Transceiver Reconfiguration Controller. EyeQ EyeQ is a debug and diagnostic tool that analyzes the incoming data, including the receiver’s gain, noise level, and jitter after the receive buffer. Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...
  • Page 179 Write. Writing a 1 to this bit triggers a write operation. 7’h13 [5:0] Specifies the 6-bit offset of the EyeQ register. eyeq offset 7’h14 [15:0] Reconfiguration data for the transceiver PHY registers. data March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...

  • Page 180: Dfe

    Addr The logical channel address. Must be specified when performing dynamic updates. The Transceiver 7’h18 [9:0] logical channel address Reconfiguration Controller maps the logical address to the physical address. Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...
  • Page 181 Specifies the polarity of the fourth post tap as follows: 0: negative polarity ■ tap 4 polarity 1: positive polarity ■ [2:0] Specifies the coefficient for the fourth post tap. tap 4 March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...

  • Page 182: Aeq

    The Transceiver Reconfiguration Controller maps the logical address to the physical address. The physical channel address. The Transceiver 7’h29 [9:0] Reconfiguration Controller maps the logical address to the physical channel address physical address. Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...

  • Page 183: Atx Pll Calibration

    Reconfiguration Controller automatically runs ATX calibration at power up. You may need to rerun ATX calibration if you reset an ATX PLL and it does not lock after the specified lock time. March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...

  • Page 184: Pll Reconfiguration

    The PLL registers for dynamic reconfiguration feature are available when you select one of the following Stratix V transceiver PHY IP cores: Custom PHY IP Core ■ ■ Low Latency PHY IP Core Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...
  • Page 185 You can establish the number of possible PLL configurations on the Reconfiguration tab of the appropriate transceiver PHY IP core. The Reconfiguration tab allows you to specify up to five input reference clocks and up to four TX PLLs. You can also change the input clock source to the CDR PLL;...
  • Page 186 Specifies the 4-bit register address used for indirect to the 7’h43 [3:0] PLL registers on the reconfiguration bus. Refer to pll offset Table 10–20 for offsets and values. 7’h44 [15:0] Specifies the read or write data. data Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...

  • Page 187: Channel And Pll Reconfiguration

    Channel and PLL Reconfiguration You can use channel and PLL reconfiguration to dynamically reconfigure the channel and PLL settings in a transceiver PHY IP core. Among the settings that you can change dynamically are the data rate and interface width.

  • Page 188: Pll Reconfiguration

    64 bits may carry valid data. Specifically, in the wider bus, only the lower <n> bits are used, where <n> is equal to the width of the FPGA fabric width specified in the transceiver PHY IP core. Table 10–21 illustrates this point for the 10G datapath, showing three examples where the FPGA fabric interface width is less than 64 bits.
  • Page 189 7’h3C [31:0] data the offset register. When MIF Mode = 2’b01, data holds an update for transceiver to be dynamically reconfigured. March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...

  • Page 190: Mode 0 Streaming A Mif For Reconfiguration

    In mode 0, you can stream the contents of a MIF containing the reconfiguration data to the transceiver PHY IP core instance. You specify this mode by writing a value of 2'b00 into bits 2 and 3 of the control and status register, as indicated in Table 10–22...

  • Page 191: Mode 1 Avalon-Mm Direct Writes For Reconfiguration

    MIFs associated with the compiled project for each transceiver PHY IP core instance in the design. The parameter settings of PHY IP core instance reflect the currently specified MIF. You can store the MIF in an on-chip ROM or any other type of memory.
  • Page 192 Length = 2 Offset Address L <n> +1 Data for Offset L <n> +2 Data for Offset L + 1 Length = 0 Reserved Opcode = End of MIF <n> +3 Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...

  • Page 193: Procedures For Reconfiguration

    1. Read the control and status register busy bit (bit 8) until it is clear. 2. Write the logical channel number of the channel to be read to the logical channel number register. 3. Write the <feature> offset address. March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...

  • Page 194: Changing Transceiver Settings Using Streamer-Based Reconfiguration

    8. Write to the Streamer control and status register to 1'b1, to initiate the streaming operation. 9. Read the control and status register busy bit. When the busy bit is deasserted, the MIF streaming operation has completed. Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...

  • Page 195: Direct Write Reconfiguration

    1. Increment the offset value by 1 for each additional data record. 7. Read the control and status register busy bit. When the busy bit is deasserted, the operation has completed. March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...
  • Page 196 #Setting data register with the second data record write_32 0x3C 16'b0010001110110000 #Writing second data to the Streamer write_32 0x3A 0x1 #Incrementing Streamer offset register offset address write_32 0x3B 0x2 Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...

  • Page 197: Understanding Logical Channel Numbering

    The transceiver PHY IP cores create a separate reconfiguration interface for each channel and each TX PLL. Each transceiver PHY IP core reports the number of reconfiguration interfaces it requires in the message pane of its GUI. You must take note of this number so that you can enter it as a parameter in the Transceiver Reconfiguration Controller.
  • Page 198 Chapter 10: Transceiver Reconfiguration Controller Understanding Logical Channel Numbering Figure 10–8 shows the Low Latency PHY IP core GUI specifying 32 channels. The message pane indicates that reconfiguration interfaces 0–31 are for the transceiver channels and reconfiguration interfaces 32–63 are for the TX PLLs.
  • Page 199 Figure 10–9 illustrates the GUI for the Transceiver Reconfiguration Controller. To connect the Low Latency PHY IP core instance to the the Transceiver Reconfiguration Controller, you would enter 64 for Number of reconfiguration interfaces. You would not need to enter any values for the Optional interface grouping parameter because all of the interfaces belong to the same transceiver PHY IP core instance.

  • Page 200: Two Phy Ip Core Instances Each With Four Bonded Channels

    PHY IP and the Transceiver Reconfiguration Controller. Two PHY IP Core Instances Each with Four Bonded Channels When two transceiver PHY instances, each with four bonded channels, are connected to a Transceiver Reconfiguration Controller, the reconfiguration buses of the two instances are concatenated.

  • Page 201: One Phy Ip Core Instance With Eight Bonded Channels

    12-15 to a single physical PLL. One PHY IP Core Instance with Eight Bonded Channels This example requires the Quartus II Fitter to place channels in two, contiguous transceiver banks. To preserve flexibility for the Fitter, each channel and TX PLL is numbered separately.

  • Page 202: Two Phy Ip Core Instances Each With Non-Bonded Channels

    Channel 7 Two PHY IP Core Instances Each with Non-Bonded Channels Non-bonded channels do not share TX PLLs.. For each transceiver PHY IP core instance, the Quartus II software assigns the data channels sequentially beginning at logical address 0 and assigns the TX PLLs the subsequent logical addresses.

  • Page 203: Reconfiguration Controller To Phy Ip Connectivity

    Embedded Controller 3 Transceiver Processor 10 GBASE-R Channels 10 GBASE-R Custom 3 Transceiver Transceiver Custom Channels Reconfiguration to Embedded CMU PLL Controller Processor Custom Reconfig to and from Transceiver March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...

  • Page 204: Merging Tx Plls In Multiple Transceiver Phy Instances

    Stratix V GX, GS, or GT Device Transceiver Bank 3 Transceiver 10 GBASE-R Channels Transceiver Reconfig to 10 GBASE-R Reconfiguration and from to Embedded Controller Custom Transceiver Processor 3 Transceiver Custom Channels CMU PLL Custom Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...

  • Page 205: Loopback Modes

    Stratix V devices. This mode is enabled by writing the phy_serial_loopback register (0x061) using the Avalon-MM PHY management interface. PCI Express supports reverse parallel loopback mode as required by the PCI Express Base Specification. March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...
  • Page 206 RX channel. Figure 10–15. Serial Loopback Transceiver Tx PMA Tx PCS Serializer tx_dataout FPGA Serial Fabric loopback Rx PMA To FPGA fabric for verification Rx PCS serializer Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...
  • Page 207 11. Migrating from Stratix IV to Stratix V Devices Previously, Altera provided the ALTGX megafunction as a general purpose transceiver PHY solution. The current release of the Quartus II software includes protocol-specific PHY IP cores that simplify the parameterization process.

  • Page 208: Chapter 11. Migrating From Stratix Iv To Stratix V Devices

    The reconfiguration bus includes Avalon-MM signals to read and write registers and memory and test bus signals. When you instantiate a transceiver PHY in a Stratix V device, the transceiver PHY IP core provides informational messages specifying the number of required reconfiguration interfaces in the message pane as Example 11–1...

  • Page 209: Xaui Phy

    3 of the Stratix IV Device Handbook. XAUI PHY This section lists the differences between the parameters and signals for the XAUI PHY IP core and the ALTGX megafunction when configured in the XAUI functional mode. Parameter Differences Table 11–2 lists the XAUI PHY parameters and the corresponding ALTGX megafunction parameters.

  • Page 210: Port Differences

    Stratix V Devices Signal Name Width Signal Name Width Reference Clocks and Resets pll_inclk refclk [<n> -1:0] Not available — rx_cruclk coreclkout xgmii_rx_clk [<n> – 1:0] Not available — rx_coreclk Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...
  • Page 211 Not available — rx_rmfifodatadeleted Transceiver Reconfiguration — cal_blk_clk These signals are included in the reconfig_to_xcvr bus. — reconfig_clk [3:0] variable reconfig_togxb reconfig_to_xcvr [16:0] variable reconfig_fromgxb reconfig_from_xcvr Avalon MM Management Interface March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...

  • Page 212: Phy Ip Core For Pci Express Phy (Pipe)

    PHY IP core for PCI Express PHY (PIPE) parameters and the corresponding ALTGX megafunction parameters. Table 11–4. Comparison of ALTGX Megafunction and PHY IP Core for PCI Express PHY (PIPE) Parameters (Part 1 of 2) ALTGX Parameter Name (Default Value)

  • Page 213: Port Differences

    11–7 PHY IP Core for PCI Express PHY (PIPE) Table 11–4. Comparison of ALTGX Megafunction and PHY IP Core for PCI Express PHY (PIPE) Parameters (Part 2 of 2) ALTGX Parameter Name (Default Value) PCI Express PHY (PIPE) Parameter Name...
  • Page 214 11–8 Chapter 11: Migrating from Stratix IV to Stratix V Devices PHY IP Core for PCI Express PHY (PIPE) Table 11–5. PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals (Part 2 of 3) Stratix IV GX Device Signal Name...
  • Page 215 Chapter 11: Migrating from Stratix IV to Stratix V Devices 11–9 PHY IP Core for PCI Express PHY (PIPE) Table 11–5. PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals (Part 3 of 3) Stratix IV GX Device Signal Name...

  • Page 216: Custom Phy

    Chapter 11: Migrating from Stratix IV to Stratix V Devices Custom PHY Custom PHY This section lists the differences between the parameters and signals for the Custom PHY IP core and the ALTGX megafunction when configured in the Basic functional mode. Parameter Differences Table 11–6 lists the Custom PHY parameters and the corresponding ALTGX megafunction parameters.

  • Page 217: Port Differences

    [<p>-1:0] rx_coreclk rx_coreclkin tx_coreclk tx_coreclkin Avalon-ST TX Interface tx_datain tx_parallel_data [<d><n>-1:0] tx_ctrlenable tx_datak [<d><n>-1:0] rx_ctrldetect rx_datak [<d><n>-1:0] Avalon-ST RX Interface rx_dataout rx_parallel_data [<d><n>-1:0] rx_runningdisp rx_runningdisp [<d/8><n>-1:0] rx_enabyteord rx_enabyteord [<n>-1:0] March 2012 Altera Corporation Altera Transceiver PHY IP Core User Guide...
  • Page 218 Note to Table 11–7: (1) <n> = the number of lanes. <d> = the total deserialization factor from the pin to the FPGA fabric. Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...

  • Page 219: Additional Information

    Additional Information This chapter provides additional information about the document and Altera. Revision History The table below displays the revision history for the chapters in this user guide. Date Version Changes Made Custom March 2012 Added register definitions for address range 0x080–0x085. .
  • Page 220 Removed Enable tx_clkout feedback path for TX PLL from the General Options tab of the ■ December Deterministic Latency PHY IP Core GUI. This option is unavailable in 11.1 and 11.1 SP1. 2011 Changed definition of phy_mgmt_clk_reset. This signal is active high and level sensitive.
  • Page 221 Updated QSF settings to include text strings used to assign values and location of the ■ assignment which is either a pin or PLL. PHY IP Core for PCI Express (PIPE) March 2012 Altera Corporation Altera Transceiver PHY IP Core...
  • Page 222 PLL reconfiguration ■ DC gain and four-stage linear equalization for the RX channels ■ Removed Stratix IV device support. ■ Changed frequency range of phy_mgmt_clk to 100-125 MHz. ■ Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...
  • Page 223 ■ Transceiver Reconfiguration Controller IP Core chapter. Renamed Avalon-MM bus in for Transceiver Reconfiguration Controller reconfig_mgmt*. ■ Provided frequency range for phy_mgmt_clk for the XAUI PHY IP Core in Arria II GX, ■ July 2011 1.2.1 Cyclone IV GX, HardCopy IV, and Stratix IV GX devices.
  • Page 224 Added PLL support to lane rate parameter description in Table 5–2 on page 5–2. ■ Moved dynamic reconfiguration for the transceiver outside of the Interlaken PHY IP Core. ■ The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core. Added a reference to...
  • Page 225 Custom PHY Transceiver Added presets for the 3.25GbE and 1.25GbE protocols. ■ Moved dynamic reconfiguration for the transceiver outside of the Custom PHY IP Core. The ■ reconfiguration signals now connect to a separate Reconfiguration Controller IP Core. Removed device support for Arria II GX, Arria II GZ, HardCopy IV GX, and Stratix IV GX.
  • Page 226 ■ detail on size of reconfig_from_xcvr in Table 4–18 on page 4–23 December Removed table providing ordering codes for the Interlaken PHY IP core. Ordering codes are ■ 1.11 2010 not required for Stratix V devices using the hard implementation of the Interlaken PHY.
  • Page 227 Removed support for Stratix IV GX devices. ■ Transceiver Reconfiguration Controller Reconfiguration is now integrated into the XAUI PHY IP core and 10GBASE-R PHY IP core. ■ December 2010 Revised register map to show word addresses instead of a byte offset from a base address.

  • Page 228: How To Contact Altera

    (software licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Meaning Indicate command names, dialog box titles, dialog box options, and other GUI Bold Type with Initial Capital labels.
  • Page 229 Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. The feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document.
  • Page 230 Info–12 Additional InformationAdditional Information Typographic Conventions Altera Transceiver PHY IP Core March 2012 Altera Corporation User Guide...

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