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101 Innovation Drive

UG-01080

2015.01.12

San Jose, CA 95134

www.altera.com

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Page 1 Altera Transceiver PHY IP Core User Guide 101 Innovation Drive UG-01080 Subscribe 2015.01.12 San Jose, CA 95134 Send Feedback www.altera.com...
Page 2: Table Of Contents
TOC-2 Altera Transceiver PHY IP Core User Guide Contents Introduction to the Protocol-Specific and Native Transceiver PHYs....1-1 Protocol-Specific Transceiver PHYs......................1-1 Native Transceiver PHYs ...........................1-2 Non-Protocol-Specific Transceiver PHYs....................1-4 Transceiver PHY Modules..........................1-4 Transceiver Reconfiguration Controller....................1-5 Resetting the Transceiver PHY........................1-5 Running a Simulation Testbench......................
Page 3 TOC-3 Altera Transceiver PHY IP Core User Guide Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option......................4-1 10GBASE-KR PHY Release Information....................4-3 Device Family Support..........................4-3 10GBASE-KR PHY Performance and Resource Utilization..............4-3 Parameterizing the 10GBASE-KR PHY....................4-4 10GBASE-KR Link Training Parameters ..................4-5 10GBASE-KR Auto-Negotiation and Link Training Parameters..........
Page 4 TOC-4 Altera Transceiver PHY IP Core User Guide 1G/10GbE Control and Status Interfaces....................5-12 Register Interface Signals.......................... 5-14 1G/10GbE PHY Register Definitions .....................5-15 PMA Registers............................5-16 PCS Registers.............................. 5-17 1G/10 GbE GMII PCS Registers......................5-18 PMA Registers............................5-20 1G/10GbE Dynamic Reconfiguration from 1G to 10GbE..............5-21 1G/10GbE PHY Arbitration Logic Requirements.................5-22...
Page 5 TOC-5 Altera Transceiver PHY IP Core User Guide Interlaken PHY IP Core..................7-1 Interlaken PHY Device Family Support....................7-2 Parameterizing the Interlaken PHY......................7-3 Interlaken PHY General Parameters......................7-3 Interlaken PHY Optional Port Parameters....................7-5 Interlaken PHY Analog Parameters......................7-5 Interlaken PHY Interfaces.......................... 7-6 Interlaken PHY Avalon-ST TX Interface....................
Page 6 TOC-6 Altera Transceiver PHY IP Core User Guide Parameterizing the Custom PHY......................9-3 General Options Parameters......................9-3 Word Alignment Parameters......................9-7 Rate Match FIFO Parameters......................9-9 8B/10B Encoder and Decoder Parameters................. 9-10 Byte Order Parameters........................9-11 PLL Reconfiguration Parameters....................9-14 Analog Parameters.........................9-16 Presets for Ethernet........................9-16...
Page 7 TOC-7 Altera Transceiver PHY IP Core User Guide Interfaces for Deterministic Latency PHY................... 11-15 Data Interfaces for Deterministic Latency PHY..................11-16 Clock Interface for Deterministic Latency PHY................. 11-19 Optional TX and RX Status Interface for Deterministic Latency PHY..........11-20 Optional Reset Control and Status Interfaces for Deterministic Latency PHY......11-21 Register Interface and Descriptions for Deterministic Latency PHY..........
Page 8 TOC-8 Altera Transceiver PHY IP Core User Guide Bit Reversal and Polarity Inversion................... 13-20 Interfaces..............................13-23 Common Interface Ports......................13-23 Standard PCS Interface Ports.....................13-29 SDC Timing Constraints........................13-34 Dynamic Reconfiguration........................13-35 Simulation Support..........................13-36 Arria V GZ Transceiver Native PHY IP Core...........14-1 Device Family Support for Arria V GZ Native PHY................
Page 9 TOC-9 Altera Transceiver PHY IP Core User Guide Simulation Support..........................15-34 Transceiver Reconfiguration Controller IP Core Overview......16-1 Transceiver Reconfiguration Controller System Overview..............16-2 Transceiver Reconfiguration Controller Performance and Resource Utilization......16-5 Parameterizing the Transceiver Reconfiguration Controller IP Core..........16-5 Parameterizing the Transceiver Reconfiguration Controller IP Core in Qsys......... 16-6 General Options Parameters......................
Page 10 TOC-10 Altera Transceiver PHY IP Core User Guide Enabling the Standard PCS PRBS Verifier Using Streamer-Based Reconfiguration..16-46 Enabling the Standard PCS PRBS Generator Using Streamer-Based Reconfiguration ..16-47 Enabling the 10G PCS PRBS Generator or Verifier Using Streamer-Based Reconfiguration........................16-48 Disabling the Standard PCS PRBS Generator and Verifier Using Streamer-Based Reconfiguration ........................
Page 11 TOC-11 Altera Transceiver PHY IP Core User Guide Migrating from Stratix IV to Stratix V Devices Overview....... 20-1 Differences in Dynamic Reconfiguration for Stratix IV and Stratix V Transceivers....... 20-2 Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices......20-3 Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices........
Page 12: Introduction To The Protocol-Specific And Native Transceiver Phys
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 13: Native Transceiver Phys
UG-01080 Native Transceiver PHYs 2015.01.19 Figure 1-1: Transceiver PHY Top-Level Modules Transceiver PHY Avalon-MM PHY Management Avalon-MM Embedded PCS & PMA Control & Reset Controller Control & Status Status Read & Write Controller Register Memory Map Control & Status Registers...
Page 14 UG-01080 Native Transceiver PHYs 2015.01.19 Figure 1-2: Stratix V Transceiver Native PHY IP Core Transceiver Native PHY altera _xcvr_native_ <dev> TX PLL Reference Clock PLLs Serializer/ CDR Reference Clock Clock Generation RX PMA Parallel Data Block (when neither PCS is enabled)
Page 15: Non-Protocol-Specific Transceiver Phys
UG-01080 Non-Protocol-Specific Transceiver PHYs 2015.01.19 Datapaths Stratix V Arria V Arria V GZ Cyclone V Standard: This datapath provides a complete PCS and PMA for the TX and RX channels. You can customize the Standard datapath by enabling or disabling individual modules and specifying data widths.
Page 16: Transceiver Reconfiguration Controller
TX and RX channels are top-level ports of the transceiver PHY. You can use these ports to design a custom reset sequence, or you can use the Altera- provided Transceiver Reset Controller IP Core.
Page 17: Running A Simulation Testbench
UG-01080 Running a Simulation Testbench 2015.01.19 The Transceiver PHY Reset Controller IP Core handles all reset sequencing of the transceiver to enable successful operation. Because the Transceiver PHY Reset Controller IP is available in clear text, you can also modify it to meet your requirements. For more information about the Transceiver PHY Reset Controller, refer to Transceiver Reconfiguration Controller IP Core.
Page 18 UG-01080 Running a Simulation Testbench 2015.01.19 Figure 1-3: Directory Structure for Generated Files <project_dir> <instance_name>. v or .vhd - the parameterized transceiver PHY IP core <instance_name> .qip - lists all files used in the transceiver PHY IP design <instance_name> .bsf - a block symbol file for you transceiver PHY IP core <project_dir>/<instance_name>...
Page 19 UG-01080 Running a Simulation Testbench 2015.01.19 File Name Description sv_xcvr_native.sv Defines the transceiver. It includes instantiations of the PCS and PMA modules and Avalon-MM PHY management interface. stratixv_hssi_ <module_name> _rbc. sv These files perform rule based checking for the module specified. For example, if the PLL type, data rate, and FPGA fabric transceiver interface width are not compatible, the checker reports an error.
Page 20: Unsupported Features
<ACDS installation path>\quartus\sopc_builder\bin\ip-make-simscript --help Related Information • Mentor Graphics ModelSim Support Simulating Altera Designs • Unsupported Features The protocol-specific and native transceiver PHYs are not supported in Qsys in the current release. Introduction to the Protocol-Specific and Native Transceiver PHYs...
Page 21: Getting Started Overview
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 22: Design Flows
• Allows you to parameterize an IP core variant and instantiate into an existing design • For some IP cores, this flow generates a complete example design and testbench Altera IP cores may or may not support the Qsys and SOPC Builder design flows. Getting Started Overview...
Page 23: Megawizard Plug-In Manager Flow
VHDL or Verilog HDL simulators. For some cores, only the plain text RTL model is generated, and you can simulate that model. Note: For more information about functional simulation models for Altera IP cores, refer to Simulating Altera Designs in volume 3 of the Quartus II Handbook.
Page 24: Simulate The Ip Core
For a complete list of models or libraries required to simulate your IP core, refer to the scripts provided with the testbench. For more information about simulating Altera IP cores, refer to Simulating Altera Designs in volume 3 of the Quartus II Handbook.
Page 25: 10Gbase-R Phy Ip Core
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 26 UG-01080 10GBASE-R PHY IP Core 2015.01.19 To make the most effective use of this soft PCS and PMA configuration for Stratix IV GT devices, you can group up to four channels in a single quad and control their functionality using one Avalon-MM PHY management bridge, transceiver reconfiguration module, and low controller.
Page 27 UG-01080 10GBASE-R PHY IP Core 2015.01.19 Figure 3-3: 10GBASE-R PHY IP Core In Arria V GT Devices Arria V GT 10GBASE-R Top Level Arria V GT 10GBASE-R Avalon-ST Streaming Tx Data Rx Data Data Data TX PMA Wiring Control & Status...
Page 28 UG-01080 10GBASE-R PHY IP Core 2015.01.19 Figure 3-4: 10GBASE-R PHY IP Core In Arria V GZ Devices Transceiver Protocol Arria V GZ Transceiver Protocol Avalon-ST Tx Data Streaming Generic Rx Data Data Data PLD-PCS & Duplex PCS TX PMA Wiring Control &...
Page 29 UG-01080 10GBASE-R PHY IP Core 2015.01.19 Figure 3-5: 10GBASE-R PHY IP Core In Stratix V Devices Transceiver Protocol Stratix V Transceiver Protocol Avalon-ST Tx Data Streaming Generic Rx Data Data Data PLD-PCS & Duplex PCS TX PMA Wiring Control & Status...
Page 30: 10Gbase-R Phy Release Information
10GBASE-R PHY Device Family Support Device support for the IP core. IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: • Final support—Verified with final timing models for this device.
Page 31: 10Gbase-R Phy Performance And Resource Utilization For Stratix Iv Devices
UG-01080 10GBASE-R PHY Performance and Resource Utilization for Stratix IV Devices 2015.01.19 Device Family Support Arria V ST devices-Soft PCS and Hard PMA Final Arria V GZ Final Stratix IV GT devices–Soft PCS and Hard PMA Final Stratix V devices–Hard PCS and PMA...
Page 32: 10Gbase-R Phy Performance And Resource Utilization For Arria V Gz And Stratix V Devices
0 PPM -200 PPM +200 PPM Note: If latency is critical, Altera recommends designing your own soft 10GBASE-R PCS and connecting to the Low Latency PHY IP Core. Parameterizing the 10GBASE-R PHY The 10GBASE-R PHY IP Core is available for the Arria V, Arria V GZ, Stratix IV, or Stratix V device families.
Page 33: General Option Parameters
Another advantage of the ATX PLL is that it does not use a transceiver channel, while the CMU PLL does. Altera recommends the ATX PLL for data rates <= 8 Gbps. Reference Clock Frequency Arria V and Stratix V devices support both frequen‐...
Page 34 UG-01080 3-10 General Option Parameters 2015.01.19 Name Value Description PCS / PMA interface width For Stratix V and Arria V GZ devices only: Specifies the data interface width between the 10G PCS and the transceiver PMA. Smaller width corresponds to lower PCS latency but higher frequency.
Page 35 UG-01080 3-11 General Option Parameters 2015.01.19 Name Value Description Enable embedded reset control On/Off When On, the automatic reset controller initiates the reset sequence for the transceiver. When Off you can design your own reset logic using tx_analogr- eset rx_analogreset...
Page 36: Analog Parameters For Stratix Iv Devices
UG-01080 3-12 Analog Parameters for Stratix IV Devices 2015.01.19 pma_bonding_master to the 10GBASE-R instance name. You must substitute the instance name from your design for the instance name shown in quotation marks. set_parameter -name pma_bonding_master "\"1\"" -to "<PHY IP instance name>"...
Page 37: 10Gbase-R Phy Interfaces
UG-01080 3-13 10GBASE-R PHY Interfaces 2015.01.19 Name Value Description Receiver common mode Specifies the RX common mode voltage. Tri-State voltage 0.82V 1.1v Receiver termination Indicates the value of the termination resistor for OCT_85_OHMS resistance the receiver. OCT_100_OHMs OCT_120_OHMS OCT_150_OHMS Receiver DC...
Page 38: 10Gbase-R Phy Data Interfaces
UG-01080 3-14 10GBASE-R PHY Data Interfaces 2015.01.19 Figure 3-6: 10GBASE-R PHY Top-Level Signals 10GBASE-R Top-Level Signals rx_serial_data<n> xgmii_tx_dc<n>[71:0] Transceiver tx_serial_data<n> SDR XGMII TX tx_ready Serial Data Inputs from MAC xgmii_tx_clk gxb_pdn External pll_pdn xgmii_rx_dc<n>[71:0] PMA Control SDR XGMII RX cal_blk_pdn...
Page 39 UG-01080 3-15 10GBASE-R PHY Data Interfaces 2015.01.19 Signal Name Direction Description Input Contains 8 lanes of data and control for xgmii_tx_dc_[<n>71:0] XGMII. Each lane consists of 8 bits of data and 1 bit of control. • Lane 0-[7:0]/[8] • Lane 1-[16:9]/[17] •...
Page 40 UG-01080 3-16 10GBASE-R PHY Data Interfaces 2015.01.19 Signal Name Direction Description Output When asserted, indicates that the PCS is rx_data_ready [<n>-1:0] sending data to the MAC. Because the on this Avalon-ST interface is 0, readyLatency the MAC must be ready to receive data whenever this signal is asserted.
Page 41: 10Gbase-R Phy Status, 1588, And Pll Reference Clock Interfaces
UG-01080 3-17 10GBASE-R PHY Status, 1588, and PLL Reference Clock Interfaces 2015.01.19 Signal Name XGMII Signal Name Description Lane 4 control xgmii_tx_dc_[44] xgmii_sdr_ctrl[4] Lane 5 data xgmii_tx_dc_[52:45] xgmii_sdr_data[47:40] Lane 5 control xgmii_tx_dc_[53] xgmii_sdr_ctrl[5] Lane 6 data xgmii_tx_dc_[61:54] xgmii_sdr_data[55:48] Lane 6 control...
Page 42: Optional Reset Control And Status Interface
UG-01080 3-18 Optional Reset Control and Status Interface 2015.01.19 Table 3-13: 10GBASE-R Status, 1588, and PLL Reference Clock Outputs Signal Name Direction Description Output Asserted to indicate that the block synchron‐ rx_block_lock izer has established synchronization. Output Asserted by the BER monitor block to...
Page 43: 10Gbase-R Phy Clocks For Arria V Gt Devices
UG-01080 3-19 10GBASE-R PHY Clocks for Arria V GT Devices 2015.01.19 Signal Name Direction Description Input When asserted, reset all blocks in the TX PCS. If tx_digitalreset[<n>-1:0] your design includes bonded TX PCS channels, refer to Timing Constraints for Reset Signals when Using Bonded PCS Channels for a SDC constraint you must include in your design.
Page 44: 10Gbase-R Phy Clocks For Arria V Gz Devices
UG-01080 3-20 10GBASE-R PHY Clocks for Arria V GZ Devices 2015.01.19 Figure 3-7: Arria V GT Clock Generation and Distribution 10GBASE-R Transceiver Channel - Arria V GT TX PCS TX PMA 10.3125 Gbps (soft) (hard) 161.1328 MHz xgmii_tx_clk pll_ref_clk TX PLL 156.25 MHz...
Page 45: 10Gbase-R Phy Clocks For Stratix Iv Devices
UG-01080 3-21 10GBASE-R PHY Clocks for Stratix IV Devices 2015.01.19 Figure 3-8: Arria V GZ Clock Generation and Distribution 10GBASE-R Hard IP Transceiver Channel - Arria V GZ 10.3125 64-bit data, 8-bit control Gbps serial TX PCS TX PMA xgmii_tx_clk pll_ref_clk 644.53125 MHz...
Page 46: 10Gbase-R Phy Clocks For Stratix V Devices
UG-01080 3-22 10GBASE-R PHY Clocks for Stratix V Devices 2015.01.19 Figure 3-9: Stratix IV Clock Generation and Distribution 10GBASE-R Transceiver Channel - Stratix IV GT 10.3125 64-bit data, 8-bit control Gbps serial TX PCS TX PCS TX PMA (soft IP)
Page 47: 10Gbase-R Phy Register Interface And Register Descriptions
UG-01080 3-23 10GBASE-R PHY Register Interface and Register Descriptions 2015.01.19 Figure 3-10: Stratix V Clock Generation and Distribution 10GBASE-R Hard IP Transceiver Channel - Stratix V 10.3125 64-bit data, 8-bit control Gbps serial TX PCS TX PMA xgmii_tx_clk pll_ref_clk 644.53125 MHz TX PLL 257.8125...
Page 48 UG-01080 3-24 10GBASE-R PHY Register Interface and Register Descriptions 2015.01.19 Table 3-15: Avalon-MM PHY Management Interface Signal Name Direction Description Input The clock signal that controls the Avalon-MM phy_mgmt_clk PHY management, interface. For Stratix IV devices, the frequency range is 37.5-50 MHz.
Page 49 UG-01080 3-25 10GBASE-R PHY Register Interface and Register Descriptions 2015.01.19 Word Addr Name Description 0x021 [31:0] Writing a 1 to channel <n> powers cal_blk_powerdown down the calibration block for channel <n>. This register is only available if you select Use external PMA control and reconfig on the Additional Options tab of the GUI.
Page 50 UG-01080 3-26 10GBASE-R PHY Register Interface and Register Descriptions 2015.01.19 Word Addr Name Description [31:0] You can use the reset_fine_control reset_fine_ register to create your own control reset sequence. The reset control module performs a standard reset sequence at power on and whenever is asserted.
Page 51 UG-01080 3-27 10GBASE-R PHY Register Interface and Register Descriptions 2015.01.19 Word Addr Name Description 0x067 [31:0] When asserted, indicates that the RX pma_rx_is_lockedtoref CDR PLL is locked to the reference clock. Bit <n> corresponds to channel <n>. 10GBASE-R PCS Provides for indirect addressing of all PCS control and status registers.
Page 52: 10Gbase-R Phy Dynamic Reconfiguration For Stratix Iv Devices
UG-01080 3-28 10GBASE-R PHY Dynamic Reconfiguration for Stratix IV Devices 2015.01.19 Word Addr Name Description [5:0] For Stratix IV devices only, records BER_COUNT[5:0] the bit error rate (BER). From block: BER monitor [13:6] For Stratix IV devices only, records ERROR_BLOCK_COUNT[7:0] the number of blocks that contain errors.
Page 53: 10Gbase-R Phy Dynamic Reconfiguration For Arria V And Stratix V Devices
UG-01080 3-29 10GBASE-R PHY Dynamic Reconfiguration for Arria V and Stratix V Devices 2015.01.19 Signal Name Direction Description Output Reconfiguration RAM. The PHY device drives this reconfig_from_xcvr [(<n>/4) RAM data to the transceiver reconfiguration IP. This 17-1:0] signal is only available in Stratix IV devices.
Page 54: 1588 Delay Requirements
UG-01080 3-30 1588 Delay Requirements 2015.01.19 1588 Delay Requirements The 1588 protocol requires symmetric delays or known asymmetric delays for all external connections. In calculating the delays for all external connections, you must consider the delay contributions of the following elements: •...
Page 55 UG-01080 3-31 10GBASE-R PHY TimeQuest Timing Constraints 2015.01.19 set_clock_uncertainty -from [get_clocks {*siv_alt_pma|pma_ch*.pma_direct| receive_pcs*|clkout}] -to pll_ref_clk -setup 0.1 set_clock_uncertainty -from [get_clocks {*siv_alt_pma|pma_direct| auto_generated|transmit_pcs0|clkout}] -to pll_ref_clk -setup 0.08 set_clock_uncertainty -from [get_clocks {*siv_alt_pma|pma_ch*.pma_direct| receive_pcs*|clkout}] -to pll_ref_clk -hold 0.1 set_clock_uncertainty -from [get_clocks {*siv_alt_pma|pma_direct| auto_generated|transmit_pcs0|clkout}] -to pll_ref_clk -hold 0.08...
Page 56: 10Gbase-R Phy Simulation Files And Example Testbench
UG-01080 3-32 10GBASE-R PHY Simulation Files and Example Testbench 2015.01.19 Note: The SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHY IP apply to all other transceiver PHYs listed in this user guide. Refer to SDC Timing Constraints of Stratix V Native PHY for details.
Page 57: Backplane Ethernet 10Gbase-Kr Phy Ip Core With Early Access Fec Option
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 58 TX PMDs for the lowest Bit Error Rate (BER). LT is defined in Clause 72 of IEEE Std 802.3ap-2007. • Auto negotiation (AN)—The Altera 10GBASE-KR PHY IP Core can auto-negotiate between 1000BASE-KX (1GbE) and 10GBASE-KR (10GbE) PHY types. The AN function is mandatory for Backplane Ethernet.
Page 59: 10Gbase-Kr Phy Release Information
All speed grades except I4 and C4 Other device families No support Altera verifies that the current version of the Quartus II software compiles the previous version of each IP MegaCore IP Library Release Notes and core. Any exceptions to this verification are reported in the Errata.
Page 60: Parameterizing The 10Gbase-Kr Phy
UG-01080 Parameterizing the 10GBASE-KR PHY 2015.01.19 The following table shows the typical expected resource utilization for selected configurations using the current version of the Quartus II software targeting a Stratix V GT (5SGTMC7K2F40C2) device. The numbers of ALMs and logic registers are rounded up to the nearest 100. Resource utilization numbers reflect changes to the resource utilization reporting starting in the Quartus II software v14.1 release for 28...
Page 61: 10Gbase-Kr Link Training Parameters
UG-01080 10GBASE-KR Link Training Parameters 2015.01.19 Related Information • 10GBASE-KR Link Training Parameters on page 4-5 10GBASE-KR Auto-Negotiation and Link Training Parameters • on page 4-7 10GBASE-R Parameters • on page 4-7 • 1GbE Parameters on page 4-9 Speed Detection Parameters •...
Page 62 UG-01080 10GBASE-KR Link Training Parameters 2015.01.19 Name Value Description VMINRULE Specifies the minimum V . The default value is 9 0-63 which represents 165 mV. VODMINRULE Specifies the minimum V for the first tap. The 0-63 default value is 22 which represents 440mV.
Page 63: 10Gbase-Kr Auto-Negotiation And Link Training Parameters
UG-01080 10GBASE-KR Auto-Negotiation and Link Training Parameters 2015.01.19 10GBASE-KR Auto-Negotiation and Link Training Parameters Table 4-5: Auto Negotiation and Link Training Settings Name Range Description AN_PAUSE Pause Ability Depends upon MAC. Local device pause capability C2:0 = D12:10 of AN word.
Page 64 UG-01080 10GBASE-R Parameters 2015.01.19 Parameter Name Options Description Reference clock frequency 644.53125MHz Specifies the input reference clock frequency. The default is 322.265625MHz. 322.265625MHz PLL Type Specifies the PLL type. You can specify either a CMU or ATX PLL. The ATX PLL has better jitter performance at higher data rates than the CMU PLL.
Page 65: 1Gbe Parameters
UG-01080 1GbE Parameters 2015.01.19 Parameter Name Options Description Enable FEC status ports On/Off When you turn this option the core includes the rx_block_lock rx_parity_good rx_parity_ , and signals. invalid tx_frame Note: This parameter is not implemented in the early access release.
Page 66: Speed Detection Parameters
UG-01080 4-10 Speed Detection Parameters 2015.01.19 Speed Detection Parameters Selecting the speed detection option gives the PHY the ability to detect to link partners that support 1G/ 10GbE but have disabled Auto-Negotiation. During Auto-Negotiation, if AN cannot detect Differential Manchester Encoding (DME) pages from a link partner, the Sequencer reconfigures to 1GE and 10GE modes (Speed/Parallel detection) until it detects a valid 1G or 10GbE pattern.
Page 67 2015.01.19 In this figure, the colors have the following meanings: • Green-Altera- Cores available Quartus II IP Library, including the 1G/10Gb Ethernet MAC, the Reset Controller, and Transceiver Reconfiguration Controller. • Orange-Arbitration Logic Requirements. Logic you must design, including the Arbiter and State Machine.
Page 68 UG-01080 4-12 10GBASE-KR PHY IP Core Functional Description 2015.01.19 • An embedded processor mode to override the state-machine-based training algorithm. This mode allows an embedded processor to establish link data rates instead of establishing the link using the state-machine-based training algorithm.
Page 69 UG-01080 4-13 10GBASE-KR PHY IP Core Functional Description 2015.01.19 Figure 4-4: TX Equalization in Daisy-Chain Mode Partner A Parter B Encode Decode dmi* Handshake Ack Change dmo* dmo* Adapt Change Adapt Change Eq Change Eq dmi* Handshake Decode Encode Parter C...
Page 70: 10Gbase-Kr Phy Arbitration Logic Requirements
UG-01080 4-14 10GBASE-KR PHY Arbitration Logic Requirements 2015.01.19 Auto negotiation with XAUI is not supported. Auto negotiation is run upon power up or if the auto negotiation module is reset. The following figures illustrate the handshaking between the Auto Negotiation, Link Training, Sequencer and Transceiver Reconfiguration Controller blocks.
Page 71: 10Gbase-Kr Phy State Machine Logic Requirements
UG-01080 4-15 10GBASE-KR PHY State Machine Logic Requirements 2015.01.19 • Channel number—specifies the requested channel • Mode—specifies 1G or 10G data modes or AN or LT modes for the corresponding channel 2. Select a channel for reconfiguration and send an ack/busy signal to the requestor. The requestor should deassert its request signal when the ack/busy is received.
Page 72 UG-01080 4-16 Forward Error Correction (Clause 74) 2015.01.19 Figure 4-7: FEC Functional Block Diagram XGMII Transmit Encode Decode Receive Clause 49 Scramble Descramble Gearbox BER and Sync Block Sync Header Monitor FEC (2112,2080) Encoder FEC (2112,2080) Decoder and Block Sync...
Page 73 UG-01080 4-17 Forward Error Correction (Clause 74) 2015.01.19 Figure 4-8: FEC Codeword Format 64 Bit Payload Word 0 64 Bit Payload Word 1 64 Bit Payload Word 2 64 Bit Payload Word 3 64 Bit Payload Word 4 64 Bit Payload Word 5...
Page 74 UG-01080 4-18 Forward Error Correction (Clause 74) 2015.01.19 • FEC Block Synchronizer: The FEC block synchronizer achieves FEC block delineation by locking to correctly received FEC blocks. An algorithm with hysteresis maintains block and word delineation. • FEC Descrambler: The FEC descrambler descrambles the received data to regenerate unscrambled data utilizing the original FEC scrambler polynomial.
Page 75: 10Base-Kr Phy Interfaces
UG-01080 4-19 10BASE-KR PHY Interfaces 2015.01.19 10BASE-KR PHY Interfaces Figure 4-10: 10GBASE-KR Top-Level Signals 10GBASE-KR Top-Level Signals rx_serial_data xgmii_tx_dc[71:0] Transceiver tx_serial_data xgmii_tx_clk Serial Data xgmii_rx_dc[71:0] reconfig_to_xcvr[(<n>70-1):0] xgmii_rx_clk reconfig_from_xcvr[(<n>46-1):0] gmii_tx_d[7:0] rc_busy gmii_rx_d[7:0] lt_start_rc XGMII gmii_tx_en main_rc[5:0] gmii_tx_err and GMII post_rc[4:0] gmii_rx_err...
Page 76: 10Gbase-Kr Phy Clock And Reset Interfaces
If you instantiate multiple channels within a transceiver bank they share TX PLLs. If a reset is applied to this PLL, it will affect all channels. Altera recommends leaving the TX PLL free-running after the start-up reset sequence is completed. After a channel is reconfigured you can simply reset the digital portions of that specific channel instead of going through the entire reset sequence.
Page 77 UG-01080 4-21 10GBASE-KR PHY Clock and Reset Interfaces 2015.01.19 Table 4-10: Clock and Reset Signals Signal Name Direction Description Output The RX clock which is recovered from the received rx_recovered_clk data. You can use this clock as a reference to lock an external clock source.
Page 78: 10Gbase-Kr Phy Data Interfaces
UG-01080 4-22 10GBASE-KR PHY Data Interfaces 2015.01.19 Transceiver Reconfiguration Controller IP Core Overview • on page 16-1 10GBASE-KR PHY Data Interfaces The following table describes the signals in the XGMII and GMII interfaces. The MAC drives the TX XGMII and GMII signals to the 10GBASE-KR PHY. The 10GBASE-KR PHY drives the RX XGMII or GMII signals to the MAC.
Page 79 UG-01080 4-23 10GBASE-KR PHY XGMII Mapping to Standard SDR XGMII Data 2015.01.19 10GBASE-KR GMII Data Interface Output When asserted, indicates an error. May be asserted gmii_rx_err at any time during a frame transfer to indicate an error in that frame.
Page 80 UG-01080 4-24 10GBASE-KR PHY Serial Data Interface 2015.01.19 Signal Name SDR XGMII Signal Name Description Lane 5 data xgmii_tx_dc[52:45] xgmii_sdr_data[47:40] Lane 5 control xgmii_tx_dc[53] xgmii_sdr_ctrl[5] Lane 6 data xgmii_tx_dc[61:54] xgmii_sdr_data[55:48] Lane 6 control xgmii_tx_dc[62] xgmii_sdr_ctrl[6] Lane 7 data xgmii_tx_dc[70:63] xgmii_sdr_data[63:56]...
Page 81: 10Gbase-Kr Phy Control And Status Interfaces
UG-01080 4-25 10GBASE-KR PHY Control and Status Interfaces 2015.01.19 10GBASE-KR PHY Control and Status Interfaces The 10GBASE-KR XGMII and GMII interface signals drive data to and from PHY. Table 4-14: Control and Status Signals Signal Name Direction Description Output Asserted to indicate that the block synchronizer has rx_block_lock established synchronization.
Page 82 UG-01080 4-26 10GBASE-KR PHY Control and Status Interfaces 2015.01.19 Signal Name Direction Description input. The random error without a rate ref_clk_1g match FIFO mode is: • +/- 1 ns at 1000 Mbps • +/- 5 ns at 100 Mbps • +/- 25 ns at 10 Mbps...
Page 83: Daisy-Chain Interface Signals
UG-01080 4-27 Daisy-Chain Interface Signals 2015.01.19 Signal Name Direction Description Output When you enable 1588, this signal outputs the real rx_latency_adj_10g[15:0] time latency in XGMII clock cycles (156.25 MHz) for the RX PCS and PMA datapath for 10G mode. Bits 0 to 9 represent the fractional number of clock cycles.
Page 84: Embedded Processor Interface Signals
UG-01080 4-28 Embedded Processor Interface Signals 2015.01.19 Table 4-15: Daisy Chain Interface Signals Signal Name Direction Description Input When asserted, enable Daisy Chain mode. dmi_mode_en Input When asserted, the daisy chain state machine has dmi_frame_lock locked to the training frames.
Page 85: Dynamic Reconfiguration Interface Signals
UG-01080 4-29 Dynamic Reconfiguration Interface Signals 2015.01.19 Table 4-16: Embedded Processor Interface Signals Signal Name Direction Description Input When asserted, enables embedded processor mode. upi_mode_en Input Selects the active tap. The following encodings are upi_adj[1:0] defined: • 2'b01: Main tap •...
Page 86 UG-01080 4-30 Dynamic Reconfiguration Interface Signals 2015.01.19 Signal Name Direction Description Output Reconfiguration signals to the Reconfiguration reconfig_from_xcvr Design Example. <n> grows linearly with the [(<n>46-1):0] number of reconfiguration interfaces. Input When asserted, indicates that reconfiguration is in rc_busy progress.
Page 87 UG-01080 4-31 Dynamic Reconfiguration Interface Signals 2015.01.19 Signal Name Direction Description Output Specifies the PCS mode for reconfig using 1-hot pcs_mode_rc[5:0] encoding. The following modes are defined: • 6'b000001: Auto-Negotiation mode • 6'b000010: Link Training mode • 6'b000100: 10GBASE-KR data mode •...
Page 88: Register Interface Signals
UG-01080 4-32 Register Interface Signals 2015.01.19 Signal Name Direction Description Input Link training requires RX equalization to be rxeq_done complete. Tie this signal to 1 to indicate that RX equalization is complete. Register Interface Signals The Avalon-MM master interface signals provide access to all registers.
Page 89 UG-01080 4-33 10GBASE-KR PHY Register Definitions 2015.01.19 Notes: • Unless otherwise indicated, the default value of all registers is 0. • Writing to reserved or undefined register addresses may have undefined side effects. • To avoid any unspecified bits to be erroneously overwritten, you must perform read-modify-writes to change the register values.
Page 90 UG-01080 4-34 10GBASE-KR PHY Register Definitions 2015.01.19 Word Name Description Addr When set to 1, indicates that the core is requesting the FEC Assert KR FEC ability. When this bit changes, you must assert the Request Reset SEQ bit (0xB0[0]) to renegotiate with the new value.
Page 91 UG-01080 4-35 10GBASE-KR PHY Register Definitions 2015.01.19 Word Name Description Addr 0xB4 31:0 Counts the number of uncorrectable FEC blocks. Resets to 0 FEC Uncorrected when read. Otherwise, it holds at the maximum count and Blocks does not roll over. Refer to Clause 74.8.4.1 of IEEE 802.3ap- 2000 for details.
Page 92 UG-01080 4-36 10GBASE-KR PHY Register Definitions 2015.01.19 Word Name Description Addr When set to 1, fault information has been sent to the link AN ADV Remote partner. When 0, a fault has not occurred. The current value Fault clears when the register is read. Remote Fault (RF) is encoded in bit D13 of the base Link Codeword.
Page 93 UG-01080 4-37 10GBASE-KR PHY Register Definitions 2015.01.19 Word Name Description Addr • [4:0]: Selector • [9:5]: Echoed nonce which are set by the state machine • [12:10]: Pause bits • [13]: Remote Fault bit • [14]: ACK which is controlled by the SM •...
Page 94 UG-01080 4-38 10GBASE-KR PHY Register Definitions 2015.01.19 Word Name Description Addr 0xC5 15:0 The Auto-Negotiation TX state machine uses these bits if the User Next page Auto-Negotiation next pages ctrl bit is set. The following bits are defined: • [11]: Toggle bit •...
Page 95 UG-01080 4-39 10GBASE-KR PHY Register Definitions 2015.01.19 Word Name Description Addr 24:0 Received technology ability field bits of Clause 73 AN LP ADV Tech_ Auto-Negotiation. The 10GBASE-KR PHY supports A0 and A[24:0] A2. The following protocols are defined: • A0 1000BASE-KX •...
Page 96 UG-01080 4-40 10GBASE-KR PHY Register Definitions 2015.01.19 Word Name Description Addr Specifies the number of equalization steps for each main tap main_step_cnt update. There are about 20 settings for the internal algorithm [3:0] to test. The valid range is 1-15. The default value is 4'b0010.
Page 97 UG-01080 4-41 10GBASE-KR PHY Register Definitions 2015.01.19 Word Name Description Addr 22:20 RW RX CTLE mode in the Link Training algorithm. The default rx_ctle_mode value is 3'b000. The following encodings are defined: • 3'b000: CTLE tuning in link training is disabled. Retains user set value of CTLE.
Page 98 UG-01080 4-42 10GBASE-KR PHY Register Definitions 2015.01.19 Word Name Description Addr When set to 1, the receiver is trained and is ready to receive Link Trained - data. When set to 0, receiver training is in progress. For more Receiver status information, refer to the state variable rx_trained as defined in Clause 72.6.10.3.1 and bit 10GBASE-KR PMD control...
Page 99 UG-01080 4-43 10GBASE-KR PHY Register Definitions 2015.01.19 Word Name Description Addr 19:10 RW Specifies the number of thousands of training frames to ber_time_k_frames examine for bit errors on the link for each step of the equalization settings. Set ber_time_m_frames = 0 for time/ bits to match the following values: •...
Page 100 UG-01080 4-44 10GBASE-KR PHY Register Definitions 2015.01.19 Word Name Description Addr 13:8 Status report register for the contents of the second, 16-bit LD coefficient word of the training frame most recently sent from the local status[5:0] device control channel. The following fields are defined: •...
Page 101 UG-01080 4-45 10GBASE-KR PHY Register Definitions 2015.01.19 Word Name Description Addr When set to 1, The local device TX coefficients are set to a LP Preset state where equalization is turned off. Preset coefficients are Coefficients used. When set to 0, the local device operates normally. The function and values of the preset bit is defined in 72.6.10.2.3.1.
Page 102 UG-01080 4-46 10GBASE-KR PHY Register Definitions 2015.01.19 Word Name Description Addr Stores the most recent V setting that LT specified using the LT V setting Transceiver Reconfiguration Controller IP core. It reflects Link Partner commands to fine-tune the V 12:8...
Page 103: Pma Registers
UG-01080 4-47 PMA Registers 2015.01.19 Word Name Description Addr Override value for the VPOSTRULE parameter. When 20:16 RW LT VPOST ovrd enabled, this value substitutes for the VPOSTRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.
Page 104: Pcs Registers
UG-01080 4-48 PCS Registers 2015.01.19 Addr Access Name Description 0x64 [31:0] When set, programs the RX CDR PLL to lock to the pma_rx_set_ incoming data. locktodata 0x65 [31:0] When set, programs the RX clock data recovery pma_rx_set_ (CDR) PLL to lock to the reference clock.
Page 105: Creating A 10Gbase-Kr Design
UG-01080 4-49 Creating a 10GBASE-KR Design 2015.01.19 Table 4-22: PCS Registers Addr Acce Name Description 0x80 31:0 Because the PHY implements a single channel, this Indirect_addr register must remain at the default value of 0 to specify logical channel 0.
Page 106: Editing A 10Gbase-Kr Mif File
PHY into low latency mode during AN/LT. These MIFs are the three configurations used in the MIF streaming process. The example design contains five required MIFs (1G, 10G, 1G with 1588,10G with 1588 and AN/LT). Altera recommends that you use these MIFs even if you are not using the example design.
Page 107 UG-01080 4-51 Editing a 10GBASE-KR MIF File 2015.01.19 Example 4-1: Edits to a MIF to Remove PMA Settings Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option Altera Corporation Send Feedback...
Page 108: Design Example
UG-01080 4-52 Design Example 2015.01.19 Design Example Figure 4-12: PHY-Only Design Example with Two Backplane Ethernet and Two Line-Side (1G/10G) Ethernet Channels NF_DE_WRAPPER Test Harness TH0_ADDR = 0xF nnn Management Master XGMII XGMII XGMII XGMII Test Harness TH1_ADDR = 0xE nnn...
Page 109: Sdc Timing Constraints
Link partner, to which the LD is connected. Media Access Control. Media independent interface. Open System Interconnection. Physical Coding Sublayer. Physical Layer in OSI 7-layer architecture, also in Altera device scope is: PCS + PMA. Physical Medium Attachment. Physical Medium Dependent. SGMII Serial Gigabit Media Independent Interface.
Page 110: 1G/10 Gbps Ethernet Phy Ip Core
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 111: 1G/10Gbe Phy Release Information
UG-01080 1G/10GbE PHY Release Information 2015.01.19 Figure 5-1: Level Modules of the 1G/10GbE PHY MegaCore Function Altera Device with 10.3125+ Gbps Serial Transceivers 1G/10Gb Ethernet PHY MegaCore Function Native PHY Hard IP 257.8 1 Gb SFP / Serial TX XGMII Data...
Page 112: Device Family Support
All speed grades except I4 and C4 Other device families No support Altera verifies that the current version of the Quartus II software compiles the previous version of each IP core. Any exceptions to this verification are reported in the MegaCore IP Library Release Notes and Errata.
Page 113: Parameterizing The 1G/10Gbe Phy
UG-01080 Parameterizing the 1G/10GbE PHY 2015.01.19 PHY Module Options ALMs M20K Memory Logic Registers 1GbE/10GbE - 1GbE only with Sequencer 1GbE/10GbE - 1GbE/10GbE 1000 2000 with 1588 1GbE/10GbE - 1GbE/10GbE 1100 2000 with 1588 and Sequencer Parameterizing the 1G/10GbE PHY The 1G/10GbE PHY IP Core is available for the Arria V GZ and Stratix V device families.
Page 114: Speed Detection Parameters
UG-01080 Speed Detection Parameters 2015.01.19 Parameter Name Options Description Enable IEEE 1588 Precision Time On/Off When you turn this option On, the core includes Protocol a module in the PCS to implement the IEEE 1588 Precision Time Protocol. PHY ID (32 bit)
Page 115: Phy Analog Parameters
UG-01080 PHY Analog Parameters 2015.01.19 Parameter Name Options Description Link fail inhibit time for 10Gb Specifies the time before is set to 504 ms link_status Ethernet FAIL or OK. A link fails if the link_fail_ has expired before inhibit_time link_status is set to OK.
Page 116: 1G/10Gbe Phy Interfaces
UG-01080 1G/10GbE PHY Interfaces 2015.01.19 1G/10GbE PHY Interfaces Figure 5-2: 1G/10GbE PHY Top-Level Signals 1G/10GbE Top-Level Signals rx_serial_data xgmii_tx_dc[71:0] Transceiver tx_serial_data xgmii_tx_clk Serial Data xgmii_rx_dc[71:0] reconfig_to_xcvr[(<n>70-1):0] xgmii_rx_clk reconfig_from_xcvr[(<n>46-1):0] gmii_tx_d[7:0] rc_busy gmii_rx_d[7:0] lt_start_rc gmii_tx_en XGMII main_rc[5:0] gmii_tx_err and GMII post_rc[4:0] gmii_rx_err...
Page 117: 1G/10Gbe Phy Clock And Reset Interfaces
For more informa‐ rx_digitalreset tion about reset, refer to the "Transceiver PHY Reset IP Core" chapter in the Altera Transceiver PHY IP Core User Guide. is the Avalon-MM reset signal.
Page 118: 1G/10Gbe Phy Data Interfaces
UG-01080 1G/10GbE PHY Data Interfaces 2015.01.19 Table 5-6: Clock and Reset Signals Signal Name Direction Description Output The RX clock which is recovered from the received rx_recovered_clk data. You can use this clock as a reference to lock an external clock source. Its frequency is 125 or 156.25 MHz.
Page 119 UG-01080 5-10 1G/10GbE PHY Data Interfaces 2015.01.19 Signal Name Direction Description Input XGMII data and control for 8 lanes. Each lane xgmii_tx_dc[71:0] consists of 8 bits of data and 1 bit of control. Input Clock for single data rate (SDR) XGMII TX xgmii_tx_clk interface to the MAC.
Page 120: Xgmii Mapping To Standard Sdr Xgmii Data
UG-01080 5-11 XGMII Mapping to Standard SDR XGMII Data 2015.01.19 Signal Name Direction Description Output Disparity error signal indicating a 10-bit running led_disp_err disparity error. Asserted for one rx_clkout_1g cycle when a disparity error is detected. A running disparity error indicates that more than the previous and perhaps the current received group had an error.
Page 121: Serial Data Interface
UG-01080 5-12 Serial Data Interface 2015.01.19 Table 5-9: RX XGMII Mapping to Standard SDR XGMII Interface The 72-bit RX XGMII data bus format is different from the standard SDR XGMII interface. This table shows the mapping of this non-standard format to the standard SDR XGMII interface.
Page 122 UG-01080 5-13 1G/10GbE Control and Status Interfaces 2015.01.19 Signal Name Direction Description Output Asserted by the BER monitor block to indicate a rx_hi_ber Sync Header high bit error rate greater than 10 Output When asserted, indicates the TX PLL is locked.
Page 123: Register Interface Signals
UG-01080 5-14 Register Interface Signals 2015.01.19 Signal Name Direction Description Output When you enable 1588, this signal outputs the real rx_latency_adj_1g[21:0] time latency in GMII clock cycles (125 MHz) for the RX PCS and PMA datapath for 1G mode. Bits 0 to 9 represent fractional number of clock cycles.
Page 124: 1G/10Gbe Phy Register Definitions
UG-01080 5-15 1G/10GbE PHY Register Definitions 2015.01.19 Signal Name Direction Description Input Write signal. Active high. mgmt_write Input Read signal. Active high. mgmt_read Output When asserted, indicates that the Avalon-MM slave mgmt_waitrequest interface is unable to respond to a read or write request.
Page 125: Pma Registers
UG-01080 5-16 PMA Registers 2015.01.19 Addr Name Description 0xB1 When asserted, the sequencer is indicating that SEQ Link Ready the link is ready. Related Information Avalon Interface Specifications PMA Registers The PMA registers allow you to reset the PMA and provide status information.
Page 126: Pcs Registers
UG-01080 5-17 PCS Registers 2015.01.19 Table 5-15: PMA Registers - TX and RX Serial Data Interface The following PMA registers allow you to customize the TX and RX serial data interface Address Name Description When set to 1, the TX interface inverts the polarity of the tx_invpolarity TX data.
Page 127: 1G/10 Gbe Gmii Pcs Registers
UG-01080 5-18 1G/10 GbE GMII PCS Registers 2015.01.19 Addr Acce Name Description High BER status. When set to 1, the PCS is reporting a HI_BER high BER. When set to 0, the PCS is not reporting a high BER. Block lock status. When set to 1, the PCS is locked to BLOCK_LOCK received blocks.
Page 128 UG-01080 5-19 1G/10 GbE GMII PCS Registers 2015.01.19 Addr Name Description Full-duplex mode enable for the local device. Set to 1 for full-duplex support. Half-duplex mode enable for the local device. Set to 1 for half-duplex support. This bit should always be set to 0.
Page 129: Pma Registers
UG-01080 5-20 PMA Registers 2015.01.19 Addr Name Description Full-duplex mode enable for the link partner. This bit should always be 1 because only full duplex is supported. Half-duplex mode enable for the link partner. A value of 1 indicates support for half duplex. This bit should always be 0 because half-duplex mode is not supported.
Page 130: 1G/10Gbe Dynamic Reconfiguration From 1G To 10Gbe
1G and 10GbE operation on a channel-by-channel basis. In this figure, the colors have the following meanings: • Green-Altera- Cores available Quartus II IP Library, including the 1G/10Gb Ethernet MAC, the Reset Controller, and Transceiver Reconfiguration Controller. • Orange-Arbitration Logic Requirements Logic you must design, including the Arbiter and State Machine.
Page 131: 1G/10Gbe Phy Arbitration Logic Requirements
UG-01080 5-22 1G/10GbE PHY Arbitration Logic Requirements 2015.01.19 Figure 5-4: Block Diagram for Reconfiguration Example Backplane-KR or 1G/10Gb Ethernet PHY MegaCore Function Backplane-KR or 1G/10Gb Ethernet PHY MegaCore Function Backplane-KR or 1G/10Gb Ethernet PHY MegaCore Function Native PHY Hard IP 257.8...
Page 132: 1G/10Gbe Phy State Machine Logic Requirements
UG-01080 5-23 1G/10GbE PHY State Machine Logic Requirements 2015.01.19 • Channel number—specifies the requested channel • Mode—specifies 1G or 10G mode for the corresponding channel 2. Select a channel for reconfiguration and send an ack/busy signal to the requestor. The requestor should deassert its request signal when the ack/busy is received.
Page 133: Creating A 1G/10Gbe Design
UG-01080 5-24 Creating a 1G/10GbE Design 2015.01.19 Example 5-1: Edits to a MIF to Remove PMA Settings Creating a 1G/10GbE Design Here are the steps you must take to create a 1G/10GbE design using this PHY. 1. Generate the 1G/10GbE PHY with the required parameterization.
Page 134: Dynamic Reconfiguration Interface Signals
UG-01080 5-25 Dynamic Reconfiguration Interface Signals 2015.01.19 8. Generate a fractional PLL to create the 156.25 MHz XGMII clock from the 10G reference clock. 9. Instantiate the PHY in your design based on the required number of channels. 10.To complete the system, connect all the blocks.
Page 135 UG-01080 5-26 Dynamic Reconfiguration Interface Signals 2015.01.19 Signal Name Direction Description Output Specifies the TX equalization tap to update to tap_to_upd[2:0] optimize signal quality. The following encodings are defined: • 3'b100: main tap • 3'b010: post-tap • 3'b001: pre-tap Output When asserted, starts PCS reconfiguration.
Page 136: 10 Gbps Ethernet Phy Ip Core
Clause 37 of the IEEE 802.3 2005 Standard standard. The 10G PCS implements the 10 Gb Ethernet protocol as defined in IEEE 802.3 2005 Standard. You can switch dynamically between the 1G and 10G PCS using the Altera Transceiver Reconfiguration Controller IP Core to reprogram the core. This Ethernet core targets 1G/10GbE applications including network interfaces to 1G/10GbE dual speed SFP+ pluggable modules, 1G/10GbE 10GBASE-T copper external PHY devices to drive CAT-6/7 shielded twisted pair cables, and chip-to-chip interfaces.
Page 137 UG-01080 5-28 1G/10 Gbps Ethernet PHY IP Core 2015.01.19 Figure 5-5: Level Modules of the 1G/10GbE PHY MegaCore Function Altera Device with 10.3125+ Gbps Serial Transceivers 1G/10Gb Ethernet PHY MegaCore Function Native PHY Hard IP 257.8 1 Gb SFP /...
Page 138: Design Example
UG-01080 5-29 Design Example 2015.01.19 Design Example Figure 5-6: PHY-Only Design Example with Two Backplane Ethernet and Two Line-Side (1G/10G) Ethernet Channels NF_DE_WRAPPER Test Harness TH0_ADDR = 0xF nnn Management Master XGMII XGMII XGMII XGMII Test Harness TH1_ADDR = 0xE nnn...
Page 139: Simulation Support
UG-01080 5-30 Simulation Support 2015.01.19 Simulation Support The 1G/10GbE and 10GBASE-KR PHY IP core supports the following Altera-supported simulators for this Quartus II software release: • ModelSim Verilog • ModelSim VHDL • VCS Verilog • VCS VHDL Stratix V devices also support NCSIM Verilog and NCSIM VHDL simulation. When you generate a 1G/ ®...
Page 140 UG-01080 5-31 Acronyms 2015.01.19 Acronym Definition Physical Medium Attachment. Physical Medium Dependent. SGMII Serial Gigabit Media Independent Interface. Wide Area Network. XAUI 10 Gigabit Attachment Unit Interface. 1G/10 Gbps Ethernet PHY IP Core Altera Corporation Send Feedback...
Page 141: Xaui Phy Ip Core
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 142: Xaui Phy Release Information
XAUI PHY Device Family Support This section describes device family support for the IP core. IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: • Final support—Verified with final timing models for this device.
Page 143: Xaui Phy Performance And Resource Utilization For Stratix Iv Devices
UG-01080 XAUI PHY Performance and Resource Utilization for Stratix IV Devices 2015.01.19 Device Family Support Stratix IV GX and GT devices-Soft or hard PCS and Final Stratix V devices-Soft PCS + PMA Final Other device families No support DXAUI Stratix IV GX and GT...
Page 144: Xaui Phy General Parameters
Starting channel number 0-124 The physical starting channel number in the Altera device for channel 0 of this XAUI PHY. In Arria II GX, Cyclone IV GX, HardCopy IV, and Stratix IV devices, this starting channel number must be 0 or a multiple of 4.
Page 145 UG-01080 XAUI PHY General Parameters 2015.01.19 Name Value Description XAUI interface type Hard XAUI The following 3 interface types are available: Soft XAUI • Hard XAUI–Implements the PCS and PMA in hard logic. Available for Arria II, DDR XAUII Cyclone IV, HardCopy IV, and Stratix IV devices.
Page 146: Xaui Phy Analog Parameters
UG-01080 XAUI PHY Analog Parameters 2015.01.19 Example 6-1 shows how to remove the restriction on logical lane 0 channel assignment in Stratix V devices by redefining the pma_bonding_master parameter using the Quartus II Assignment Editor. In this example, the pma_bonding_master was originally assigned to physical channel 1. (The original assignment could also have been to physical channel 4.) The to parameter reassigns the...
Page 147 UG-01080 XAUI PHY Analog Parameters for Arria II GX, Cyclone IV GX, HardCopy IV and Stratix 2015.01.19 IV Devices Name Value Description Pre-emphasis pre-tap setting 0–7 Sets the amount of pre-emphasis on the TX buffer. Available for Stratix IV. Invert the pre-emphasis pre-tap...
Page 148: Advanced Options Parameters
UG-01080 Advanced Options Parameters 2015.01.19 Name Value Description Receiver static equalizer setting 0–15 This option sets the equalizer control settings. The equalizer uses a pass band filter. Specifying a low value passes low frequencies. Specifying a high value passes high frequencies. Available for HardCopy IV and Stratix IV devices.
Page 149: Xaui Phy Configurations
UG-01080 XAUI PHY Configurations 2015.01.19 XAUI PHY Configurations This section describes configurations of the IP core. The following figure illustrates one configuration of the XAUI IP Core. As this figure illustrates, if your variant includes a single instantiation of the XAUI IP Core, the transceiver reconfiguration control logic is included in the XAUI PHY IP Core.
Page 150: Xaui Phy Ports
UG-01080 6-10 XAUI PHY Ports 2015.01.19 XAUI PHY Ports This section describes the ports for the IP core. Figure 6-3 illustrates the top-level signals of the XAUI PHY IP Core for the hard IP implementation. This variant is available for Arria II GX, Cyclone IV GX, HardCopy IV and Stratix IV GX devices.Figure 6-4...
Page 151: Xaui Phy Data Interfaces
UG-01080 6-11 XAUI PHY Data Interfaces 2015.01.19 The following figure illustrates the top-level signals of the XAUI PHY IP Core for the soft IP implementa‐ tion for both the single and DDR rates. Figure 6-4: XAUI Top-Level Signals—Soft PCS and PMA...
Page 152: Sdr Xgmii Tx Interface
UG-01080 6-12 SDR XGMII TX Interface 2015.01.19 For the DDR XAUI variant, the start of control character (0xFB) is aligned to either byte 0 or byte 5. Figure 6-6: Byte 0 Start of Frame Transmission Example tx_clk txc[7:0] start FB...
Page 153: Sdr Xgmii Rx Interface
UG-01080 6-13 SDR XGMII RX Interface 2015.01.19 Table 6-7: SDR TX XGMII Interface Signal Name Direction Description Output Contains 4 lanes of data and control for XGMII. Each lane xgmii_tx_dc[71:0] consists of 16 bits of data and 2 bits of control.
Page 154 UG-01080 6-14 XAUI PHY Clocks, Reset, and Powerdown Interfaces 2015.01.19 Figure 6-8: Clock Inputs and Outputs for IP Core with Hard PCS phy_mgmt_clk XAUI Hard IP Core pll_ref_clk pll_inclk rx_cruclk Hard PCS xgmii_tx_clk tx_coreclk xgmii_rx_clk coreclkout 4 x 3.125 Gbps serial...
Page 155: Xaui Phy Pma Channel Controller Interface
UG-01080 6-15 XAUI PHY PMA Channel Controller Interface 2015.01.19 Signal Name Direction Description Input The XGMII TX clock which runs at 156.25 MHz. xgmii_tx_clk Connect xgmii_tx_clk to xgmii_rx_clk to guarantee this clock is within 150 ppm of the transceiver reference clock.
Page 156: Xaui Phy Optional Pma Control And Status Interface
UG-01080 6-16 XAUI PHY Optional PMA Control and Status Interface 2015.01.19 XAUI PHY Optional PMA Control and Status Interface You can access the state of the optional PMA control and status signals available in the soft IP implemen‐ tation using the Avalon-MM PHY Management interface to read the control and status registers which are detailed in XAUI PHY IP Core Registers .
Page 157 UG-01080 6-17 XAUI PHY Optional PMA Control and Status Interface 2015.01.19 neous value of a signal to ensure correct functioning of the XAUI PHY. In such cases, you can include the required signal in the top-level module of your XAUI PHY IP Core.
Page 158: Xaui Phy Register Interface And Register Descriptions
UG-01080 6-18 XAUI PHY Register Interface and Register Descriptions 2015.01.19 Name Direction Description Output Transceiver 8B/10B code group violation or disparity rx_errdetect[7:0] error indicator. If either signal is asserted, a code group violation or disparity error was detected on the associated received code group.
Page 159 UG-01080 6-19 XAUI PHY Register Interface and Register Descriptions 2015.01.19 Table 6-14: Avalon-MM PHY Management Interface Signal Name Direction Description Input Avalon-MM clock input. phy_mgmt_clk There is no frequency restriction for Stratix V devices; however, if you plan to use the same clock...
Page 160 UG-01080 6-20 XAUI PHY Register Interface and Register Descriptions 2015.01.19 Word Addr Bits Register Name Description 0x022 [31:0] Bit[P] indicates that the TX CMU PLL (P) is pma_tx_pll_is_locked locked to the input reference clock. There is typically one bit per pma_tx_pll_is_locked system.
Page 161 UG-01080 6-21 XAUI PHY Register Interface and Register Descriptions 2015.01.19 Word Addr Bits Register Name Description 0x061 [31:0] Writing a 1 to channel < > puts channel phy_serial_loopback < > in serial loopback mode. For informa‐ tion about pre- or post-CDR serial loopback modes, refer to Loopback Modes.
Page 162 UG-01080 6-22 XAUI PHY Register Interface and Register Descriptions 2015.01.19 Word Addr Bits Register Name Description [31:16] - Reserved [15:8] When asserted, indicates that the patterndetect[7:0] programmed word alignment pattern has been detected in the current word boundary. The RX pattern detect signal is 2 bits wide per channel or 8 bits per XAUI link.
Page 163 UG-01080 6-23 XAUI PHY Register Interface and Register Descriptions 2015.01.19 Word Addr Bits Register Name Description [31:8] Reserved [7:4] Indicates a RX phase compensation FIFO phase_comp_fifo_error[3:0] overflow or condition on the underrun corresponding lane. Reading the value of the register clears the phase_comp_fifo_error bits.
Page 164 0x08a Setting this bit to 1 shortens the duration of simulation_flag reset and loss timer when simulating. Altera recommends that you keep this bit set during simulation. For more information about the individual PCS blocks, refer to the Transceiver Architecture chapters of the appropriate device handbook.
Page 165: Xaui Phy Dynamic Reconfiguration For Arria Ii Gx, Cyclone Iv Gx, Hardcopy Iv Gx, And Stratix Iv Gx
UG-01080 6-25 XAUI PHY Dynamic Reconfiguration for Arria II GX, Cyclone IV GX, HardCopy IV GX, 2015.01.19 and Stratix IV GX Transceiver Architecture in Stratix V Devices • XAUI PHY Dynamic Reconfiguration for Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX The Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX use the ALTGX_RECONFIG Mega function for transceiver reconfiguration.
Page 166: Logical Lane Assignment Restriction
UG-01080 6-26 Logical Lane Assignment Restriction 2015.01.19 Example 6-2: Informational Messages for the Transceiver Reconfiguration Interface PHY IP will require 8 reconfiguration interfaces for connection to the external reconfiguration controller.Reconfiguration interface offsets 0-3 are connected to the transceiver channels.Reconfiguration interface offsets 4-7 are connected to the transmit PLLs.
Page 167: Sdc Timing Constraints
Refer to “Running a Simulation Testbench” for a description of the directories and files that the Quartus II software creates automatically when you generate your XAUI PHY IP Core. Refer to the Altera Wiki for an example testbench that you can use as a starting point in creating your own verification environment.
Page 168: Interlaken Phy Ip Core
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 169: Interlaken Phy Device Family Support
Interlaken PHY Device Family Support This section describes the Interlaken PHY device family support. IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: • Final support—Verified with final timing models for this device.
Page 170: Parameterizing The Interlaken Phy
UG-01080 Parameterizing the Interlaken PHY 2015.01.19 Parameterizing the Interlaken PHY The Interlaken PHY IP Core is available when you select the Arria V GZ or Stratix V devices. Complete the following steps to configure the Interlaken PHY IP Core in the MegaWizard Plug-In Manager: 1.
Page 171 Although 5 -8191 words are valid metaframe length values, the current Interlaken PHY IP Core implementation requires a minimum of 128 Metaframe length for good, stable performance. In simulation, Altera recommends that you use a smaller metaframe length to reduce simulation times. Input clock frequency Specifies the frequency of the input reference clock.
Page 172: Interlaken Phy Optional Port Parameters
UG-01080 Interlaken PHY Optional Port Parameters 2015.01.19 Parameter Value Description Base data rate This option allows you to specify a Base data rate to 1 × Lane rate minimize the number of PLLs required to generate 2 × Lane rate the clocks necessary for data transmission at different frequencies.
Page 173: Interlaken Phy Interfaces
UG-01080 Interlaken PHY Interfaces 2015.01.19 Click on the appropriate link to specify the analog options for your device: Related Information Analog Settings for Arria V GZ Devices • on page 19-11 Analog Settings for Stratix V Devices • on page 19-34 Interlaken PHY Interfaces This section describes the Interlaken PHY interfaces.
Page 174: Interlaken Phy Avalon-St Tx Interface
UG-01080 Interlaken PHY Avalon-ST TX Interface 2015.01.19 Interlaken PHY Avalon-ST TX Interface This section lists the signals in the Avalon-ST TX interface. Table 7-4: Avalon-ST TX Signals Signal Name Direction Description Input Avalon-ST data bus driven from the FPGA fabric to tx_parallel_data<n>[63:0]...
Page 175 UG-01080 Interlaken PHY Avalon-ST TX Interface 2015.01.19 Signal Name Direction Description Input When asserted, indicates that tx_parallel_data<n>[65] tx_parallel_data<n> is valid and is ready to be written into the TX [63:0] FIFO. When deasserted, indicates that tx_parallel_ is invalid and is not written into the data<n>[63:0]...
Page 176 67. The frequency range for is (data rate/40) - tx_coreclkin (data rate/67). For best results, Altera recommends that = (data rate/40). tx_coreclkin Output For single lane Interlaken links,...
Page 177: Interlaken Phy Avalon-St Rx Interface
The Interlaken MAC must wait for this signal to be asserted before initiating valid user data transfers on any lane. This output is synchronous to the clock domain. For consistent coreclkin tx_sync_ performance, Altera recommends using done frequency of lane (data coreclkin rx_coreclkin rate/40).
Page 178 UG-01080 7-11 Interlaken PHY Avalon-ST RX Interface 2015.01.19 Signal Name Direction Description Output When asserted, indicates that rx_parallel_data<n> rx_parallel_data<n>[63:0] valid. When deasserted, indicates the [64] rx_parallel_data<n> is invalid. This output is synchronous to the [63:0] clock domain. coreclkin The Interlaken PCS implements a gearbox between the PMA and PCS interface.
Page 179 UG-01080 7-12 Interlaken PHY Avalon-ST RX Interface 2015.01.19 Signal Name Direction Description Output When asserted, indicates an RX FIFO overflow error. rx_parallel_data<n> [67] Output When asserted, indicates that the RX FIFO is partially empty rx_parallel_data<n> and is still accepting data from the frame synchronizer. This...
Page 180 UG-01080 7-13 Interlaken PHY Avalon-ST RX Interface 2015.01.19 Signal Name Direction Description Output When asserted, indicates that the RX frame synchronization rx_parallel_data<n> state machine has found and received 4 consecutive, valid [70] synchronization words. The frame synchronization state machine requires 4 consecutive synchronization words to exit the presync state and enter the synchronized state.
Page 181: Interlaken Phy Tx And Rx Serial Interface
UG-01080 7-14 Interlaken PHY TX and RX Serial Interface 2015.01.19 Signal Name Direction Description Input When asserted, enables reading of data from the RX FIFO. This rx_dataout_bp<n> signal functions as a read enable. The RX interface has a ready latency of 1 cycle so that rx_paralleldata<n>[63:0]...
Page 182: Interlaken Optional Clocks For Deskew
When enabled, is available as input rx_coreclkin rx_coreclkin port which drives the read side of RX FIFO. Altera recommends using this clock to reduce clock skew. You should use a minimum frequency of lane data rate/ 67 to drive . Using a lower...
Page 183: Interlaken Phy Register Interface And Register Descriptions
UG-01080 7-16 Interlaken PHY Register Interface and Register Descriptions 2015.01.19 Interlaken PHY Register Interface and Register Descriptions This section describes the register interface and register descriptions. The Avalon-MM PHY management interface provides access to the Interlaken PCS and PMA registers, resets, error handling, and serial loopback controls.
Page 184 Interlaken PHY IP. Altera does not recommend use of a soft reset or the use of these reset register bits for Interlaken PHY IP. (write) Writing a 1 to bit 0 initiates a TX digital reset_control reset using the reset controller module.
Page 185 Interlaken PHY IP. Altera does not recommend use of a soft reset or the use of these reset register bits for Interlaken PHY IP. Writing a 1 causes the RX digital reset reset_rx_digital...
Page 186 UG-01080 7-19 Interlaken PHY Register Interface and Register Descriptions 2015.01.19 Word Addr Bits Register Name Description 0x065 [31:0] When set, programs the RX CDR PLL to pma_rx_set_locktoref lock to the reference clock. Bit < > corresponds to channel < >. By default, the Interlaken PHY IP configures the CDR PLL in Auto lock Mode.
Page 187: Why Transceiver Dynamic Reconfiguration
UG-01080 7-20 Why Transceiver Dynamic Reconfiguration 2015.01.19 Why Transceiver Dynamic Reconfiguration Dynamic reconfiguration is necessary to calibrate transceivers to compensate for variations due to PVT. As silicon progresses towards smaller process nodes, circuit performance is affected more by variations due to process, voltage, and temperature (PVT). These process variations result in analog voltages that can be offset from required ranges.
Page 188: Interlaken Phy Timequest Timing Constraints
Refer to “ Running a Simulation Testbench” for a description of the directories and files that the Quartus II software creates automatically when you generate your Interlaken PHY IP Core. Refer to the Altera Wiki for an example testbench that you can use as a starting point in creating your own verification environment.
Page 189: Phy Ip Core For Pci Express (Pipe)
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 190 UG-01080 PHY IP Core for PCI Express (PIPE) 2015.01.19 Figure 8-1: Gen3 PCI Express PHY (PIPE) with Hard IP PCS and PMA in Arria V GZ and Stratix V GX Devices Arria V GZ or Stratix V FPGA PHY IP Core for PCI Express - Gen3...
Page 191: Phy For Pcie (Pipe) Device Family Support
• Devices PHY for PCIe (PIPE) Device Family Support IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: • Final support—Verified with final timing models for this device. • Preliminary support—Verified with preliminary timing models for this device.
Page 192 UG-01080 PHY for PCIe (PIPE) General Options Parameters 2015.01.19 Table 8-2: PHY IP Core for PCI Express General Options Name Value Description Device family Supports all Arria V and Stratix V Stratix V devices. Arria V GZ Arria V GX...
Page 193 UG-01080 PHY for PCIe (PIPE) General Options Parameters 2015.01.19 Name Value Description Gen1 and Gen2 PLL type You can select either the CMU or ATX PLL. The CMU PLL has a larger frequency range than the ATX PLL. The ATX PLL is designed to improve jitter performance and achieves lower channel-to-channel skew;...
Page 194: Phy For Pcie (Pipe) Interfaces
UG-01080 PHY for PCIe (PIPE) Interfaces 2015.01.19 PHY Interface for the PCI Express Architecture PCI Express 3.0 • PHY for PCIe (PIPE) Interfaces This section describes interfaces of the PHY IP Core for PCI Express (PIPE). The following figure illustrates the top-level pinout of the PHY IP Core for PCI Express PHY. The port descriptions use the following variables to represent parameters: •...
Page 195: Phy For Pcie (Pipe) Input Data From The Phy Mac
UG-01080 PHY for PCIe (PIPE) Input Data from the PHY MAC 2015.01.19 For more information about _hw.tcl files, refer to refer to the Component Interface Tcl Reference chapter in volume 1 of the Quartus II Handbook. Related Information Component Interface Tcl Reference PHY for PCIe (PIPE) Input Data from the PHY MAC Input data signals are driven from the PHY MAC to the PCS.
Page 196 UG-01080 PHY for PCIe (PIPE) Input Data from the PHY MAC 2015.01.19 Signal Name Direction Description Input For Gen3, specifies start block byte location for TX tx_blk_start data in the 128-bit block data. Used when the interface between the PCS and PHY MAC is 32 bits.
Page 197 UG-01080 PHY for PCIe (PIPE) Input Data from the PHY MAC 2015.01.19 Signal Name Direction Description Input For Gen3, selects the transmitter de-emphasis. The pipe_g3_txdeemph[17:0] 18 bits specify the following coefficients: • [5:0]: C • [11:6]: C • [17:12]: C...
Page 198 UG-01080 8-10 PHY for PCIe (PIPE) Input Data from the PHY MAC 2015.01.19 Signal Name Direction Description Input When asserted high, the electrical idle state is rx_eidleinfersel[3<n>-1:0] inferred instead of being identified using analog circuitry to detect a device at the other end of the link.
Page 199: Phy For Pcie (Pipe) Output Data To The Phy Mac
UG-01080 8-11 PHY for PCIe (PIPE) Output Data to the PHY MAC 2015.01.19 PHY for PCIe (PIPE) Output Data to the PHY MAC This section describes the PIPE output signals. These signals are driven from the PCS to the PHY MAC.
Page 200 UG-01080 8-12 PHY for PCIe (PIPE) Output Data to the PHY MAC 2015.01.19 Signal Name Direction Description Output For Gen3, this signal is deasserted by the PHY to instruct pipe_rx_data_valid the MAC to ignore for one clock cycle. A pipe_rxdata value of 1 indicates the MAC should use the data.
Page 201: Phy For Pcie (Pipe) Clocks
UG-01080 8-13 PHY for PCIe (PIPE) Clocks 2015.01.19 PHY for PCIe (PIPE) Clocks This section describes the clock ports. Table 8-6: Clock Ports Signal Name Direction Description Input This is the 100 MHz input reference clock source for the pll_ref_clk PHY TX and RX PLL.
Page 202: Phy For Pcie (Pipe) Optional Status Interface
UG-01080 8-14 PHY for PCIe (PIPE) Optional Status Interface 2015.01.19 Add the following command to force Timequest analysis at 62.5 MHz. create_generated_clock -name clk_g1 -source [get_ports {pll_refclk}] \ -divide_by 8 -multiply_by 5 -duty_cycle 50 -phase 0 -offset 0 [get_nets {*pipe_nr_inst|transceiver_core|inst_sv_xcvr_native|inst_sv_pcs| \ ch[*].inst_sv_pcs_ch|inst_sv_hssi_tx_pld_pcs_interface|pld8gtxclkout}] -add...
Page 203: Phy For Pcie (Pipe) Register Interface And Register Descriptions
UG-01080 8-15 PHY for PCIe (PIPE) Register Interface and Register Descriptions 2015.01.19 Table 8-9: Transceiver Differential Serial Interface Signal Name Direction Description Input Receiver differential serial input data, < > is the rx_serial_data[<n>-1:0] number of lanes. Output Transmitter differential serial output data <...
Page 204 UG-01080 8-16 PHY for PCIe (PIPE) Register Interface and Register Descriptions 2015.01.19 Figure 8-5: PCI Express PIPE IP Core Top-Level Modules PHY IP Core for PCI Express and Avalon-MM Control Interface for Non-PIPE Functionality PHY IP Core for PCI Express...
Page 205 UG-01080 8-17 PHY for PCIe (PIPE) Register Interface and Register Descriptions 2015.01.19 Signal Name Direction Description Input Write signal. phy_mgmt_write Input Read signal. phy_mgmt_read Output When asserted, indicates that the Avalon-MM slave phy_mgmt_waitrequest interface is unable to respond to a read or write request.
Page 206 UG-01080 8-18 PHY for PCIe (PIPE) Register Interface and Register Descriptions 2015.01.19 Word Addr Bits Register Name Description [31:0] RW You can use the reset_fine_control reset_fine_control register to create your own reset sequence. The reset control module, illustrated in Transceiver PHY Top-Level Modules,...
Page 207 UG-01080 8-19 PHY for PCIe (PIPE) Register Interface and Register Descriptions 2015.01.19 Word Addr Bits Register Name Description 0x064 [31:0] RW When set, programs the RX CDR PLL to pma_rx_set_locktodata lock to the incoming data. Bit <n> corresponds to channel <n>.
Page 208 UG-01080 8-20 PHY for PCIe (PIPE) Register Interface and Register Descriptions 2015.01.19 Word Addr Bits Register Name Description [31:6] RW Reserved — [5:1] Sets the number of bits the TX block needs tx_bitslipboundary_select 0x083 to slip the output. Used for very latency sensitive protocols.
Page 209: Phy For Pcie (Pipe) Link Equalization For Gen3 Data Rate
UG-01080 8-21 PHY for PCIe (PIPE) Link Equalization for Gen3 Data Rate 2015.01.19 Word Addr Bits Register Name Description [31:20 Reserved — [19:16 When set, indicates a run length violation. rx_rlv From block: Word aligner. [15:12 When set, indicates that RX word aligner rx_patterndetect has achieved synchronization.
Page 210: Phase 0
Phase 2 tuning. The PIPE interface does not provide any measurement metric to the Root Port to guide coefficient preset decision making. The Root Port should reflect the existing coefficients and move to the next phase. The default Full Swing (FS) value advertized by Altera device is 40 and Low Frequency (LF) is 13.
Page 211: Phase 3 (Optional)
Recommendations for Tuning Link Partner’s Transmitter This section describes tuning link partner’s transmitter. To improve the BER of the StratixV receiver, Altera recommends that you turn on Adaptive Equalization (AEQ) one-time mode during Phase 2 Equalization for Endpoints or Phase 3 Equalization for Root Ports.
Page 212: Phy For Pcie (Pipe) Dynamic Reconfiguration
UG-01080 8-24 PHY for PCIe (PIPE) Dynamic Reconfiguration 2015.01.19 some instances you may want to override the specified four-stage link equalization procedure to dynamically tune PMA settings. Follow these steps to override Gen3 equalization: 1. Connect the Transceiver Reconfiguration Controller IP Core to your PHY IP Core for PCI Express as shown in PCI Express PIPE IP Core Top-Level Modules.
Page 213: Logical Lane Assignment Restriction
Refer to Running a Simulation Testbench for a description of the directories and files that the Quartus II software creates automatically when you generate your PHY IP Core for PCI Express. Refer to the Altera Wiki for an example testbench that you can use as a starting point in creating your own verification environment.
Page 214: Custom Phy Ip Core
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 215: Device Family Support
Transceiver Configurations in Stratix V Devices • Device Family Support IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: • Final support—Verified with final timing models for this device. • Preliminary support—Verified with preliminary timing models for this device.
Page 216: Parameterizing The Custom Phy
UG-01080 Parameterizing the Custom PHY 2015.01.19 Table 9-2: Custom PHY IP Core Performance and Resource Utilization—Stratix V GT Device Channels Combinational ALUTs Logic Registers (Bits) Parameterizing the Custom PHY Complete the following steps to configure the Custom PHY IP Core: 1.
Page 217 UG-01080 General Options Parameters 2015.01.19 Name Value Description Bonding mode Non-bonded or x1 Select Non-bonded or x1 to use separate clock sources for each channel. (This option is available for Bonded or xN Cyclone V and Arria V devices.) If one PLL drives fb_compensation multiple channels, PLL merging is required.
Page 218 UG-01080 General Options Parameters 2015.01.19 Name Value Description PCS-PMA interface width 8, 10, 16, 20 The PCS-PMA interface width depends on the FPGA fabric transceiver interface width and whether 8B/10B is enabled. The following combinations are available: FPGA/XCVR 8B/10B PMA Interface...
Page 219 UG-01080 General Options Parameters 2015.01.19 Name Value Description Base data rate The base data rate is the frequency of the clock input 1 × Data rate to the PLL. Select a base data rate that minimizes the 2 × Data rate number of PLLs required to generate all the clocks required for data transmission.
Page 220: Word Alignment Parameters
UG-01080 Word Alignment Parameters 2015.01.19 Name Value Description Enable embedded reset On/Off When On, the automatic reset controller initiates the control reset sequence for the transceiver. When Off you can design your own reset logic using tx_analogreset rx_analogreset tx_digitalreset rx_digital-...
Page 221 UG-01080 Word Alignment Parameters 2015.01.19 Table 9-5: Word Aligner Options Name Value Description Manual In this mode you enable the word alignment function by asserting rx_enapatternalign using the Avalon-MM interface. When the PCS exits reset, the word aligner automati‐ cally performs an initial alignment to the...
Page 222: Rate Match Fifo Parameters
UG-01080 Rate Match FIFO Parameters 2015.01.19 Name Value Description Enable run length violation On/Off If you turn this option on, you can specify the checking run length which is the maximum legal number of contiguous 0s or 1s. Run length...
Page 223: 8B/10B Encoder And Decoder Parameters
FIFO is capable of inserting or deleting the first two bytes (K28.5//D2.2) of /C2/ ordered sets during auto-negotiation. However, the insertion or deletion of the first two bytes of /C2/ ordered Altera Knowledge Base sets can cause the auto-negotiation link to fail. For more information, visit Support Solution.
Page 224: Byte Order Parameters
UG-01080 9-11 Byte Order Parameters 2015.01.19 Table 9-8: 8B/10B Options Name Value Description Enable 8B/10B decoder/encoder On/Off Enable this option if your application requires 8B/10B encoding and decoding. This option on adds the , and tx_datak <n> rx_datak <n> signals to your rx_runningdisp <n>...
Page 225 UG-01080 9-12 Byte Order Parameters 2015.01.19 Table 9-9: Byte Order Options Name Value Description Enable byte ordering block On/Off Turn this option on if your application uses serialization to create a datapath that is larger than 1 symbol. This option is only available if...
Page 226 UG-01080 9-13 Byte Order Parameters 2015.01.19 Name Value Description Enable byte ordering block On/Off Turn this option on to choose manual control manual control of byte ordering. This option creates the signal. A byte ordering operation enabyteord occurs whenever is asserted.
Page 227: Pll Reconfiguration Parameters
UG-01080 9-14 PLL Reconfiguration Parameters 2015.01.19 Name Value Description Byte ordering pad pattern 00000000 Specifies the pad pattern that is inserted to align the SOP. Enter the following size pad patterns: Data Width 8B/10B Pad Pattern Encoded? 8, 16, 32...
Page 228 UG-01080 9-15 PLL Reconfiguration Parameters 2015.01.19 Name Value Description Number of reference clocks Specifies the number of input reference clocks. More than one reference clock may be required if your design reconfigures channels to run at multiple frequencies. Main TX PLL logical index Specifies the index for the TX PLL that should be instantiated at startup.
Page 229: Analog Parameters
UG-01080 9-16 Analog Parameters 2015.01.19 Name Value Description Enable channel interface On/Off Turn this option on to enable PLL and datapath dynamic reconfiguration. When you select this option, the width of tx_parallel_ buses increases data rx_parallel_data in the following way.
Page 230 UG-01080 9-17 Presets for Ethernet 2015.01.19 Parameter Name GIGE-1.25 Gbps GIGE-2.50 Gbps PCS-PMA Interface Width Data rate 1250 Mbps 3125 Mbps Input clock frequency 62.5 MHz 62.5 MHz Enable TX Bitslip Create rx_coreclkin port Create tx_coreclkin port Create rx_recovered_clk port...
Page 231 UG-01080 9-18 Presets for Ethernet 2015.01.19 Parameter Name GIGE-1.25 Gbps GIGE-2.50 Gbps Enable 8B/10B decoder/encoder Enable manual disparity control Create optional 8B/10B status port Byte Order Options Enable byte ordering block Enable byte ordering block manual control Byte ordering pattern...
Page 232: Interfaces
UG-01080 9-19 Interfaces 2015.01.19 Interfaces Figure 9-2: Custom PHY Top-Level Signals The variables in Figure 9–2 represent the following parameters: • <n>—The number of lanes • <w>—The width of the FPGA fabric to transceiver interface per lane • <s>— The symbol size •...
Page 233 UG-01080 9-20 Data Interfaces 2015.01.19 Table 9-12: Avalon-ST TX Interface Signals Signal Name Direction Description Input This is TX parallel data driven from the MAC. The ready tx_parallel_data[(<n> latency on this interface is 0, so that the PHY must be able 43:0] to accept data as soon as it comes out of reset.
Page 234 UG-01080 9-21 Data Interfaces 2015.01.19 Table 9-13: Location of Valid Data Words for tx_parallel_data for Various FPGA Fabric to PCS Parameterizations The following table shows the valid 11-bit data words with and without the byte deserializer for single- and double-word FPGA fabric to PCS interface widths. The byte serializer allows the PCS to operate at twice the data width of the PMA .
Page 235 UG-01080 9-22 Data Interfaces 2015.01.19 Table 9-14: Avalon-ST RX Interface Signals These signals are driven from the PCS to the MAC. This is an Avalon source interface. Signal Name Direction Description Output This is RX parallel data driven from the Custom rx_parallel_data[<n>63:0]...
Page 236: Clock Interface
UG-01080 9-23 Clock Interface 2015.01.19 Signal Name Direction Description Output This is the clock for the RX parallel data source rx_clkout[< n >-1:0] interface. Output Data and control indicator for the source data. rx_datak[< n >(<w>/<s>)-1:0] When 0, indicates that...
Page 237: Optional Status Interface
UG-01080 9-24 Optional Status Interface 2015.01.19 Table 9-17: Clock Signals Signal Name Direction Description Input Reference clock for the PHY PLLs. Frequency pll_ref_clk range is 50-700 MHz. Input This is an optional clock to drive the coreclk of the rx_coreclkin[<n>-1:0] RX PCS.
Page 238 UG-01080 9-25 Optional Status Interface 2015.01.19 Signal Name Direction Signal Name Output When asserted, indicates that a rx_errdetect[<n>(<w>/<s>)-1:0] received 10-bit code group has an 8B/ 10B code violation or disparity error. Output Indicates presence or absence of rx_syncstatus[ <n> (<w>/<s>)- synchronization on the RX interface.
Page 239: Optional Reset Control And Status Interface
UG-01080 9-26 Optional Reset Control and Status Interface 2015.01.19 Signal Name Direction Signal Name Output When asserted, indicates that the RX rx_rmfifodatainserted[<n>-1:0] rate match block inserted an ||R|| column. Output When asserted, indicates that the RX rx_rmfifodatadeleted[<n>-1:0] rate match block deleted an ||R|| column.
Page 240: Register Interface And Register Descriptions
UG-01080 9-27 Register Interface and Register Descriptions 2015.01.19 Signal Name Direction Description Output When asserted, indicates that the initial TX tx_cal_busy[<n>-1:0] calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP.
Page 241 UG-01080 9-28 Register Interface and Register Descriptions 2015.01.19 Figure 9-4: Custom PHY IP Core Custom PHY IP Core Custom PHY PCS and PMA Transceiver Reconfiguration Controller Reconfig to and from Transceiver Clocks Clocks Tx Data Tx Parallel Data Rx Data Rx Parallel Data Rx Serial Data &...
Page 242: Custom Phy Ip Core Registers
UG-01080 9-29 Custom PHY IP Core Registers 2015.01.19 Signal Name Direction Description Output Output data. phy_mgmt_readdata[31:0] Input Write signal. phy_mgmt_write Input Read signal. phy_mgmt_read Output When asserted, indicates that the phy_mgmt_waitrequest Avalon-MM slave interface is unable to respond to a read or write request.
Page 243 UG-01080 9-30 Reset Controls –Manual Mode 2015.01.19 Word Bits Register Name Description Addr (write) Writing a 1 to bit 0 initiates a TX digital reset_control reset using the reset controller module. The reset affects channels enabled in the . Writing a 1 to bit 1...
Page 244 UG-01080 9-31 PMA Control and Status Registers 2015.01.19 Word Bits Register Name Description Addr Writing a 1 causes the internal RX analog reset_rx_analog reset signal to be asserted, resetting the RX analog logic of all channels enabled in . You must write a 0 to reset_ch_bitmask clear the reset condition.
Page 245 UG-01080 9-32 Custom PCS 2015.01.19 Custom PCS Table 9-25: Custom PCS Word Bits Register Name Description Addr 0x080 [31:0] Lane or group number Specifies lane or group number for indirect addressing, which is used for all PCS control and status registers. For variants that stripe data across multiple lanes, this is the logical group number.
Page 246: Sdc Timing Constraints
UG-01080 9-33 SDC Timing Constraints 2015.01.19 Word Bits Register Name Description Addr Every time this register transitions from 0 rx_bitslip to 1, the RX data slips a single bit. To block: Word aligner. When set, enables byte reversal on the RX rx_bytereversal_enable interface.
Page 247 UG-01080 9-34 Dynamic Reconfiguration 2015.01.19 Example 9-1: Informational Messages for the Transceiver Reconfiguration Interface PHY IP will require 2 reconfiguration interfaces for connection to the external reconfiguration controller. Reconfiguration interface offset 0 is connected to the transceiver channel. Reconfiguration interface offset 1 is connected to the transmit PLL.
Page 248: Low Latency Phy Ip Core
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 249: Device Family Support
• Final support—Verified with final timing models for this device. • Preliminary support—Verified with preliminary timing models for this device. The following table shows the level of support offered by the Low Latency PHY IP Core for Altera device families.
Page 250: Parameterizing The Low Latency Phy
UG-01080 10-3 Parameterizing the Low Latency PHY 2015.01.19 Implementa‐ Number of Serialization Worst-Case Combinational Dedicated Memory Bits tion Factor Frequency ALUTs Registers Lanes 6 Gbps (8 32 or 40 607.16 Gbps datapath) 6 Gbps (8 32 or 40 639.8 Gbps...
Page 251: General Options Parameters
UG-01080 10-4 General Options Parameters 2015.01.19 General Options Parameters • on page 10-4 • Additional Options Parameters on page 10-7 • PLL Reconfiguration Parameters on page 10-10 Low Latency PHY Analog Parameters • on page 10-12 5. Click Finish to generate your parameterized Low Latency PHY IP Core.
Page 252 UG-01080 10-5 General Options Parameters 2015.01.19 Name Value Description Bonding mode ×N Select ×N to use the same clock source for up to 6 channels in a single transceiver bank, fb_compensation resulting in reduced clock skew. You must use contiguous channels when you select ×N bonding.
Page 253 UG-01080 10-6 General Options Parameters 2015.01.19 Name Value Description Data rate Device Specifies the data rate in Mbps. Refer to dependent Stratix V Device Datasheet for the data rate ranges of datapath. Base data rate 1 × Data rate Select a base data rate that minimizes the number of PLLs required to generate all the 2 ×...
Page 254: Additional Options Parameters
UG-01080 10-7 Additional Options Parameters 2015.01.19 PCS-PMA Interface Width FPGA Fabric - Transceiver Interface tx_clkout and rx_clkout frequency 10G Datapath Standard Datapath Width — data rate/50 — data rate/32 — data rate/64 — data rate/66 Related Information Stratix V Device Datasheet •...
Page 255 UG-01080 10-8 Additional Options Parameters 2015.01.19 The following table describes the options available on the Additional Options tab: Table 10-5: Additional Options Name Value Description When you turn this option on, tx_coreclkin connects to the write clock of the TX phase...
Page 256 Another option is to use Altera’s Transceiver PHY Reset Controller IP Core to reset the transceivers. For more informa‐ tion, refer to the Transceiver PHY Reset Controller IP Corechapter. For more information about designing a reset...
Page 257: Pll Reconfiguration Parameters
UG-01080 10-10 PLL Reconfiguration Parameters 2015.01.19 Name Value Description Avalon data interfaces On/Off When you turn this option On, the order of symbols is changed. This option is typically required if you are planning to import your Low Latency Transceiver PHY IP Core into a Qsys system.
Page 258 UG-01080 10-11 PLL Reconfiguration Parameters 2015.01.19 Name Value Description Number of TX PLLs 1–4 Specifies the number of TX PLLs that can be used to dynamically reconfigure channels to run at multiple data rates. If your design does not require transceiver TX PLL dynamic reconfiguration, set this value to 1.
Page 259: Low Latency Phy Analog Parameters
UG-01080 10-12 Low Latency PHY Analog Parameters 2015.01.19 TX PLL (0–3) Low Latency PHY General Options for a detailed explanation of these parameters.) (Refer to Reference clock frequency Variable Specifies the frequency of the PLL input reference clock. The PLL must generate an output frequency that equals the Base data rate/2.
Page 260: Low Latency Phy Interfaces
UG-01080 10-13 Low Latency PHY Interfaces 2015.01.19 Related Information Analog Parameters Set Using QSF Assignments on page 19-1 Low Latency PHY Interfaces The following figure illustrates the top-level signals of the Custom PHY IP Core. The variables in this figure represent the following parameters: •...
Page 261 UG-01080 10-14 Low Latency PHY Data Interfaces 2015.01.19 Table 10-7: Avalon-ST interface Signal Name Direction Description Input This is TX parallel data driven from the tx_parallel_data[<n><w>-1:0] MAC FPGA fabric. The ready latency on this interface is 0, so that the PCS in Low-...
Page 262: Optional Status Interface
UG-01080 10-15 Optional Status Interface 2015.01.19 Optional Status Interface The following table describes the signals that comprise the optional status interface: Table 10-9: Optional Status Interface Signal Name Direction Description Output When asserted, indicates that the RX CDR is rx_is_lockedtodata[<n>-1:0] locked to incoming data.
Page 263: Optional Reset Control And Status Interface
UG-01080 10-16 Optional Reset Control and Status Interface 2015.01.19 Signal Name Direction Description Input Reference clock for the PHY PLLs. The pll_ref_clk frequency range is 60–700 MHz. Optional Reset Control and Status Interface The following table describes the signals in the optional reset control and status interface. These signals are available if you do not enable the embedded reset controller.
Page 264: Register Interface And Register Descriptions
UG-01080 10-17 Register Interface and Register Descriptions 2015.01.19 Register Interface and Register Descriptions The Avalon-MM PHY management interface provides access to the Low Latency PHY PCS and PMA registers that control the TX and RX channels, the PMA powerdown, PLL registers, and loopback modes.
Page 265 UG-01080 10-18 Register Interface and Register Descriptions 2015.01.19 Signal Name Direction Description Input Input data. phy_mgmt_writedata[31:0] Output Output data. phy_mgmt_readdata[31:0] Input Write signal. phy_mgmt_write Input Read signal. phy_mgmt_read For more information about the Avalon-MM and Avalon-ST protocols, including timing diagrams, refer...
Page 266: Dynamic Reconfiguration
UG-01080 10-19 Dynamic Reconfiguration 2015.01.19 Word Addr Bits Register Name Description Reset Control Registers–Automatic Reset Controller 0x063 [31:0] When channel <n> =1, indicates that receive pma_rx_signaldetect circuit for channel <n> senses the specified voltage exists at the RX input buffer.
Page 267: Sdc Timing Constraints
UG-01080 10-20 SDC Timing Constraints 2015.01.19 Controller IP Cores. Doing so causes a Fitter error. For more information, refer to Transceiver Reconfigu‐ ration Controller to PHY IP Connectivity. The following table describes the signals in the reconfiguration interface. This interface uses a clock provided by the reconfiguration controller.
Page 268: Simulation Files And Example Testbench
UG-01080 10-21 Simulation Files and Example Testbench 2015.01.19 Related Information SDC Timing Constraints of Stratix V Native PHY on page 12-74 This section describes SDC examples and approaches to identify false timing paths. Simulation Files and Example Testbench Refer to Running a Simulation Testbench for a description of the directories and files that the Quartus II software creates automatically when you generate your Low Latency PHY IP Core.
Page 269: Deterministic Latency Phy Ip Core
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 270: Deterministic Latency Auto-Negotiation
This is a standard, memory-mapped protocol that is normally used to read and write registers and memory. The transceiver reconfiguration interface connects to the Altera Transceiver Reconfiguration Controller IP Core which can dynamically reconfigure transceiver settings. Finally, the PMA transmits and receives serial data.
Page 271: Achieving Deterministic Latency
UG-01080 11-3 Achieving Deterministic Latency 2015.01.19 Base Data Rate (Mbps) Clock Divider Data Rate (Mbps) 2457.6 4915.2 3072.0 6144.0 4915.2 4915.2 6144.0 6144.0 Note: You can use PMA Direct mode in the Transceiver Native PHYs for CPRI applications that require higher frequencies.
Page 272: Deterministic Latency Phy Delay Estimation Logic
UG-01080 11-4 Deterministic Latency PHY Delay Estimation Logic 2015.01.19 Figure 11-2: Achieving Deterministic Latency for the TX and RX Datapaths The TX and RX Phase Compensation FIFOs always operate in register mode. Achieving Deterministic Latency for the TX & RX Datapaths...
Page 273 UG-01080 11-5 Deterministic Latency PHY Delay Estimation Logic 2015.01.19 Example 11-1: For RE RX _latency_ RE = <R X P CS latency in parallel clock cycles > + (<RX PMA latency in UI > + < rx_std_bitslipboundaryselect > delay ) TX_latency_RE = <TX PCS latency in parallel clock cycles>...
Page 274 UG-01080 11-6 Deterministic Latency PHY Delay Estimation Logic 2015.01.19 Example 11-4: Total Delay Uncertainty Round trip delay estimates are subject to process, voltage, and temperature (PVT) variation. = 2 × max (<t >, <t >) + µ t + µ t...
Page 275: Deterministic Latency Phy Device Family Support
Deterministic Latency PHY Device Family Support This section describes Deterministic Latency PHY IP core device support. IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: • Final support—Verified with final timing models for this device.
Page 276: Parameterizing The Deterministic Latency Phy
UG-01080 11-8 Parameterizing the Deterministic Latency PHY 2015.01.19 Parameterizing the Deterministic Latency PHY This section provides a list of steps on how to configure Deterministic Latency PHY 1. Under Tools > IP Catalog, select the device family of your choice.
Page 277 UG-01080 11-9 General Options Parameters for Deterministic Latency PHY 2015.01.19 Name Value Description Data rate Device Dependent If you select a data rate that is not supported by the configuration you have specified, the MegaWizard Table 11-7 displays a error message in the message pane.
Page 278: Additional Options Parameters For Deterministic Latency Phy
UG-01080 11-10 Additional Options Parameters for Deterministic Latency PHY 2015.01.19 Channel Width (FPGA-PCS Fabric) Serial Data Rate (Mbps) Single-Width Double-Width 8-Bit 16-Bit 16-Bit 32-Bit 1228.8 2457.6 3072 4915.2 6144 Additional Options Parameters for Deterministic Latency PHY This section describes the settings available on the Additional Options tab for the Deterministic Latency PHY IP core.
Page 279 K28.5 (0011111010) is always placed in the least significant byte (LSB) of a word with a fixed latency of 3 cycles. User logic can assume the LSB placement. Altera recommends the deterministic latency state machine mode for new Deterministic designs.
Page 280 UG-01080 11-12 Additional Options Parameters for Deterministic Latency PHY 2015.01.19 Name Value Description Word alignment mode Manual Manual–In this mode, the RX word aligner parses the incoming data stream for a specific alignment character. After it identifies this pattern, it shifts the...
Page 281: Pll Reconfiguration Parameters For Deterministic Latency Phy
UG-01080 11-13 PLL Reconfiguration Parameters for Deterministic Latency PHY 2015.01.19 Name Value Description Enable embedded reset On/ Off When you turn this option On, the embedded reset controller controller handles reset of the TX and RX channels at power up. If you turn this option Off, you must...
Page 282 UG-01080 11-14 PLL Reconfiguration Parameters for Deterministic Latency PHY 2015.01.19 Name Value Description Number of reference clocks Specifies the number of input reference clocks. More than one reference clock may be required if your design reconfigures channels to run at multiple frequencies.
Page 283: Deterministic Latency Phy Analog Parameters
UG-01080 11-15 Deterministic Latency PHY Analog Parameters 2015.01.19 Name Value Description Enable channel interface On/Off Turn this option on to enable PLL and datapath dynamic reconfiguration. When you select this option, the width of tx_parallel_data buses increases in the following...
Page 284: Data Interfaces For Deterministic Latency Phy
UG-01080 11-16 Data Interfaces for Deterministic Latency PHY 2015.01.19 Figure 11-3: Deterministic Latency PHY Top-Level Signals Deterministic PHY Top-Level Signals tx_parallel_data[< n>< w>-1>:0] tx_serial_data[< n>-1:0] High Speed Avalon-ST Tx tx_clkout[<n>-1:0] rx_serial_data[< n>-1:0] Serial I/O from MAC tx_datak[(<n>(<w>/<s>)-1:0] tx_ready rx_parallel_data[(< n>< w>)-1:0]...
Page 285 UG-01080 11-17 Data Interfaces for Deterministic Latency PHY 2015.01.19 Table 11-9: Avalon-ST TX Interface The following table describes the signals in the Avalon-ST input interface. These signals are driven from the MAC to the PCS. This is an Avalon sink interface.
Page 286 UG-01080 11-18 Data Interfaces for Deterministic Latency PHY 2015.01.19 Table 11-11: Avalon-ST RX Interface The following table describes the signals in the Avalon-ST output interface. These signals are driven from the PCS to the MAC. This is an Avalon source interface.
Page 287: Clock Interface For Deterministic Latency Phy
UG-01080 11-19 Clock Interface for Deterministic Latency PHY 2015.01.19 RX Data Word Description Word Aligner / synchronization status rx_parallel_data[10] Disparity error rx_parallel_data[11] Pattern detect rx_parallel_data[12] FIFO status. The following encodings are defined: rx_parallel_data[14:13] • 2’b00: Normal data • 2’b01: Deletion •...
Page 288: Optional Tx And Rx Status Interface For Deterministic Latency Phy
UG-01080 11-20 Optional TX and RX Status Interface for Deterministic Latency PHY 2015.01.19 Optional TX and RX Status Interface for Deterministic Latency PHY This section describes the optional TX and RX status interface settings for the Deterministic Latency PHY IP core.
Page 289: Optional Reset Control And Status Interfaces For Deterministic Latency Phy
UG-01080 11-21 Optional Reset Control and Status Interfaces for Deterministic Latency PHY 2015.01.19 Signal Name Direction Signal Name Output Asserted when the receiver CDR is locked to rx_is_lockedtoref [(<n>(<d>/<s>) the input reference clock. This signal is -1:0] asynchronous. This signal is optional.
Page 290: Register Interface And Descriptions For Deterministic Latency Phy
UG-01080 11-22 Register Interface and Descriptions for Deterministic Latency PHY 2015.01.19 Signal Name Direction Description Output When asserted, indicates that the rx_cal_busy [<n>-1:0] initial RX calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP.
Page 291 UG-01080 11-23 Register Interface and Descriptions for Deterministic Latency PHY 2015.01.19 Figure 11-4: Deterministic Latency PHY IP Core Deterministic PHY IP Core Deterministic PHY PCS and PMA Transceiver Reconfiguration Reconfig to and from Transceiver Controller Clocks Clocks Tx Data Tx Parallel Data...
Page 292 UG-01080 11-24 Register Interface and Descriptions for Deterministic Latency PHY 2015.01.19 Signal Name Direction Description Output When asserted, indicates that the Avalon-MM slave phy_mgmt_waitrequest interface is unable to respond to a read or write request. When asserted, control signals to the Avalon- MM slave interface must remain constant.
Page 293 UG-01080 11-25 Register Interface and Descriptions for Deterministic Latency PHY 2015.01.19 Word Addr Bits Register Name Description [31:0] You can use the reset_fine_control reset_fine_ register to create your own control reset sequence. In manual mode, only the TX reset occurs automati‐...
Page 294 UG-01080 11-26 Register Interface and Descriptions for Deterministic Latency PHY 2015.01.19 Word Addr Bits Register Name Description 0x067 [31:0] When asserted, indicates that the RX pma_rx_is_lockedtoref CDR PLL is locked to the reference clock. Bit < n> corresponds to channel < n>.
Page 295: Dynamic Reconfiguration For Deterministic Latency Phy
UG-01080 11-27 Dynamic Reconfiguration for Deterministic Latency PHY 2015.01.19 Word Addr Bits Register Name Description [31:4] Reserved. pcs8g_rx_wa_control Every time this register transitions rx_bitslip from 0 to 1, the RX data slips a single bit. To block: Word aligner. When set, enables byte reversal on rx_bytereversal_enable the RX interface.
Page 296: Channel Placement And Utilization For Deterministic Latency Phy
UG-01080 11-28 Channel Placement and Utilization for Deterministic Latency PHY 2015.01.19 Table 11-19: Reconfiguration Interface This table lists the signals in the reconfiguration interface. This interface uses the Avalon-MM PHY Management interface clock. Signal Name Direction Description Input Reconfiguration signals from the Transceiver reconfig_to_xcvr [(<n>70)-1:0]...
Page 297: Sdc Timing Constraints
UG-01080 11-29 SDC Timing Constraints 2015.01.19 Figure 11-5: Channel Placement and Available Channels in Arria V Devices Ch 5 Ch 5 Ch 4 Ch 4 5AGXB5KF40 Ch 3 Ch 3 GXB_L2 GXB_R2 5AGXB7KF40 Ch 2 Ch 2 Ch 1 Ch 1...
Page 298: Simulation Files And Example Testbench For Deterministic Latency Phy
UG-01080 11-30 Simulation Files and Example Testbench for Deterministic Latency PHY 2015.01.19 Related Information SDC Timing Constraints of Stratix V Native PHY on page 12-74 This section describes SDC examples and approaches to identify false timing paths. Simulation Files and Example Testbench for Deterministic Latency PHY This section describes simulation file requirements for the Deterministic Latency PHY IP core.
Page 299: Stratix V Transceiver Native Phy Ip Core
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 300: Device Family Support For Stratix V Native Phy
• Final support—Verified with final timing models for this device. • Preliminary support—Verified with preliminary timing models for this device. Table 12-1: Device Family Support This tables lists the level of support offered by the Stratix V Transceiver Native PHY IP Core for Altera device families. Device Family...
Page 301: Performance And Resource Utilization For Stratix V Native Phy
UG-01080 12-3 Performance and Resource Utilization for Stratix V Native PHY 2015.01.19 Performance and Resource Utilization for Stratix V Native PHY This section describes the performance resource utilization for Stratix V native PHY. Because the 10G PCS, Standard PCS, and PMA are implemented in hard logic, the Stratix V Native PHY IP Core uses less than 1% of the available ALMs, memory, primary and secondary logic registers.
Page 302: Parameterizing The Stratix V Native Phy
UG-01080 12-4 Parameterizing the Stratix V Native PHY 2015.01.19 Parameterizing the Stratix V Native PHY This section provides a list of instructions on how to configure the Stratix V Native PHY IP core Complete the following steps to configure the Stratix V Native PHY IP Core 1.
Page 303 UG-01080 12-5 General Parameters for Stratix V Native PHY 2015.01.19 Name Range Description Number of data channels Device Specifies the total number of data channels in each Dependent direction. From 1-32 channels are supported. Bonding mode Non-bonded or In Non-bonded or x1 mode, each channel is paired with a PLL.
Page 304: Pma Parameters For Stratix V Native Phy
UG-01080 12-6 PMA Parameters for Stratix V Native PHY 2015.01.19 PMA Parameters for Stratix V Native PHY This section describes the PMA parameters for the Stratix V native PHY. Table 12-3: PMA Options The following table describes the options available for the PMA. For more information about the PMA, refer to the PMA Architecture section in the Transceiver Architecture in Stratix V Devices.
Page 305 Stratix Native ext_pll_clk[<p> -1 : 0] PHY. Use the Stratix V Transceiver PLL IP Core to instantiate a CMU or ATX PLL. Use Altera Phase- Locked Loop (ALTERA_ PLL) Megafunction to instantiate a fractional PLL. Number of TX PLLs...
Page 306 UG-01080 12-8 PMA Parameters for Stratix V Native PHY 2015.01.19 Table 12-5: TX PLL Parameters The following table describes how you can define multiple TX PLLs for your Native PHY. The Native PHY GUI provides a separate tab for each TX PLL.
Page 307 UG-01080 12-9 PMA Parameters for Stratix V Native PHY 2015.01.19 RX CDR Options Table 12-6: RX PMA Parameters The following table describes the RX CDR options you can specify. For more information about the CDR circuitry, refer to the Receiver Clock Data Recovery Unit section in Clock Networks and PLLs in Stratix V Devices.
Page 308 UG-01080 12-10 PMA Parameters for Stratix V Native PHY 2015.01.19 PMA Optional Ports Table 12-7: RX PMA Parameters The following table describes the optional ports you can include in your IP Core. The QPI interface implements the Intel Quickpath Interconnect.
Page 309 UG-01080 12-11 PMA Parameters for Stratix V Native PHY 2015.01.19 Parameter Range Description Enable rx_clkslip port On/Off When you turn this option On, the rx_clkslip control input port is enabled. The deserializer slips one clock edge each time this signal is asserted. You...
Page 310 UG-01080 12-12 PMA Parameters for Stratix V Native PHY 2015.01.19 The following tables lists the bits used for all FPGA fabric to PMA interface widths. Regardless of the FPGA Fabric Interface Width selected, all 80 bits are exposed for the TX and RX parallel data ports.
Page 311: Standard Pcs Parameters For The Native Phy
UG-01080 12-13 Standard PCS Parameters for the Native PHY 2015.01.19 Standard PCS Parameters for the Native PHY This section shows the complete datapath and clocking for the Standard PCS and defines the parameters available in the GUI to enable or disable the individual blocks in the Standard PCS.
Page 312 • cpri select this mode if you intend to implement CPRI or another protocol that requires deterministic latency. Altera recommends that you select the appropriate CPRI preset for the CPRI protocol.
Page 313 UG-01080 12-15 Standard PCS Parameters for the Native PHY 2015.01.19 Phase Compensation FIFO The phase compensation FIFO assures clean data transfer to and from the FPGA fabric by compensating for the clock phase difference between the low-speed parallel clock and FPGA fabric interface clock. The following table describes the options for the phase compensation FIFO.
Page 314 UG-01080 12-16 Standard PCS Parameters for the Native PHY 2015.01.19 Parameter Range Description Enable RX byte ordering On/Off When you turn this option On, the PCS includes the byte ordering block. Byte ordering control mode Specifies the control mode for the byte manual ordering block.
Page 315 UG-01080 12-17 Standard PCS Parameters for the Native PHY 2015.01.19 Parameter Range Description Enable rx_std_byteorder_ena port On/Off Enables the optional rx_std_byte_order_ control input port. When this signal is asserted, the byte ordering block initiates a byte ordering operation if the Byte ordering control mode is set to manual.
Page 316 UG-01080 12-18 Standard PCS Parameters for the Native PHY 2015.01.19 Table 12-14: 8B/10B Encoder and Decoder Parameters Parameter Range Description Enable TX 8B/10B encoder On/Off When you turn this option On, the PCS includes the 8B/10B encoder. Enable TX 8B/10B disparity control...
Page 317 FIFO is capable of inserting or deleting the first two bytes (K28.5//D2.2) of /C2/ ordered sets during auto-negotiation. However, the insertion or deletion of the first two bytes of /C2/ ordered sets can cause the auto-negotiation link to fail. For more information, visit Altera Knowledge Base Support Solution.
Page 318 UG-01080 12-20 Standard PCS Parameters for the Native PHY 2015.01.19 Status Condition Protocol Mapping of Status Flags to RX Data Value PHY IP Core for PCI RXD[62:62] = rx_ (2'b10 AND (PAD Express (PIPE) , or rmfifostatus[1:0] OR EDB) = empty)
Page 319 UG-01080 12-21 Standard PCS Parameters for the Native PHY 2015.01.19 Status Condition Protocol Mapping of Status Flags to RX Data Value Basic double width RXD[62:62] = rx_ 2'b01 , or rmfifostatus[1:0] Serial RapidIO double width RXD[46:45] = rx_rmfifos- , or...
Page 320 UG-01080 12-22 Standard PCS Parameters for the Native PHY 2015.01.19 Parameter Range Description RX word aligner mode Specifies one of the following 3 modes for the bit_slip word aligner: sync_sm • Bit_slip : You can use bit slip mode to manual shift the word boundary.
Page 321 UG-01080 12-23 Standard PCS Parameters for the Native PHY 2015.01.19 Parameter Range Description Enable rx_std_wa_patternalign port On/Off Enables the optional rx_std_wa_patterna- control input port. A rising edge on this lign signal causes the word aligner to align the next incoming word alignment pattern when the word aligner is configured in manual mode.
Page 322 UG-01080 12-24 Standard PCS Parameters for the Native PHY 2015.01.19 Parameter Range Description Enable rx_std_bitrev_ena port On/Off When you turn this option On, asserting control port causes the RX std_bitrev_ena data order to be reversed from the normal order, LSB to MSB, to the opposite, MSB to LSB.
Page 323 UG-01080 12-25 Standard PCS Pattern Generators 2015.01.19 PRBS Verifier You can use the PRBS pattern generators for verification or diagnostics. The pattern generator blocks support the following patterns: • Pseudo-random binary sequence (PRBS) • Square wave Table 12-18: PRBS Parameters...
Page 324 UG-01080 12-26 Standard PCS Pattern Generators 2015.01.19 PCS-PMA Width 8-Bit 10-Bit 16-Bit 20-Bit PRBS-10 PRBS 15 PRBS 23 PRBS 31 Unlike the 10G PRBS verifier, the Standard PRBS verifier uses the Standard PCS word aligner. You must specify the word aligner size and pattern. The following table lists the encodings for the available choices.
Page 325 UG-01080 12-27 Standard PCS Pattern Generators 2015.01.19 PCS-PMA Width PRBS Patterns PRBS Pattern Select Word Aligner Size Word Aligner Pattern PRBS 7 3’b000 3’b100 0x0000043040 PRBS 23 3’b001 3’b110 0x00007FFFFF 20-bit PRBS 15 3’b101 3’b100 0x0000007FFF PRBS 31 3’b110 3’b110...
Page 326 UG-01080 12-28 Standard PCS Pattern Generators 2015.01.19 Offset OffsetBits Name Description 0xA3 [15:0] Stores the least significant 16 bits Word Aligner Pattern from the word aligner pattern as [15:0] specified in the previous table. 0xA4 [15] Disables the synchronization state Sync State Machine machine.
Page 327: 10G Pcs Parameters For Stratix V Native Phy
UG-01080 12-29 10G PCS Parameters for Stratix V Native PHY 2015.01.19 10G PCS Parameters for Stratix V Native PHY This section shows the complete datapath and clocking for the 10G PCS and defines parameters available in the GUI to enable or disable the individual blocks in the 10G PCS.
Page 328 UG-01080 12-30 10G PCS Parameters for Stratix V Native PHY 2015.01.19 Table 12-23: General and Datapath Parameters Parameter Range Description 10G PCS protocol mode Specifies the protocol that you intend to basic implement with the Native PHY. The interlaken protocol mode selected guides the...
Page 329 UG-01080 12-31 10G PCS Parameters for Stratix V Native PHY 2015.01.19 Table 12-24: 10G TX FIFO Parameters Parameter Range Description TX FIFO Mode Specifies one of the following 3 modes: Interlaken • interlaken : The TX FIFO acts as an phase_comp elastic buffer.
Page 330 UG-01080 12-32 10G PCS Parameters for Stratix V Native PHY 2015.01.19 Parameter Range Description Enable tx_10g_fifo_pfull port On/Off When you turn this option On , the 10G PCS includes the active high tx_10g_ fifo_pfull port tx_10g_fifo_pfull is synchronous to coreclk...
Page 331 UG-01080 12-33 10G PCS Parameters for Stratix V Native PHY 2015.01.19 Table 12-25: 10G RX FIFO Parameters Parameter Range Description RX FIFO Mode Specifies one of the following 3 modes: Interlaken • interlaken : Select this mode for the clk_comp Interlaken protocol.
Page 332 UG-01080 12-34 10G PCS Parameters for Stratix V Native PHY 2015.01.19 Parameter Range Description Enable RX FIFO control word deletion On/Off When you turn this option On , the (Interlaken) parameter enables or control_del disables writing the Interlaken control word to RX FIFO. When disabled, a...
Page 333 UG-01080 12-35 10G PCS Parameters for Stratix V Native PHY 2015.01.19 Parameter Range Description Enable rx_10g_fifo_rd_en port On/Off When you turn this option On, the 10G (Interlaken) PCS includes the rx_10g_fifo_rd_en input port. Asserting this signal reads a word from the RX FIFO. This signal is only available for the Interlaken protocol.
Page 334 UG-01080 12-36 10G PCS Parameters for Stratix V Native PHY 2015.01.19 Parameter Range Description teng_tx_framgen_burst_enable On/Off When you turn this option On, the frame generator burst functionality is enabled. Enable tx_10g_frame port On/Off When you turn this option On, the 10G...
Page 335 UG-01080 12-37 10G PCS Parameters for Stratix V Native PHY 2015.01.19 Table 12-27: Interlaken Frame Synchronizer Parameters Parameter Range Description teng_tx_framsync_enable On/Off When you turn this option On, the 10G PCS frame generator is enabled. Enable rx_10g_frame port On/Off When you turn this option On, the 10G...
Page 336 UG-01080 12-38 10G PCS Parameters for Stratix V Native PHY 2015.01.19 Parameter Range Description Enable rx_10g_frame_diag_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_diag_ output port. This signal is asserted to indicate a diagnostic control word error.
Page 337 UG-01080 12-39 10G PCS Parameters for Stratix V Native PHY 2015.01.19 Table 12-29: 10GBASE-R BER Checker Parameters Parameter Range Description Enable rx_10g_highber port On/Off When you turn this option On, the TX (10GBASE-R) 10G PCS datapath includes the rx_10g_ output port. This signal is highber asserted to indicate a BER of >10...
Page 338 UG-01080 12-40 10G PCS Parameters for Stratix V Native PHY 2015.01.19 Scrambler and Descrambler Parameters TX scrambler randomizes data to create transitions to create DC-balance and facilitate CDR circuits based on the x +1 polynomial. The scrambler operates in the following two modes: •...
Page 339 UG-01080 12-41 10G PCS Parameters for Stratix V Native PHY 2015.01.19 Block Synchronization The block synchronizer determines the block boundary of a 66-bit word for the 10GBASE-R protocol or a 67-bit word for the Interlaken protocol. The incoming data stream is slipped one bit at a time until a valid synchronization header (bits 65 and 66) is detected in the received data stream.
Page 340 UG-01080 12-42 10G PCS Pattern Generators 2015.01.19 Parameter Range Description Enable TX data bitslip On/Off When you turn this option On, the TX gearbox operates in bitslip mode. Enable RX data polarity inversion On/Off When you turn this option On, the...
Page 341 UG-01080 12-43 10G PCS Pattern Generators 2015.01.19 bits. The following table lists the offsets and registers of the pattern generators and verifiers Test Enable in the 10G PCS. Note: The 10G PRBS generator inverts its pattern before transmission. The 10G PRBS verifier inverts the received pattern before verification.
Page 342 UG-01080 12-44 10G PCS Pattern Generators 2015.01.19 Offset Bits Name Description [15:12] Specifies the number of consecutive 1s Square Wave Pattern and 0s. The following values are available: 1, 4, 5, 6, 8, and 10. [10] Enables the PRBS-7 polynomial in the TX PRBS 7 Enable transmitter.
Page 343 UG-01080 12-45 10G PCS Pattern Generators 2015.01.19 Offset Bits Name Description [14] Enables the PRBS-7 polynomial in the RX PRBS 7 Enable receiver. [13] Enables the PRBS-23 polynomial in the RX PRBS 23 Enable receiver. [12] Enables the PRBS-9 polynomial in the...
Page 344: Interfaces For Stratix V Native Phy
UG-01080 12-46 Interfaces for Stratix V Native PHY 2015.01.19 In addition you have the following options: • You can toggle the bit switch between two data patterns. Data Pattern Select • You can change the value of Seed A Seed B Unlike the PRBS pattern generator, the pseudo-random pattern generator does not require a configurable clock.
Page 345 UG-01080 12-47 Common Interface Ports for Stratix V Native PHY 2015.01.19 Figure 12-5: Stratix V Native PHY Common Interfaces Native PHY Common Interfaces ext_pll_clk[<p>-1:0] tx_serial_data[<n>-1:0] TX & RX tx_pll_refclk[< r>-1:0] rx_serial_data[<n>-1:0] Serial Ports Clock Input tx_pma_clkout[<n>-1:0] & Output Signals rx_pma_clkout[<n>-1:0] rx_cdr_refclk[<r>-1:0]...
Page 346 UG-01080 12-48 Common Interface Ports for Stratix V Native PHY 2015.01.19 Name Direction Description Input When asserted, resets the TX PLL. Active pll_powerdown[ <p> -1:0] high, edge sensitive reset signal. By default, the Stratix V Native Transceiver PHY IP Cores creates a separate pll_powerdown signal for each logical PLL.
Page 347 UG-01080 12-49 Common Interface Ports for Stratix V Native PHY 2015.01.19 Name Direction Description Input PCS TX parallel data. Used when you enable tx_parallel_data[ <n> 64-1:0] either the Standard or 10G datapath. For the Standard datapath, if you turn on Enable...
Page 348 UG-01080 12-50 Common Interface Ports for Stratix V Native PHY 2015.01.19 Name Direction Description Input Control input port for Quick Path Intercon‐ tx_pma_qpipullup nect (QPI) applications. When asserted, the transmitted pulls the output signal to high state. Use this port only for QPI applica‐...
Page 349 UG-01080 12-51 Common Interface Ports for Stratix V Native PHY 2015.01.19 Name Direction Description Input When asserted, programs the RX CDR to rx_set_locktoref[ <n> -1:0] manual lock to reference mode in which you control the reset sequence using the setlocktoref...
Page 350 UG-01080 12-52 Common Interface Ports for Stratix V Native PHY 2015.01.19 Table 12-39: Signal Definitions for tx_parallel_data with and without 8B/10B Encoding The following table shows the signals within that correspond to data, control, and status tx_parallel_data signals for a single 11-bit word. The...
Page 351: Standard Pcs Interface Ports
UG-01080 12-53 Standard PCS Interface Ports 2015.01.19 RX Data Word Description The following encodings are defined: rx_parallel_data[14:13] • 2’b00: Normal data • 2’b01: Deletion • 2’b10: Insertion (or Underflow with 9’h1FE or 9’h1F7) • 2’b11: Overflow Running disparity value rx_parallel_data[15]...
Page 352 UG-01080 12-54 Standard PCS Interface Ports 2015.01.19 Figure 12-6: Standard PCS Interfaces Standard PCS Interface Ports tx_std_clkout[<n>-1:0] Polarity rx_std_polinv[<n>-1:0] rx_std_clkout[<n>-1:0] Inversion tx_std_polinv[< n>-1:0] Clocks tx_std_coreclkin[<n>-1:0] rx_std_coreclkin[<n>-1:0] rx_std_rmfifo_empty[< n>-1:0] Rate rx_std_rmfifo_full[< n>-1:0] Match FIFO rx_std_bitrev_ena[<n>-1:0] tx_std_bitslipboundarysel[5<n>-1:0] rx_std_pcfifo_full[< n>-1:0] Phase rx_std_bitslipboundarysel[5< n>-1:0] rx_std_pcfifo_empty[<n>-1:0]...
Page 353 UG-01080 12-55 Standard PCS Interface Ports 2015.01.19 Name Synchronous to Description tx_std_coreclkin/ rx_std_coreclkin Output RX phase compensation FIFO status rx_std_pcfifo_empty[<n>- empty flag. 1:0] Output TX phase compensation FIFO status full tx_std_pcfifo_full[<n>- flag. 1:0] Output TX phase compensation FIFO status tx_std_pcfifo_empty[<n>- empty flag.
Page 354 UG-01080 12-56 Standard PCS Interface Ports 2015.01.19 Name Synchronous to Description tx_std_coreclkin/ rx_std_coreclkin Input Polarity inversion for the 8B/10B decoder, rx_std_polinv[<n>-1:0] When set, the RX channels invert the polarity of the received data. You can use this signal to correct the polarity of...
Page 355 UG-01080 12-57 Standard PCS Interface Ports 2015.01.19 Name Synchronous to Description tx_std_coreclkin/ rx_std_coreclkin Output This signal operates when the word aligner rx_std_bitslipboun- is in bitslip word alignment mode. It darysel[5<n>-1:0] reports the number of bits that the RX block slipped to achieve deterministic latency.
Page 356: 10G Pcs Interface
UG-01080 12-58 10G PCS Interface 2015.01.19 Name Synchronous to Description tx_std_coreclkin/ rx_std_coreclkin Output When asserted, indicates an error only rx_std_prbs_err after the signal has rx_std_prbs_done been asserted. This signal pulses for every error that occurs. Errors can only occur once per word.
Page 357 UG-01080 12-59 10G PCS Interface 2015.01.19 Figure 12-7: Stratix V Native PHY 10G PCS Interfaces 10G PCS Interface Ports tx_10g_coreclkin[<n>-1:0] tx_10g_diag_status[2<n>-1:0] Frame rx_10g_coreclkin[<n>-1:0] tx_10g_burst_en[<n>-1:0] Generator Clocks tx_10g_clkout[<n>-1:0] tx_10g_frame[<n>-1:0] rx_10g_clkout[<n>-1:0] rx_10g_clk33out[<n>-1:0]t rx_10g_frame[<n>-1:0] rx_10g_frame_lock[<n>-1:0] tx_10g_control[8<n>-1:0] rx_10g_pyld_ins[<n>-1:0] tx_10g_data_valid[<n>-1:0] rx_10g_frame_mfrm_err[< n>-1:0] tx_10g_fifo_full[< n>-1:0] rx_10g_frame_sync_err[<n>-1:0] Frame tx_10g_fifo_pfull[<...
Page 358 UG-01080 12-60 10G PCS Interface 2015.01.19 Name Direction Description Output TX parallel clock output for the TX PCS. tx_10g_clkout [<n>-1:0] Output RX parallel clock output which is recovered from the RX rx_10g_clkout data stream. [<n>-1:0] Output This clock is driven by the RX deserializer. Its frequency...
Page 359 UG-01080 12-61 10G PCS Interface 2015.01.19 Name Direction Description • [2]: Inversion signal, must always be set to 1'b0. • [1]: Sync Header, 1 indicates a control word • [0]: Sync Header, 1 indicates a data word 10G BaseR mode: •...
Page 360 UG-01080 12-62 10G PCS Interface 2015.01.19 Name Direction Description Output When asserted, indicates that the TX FIFO is partially tx_10g_fifo_pfull full. Synchronous to tx_10g_coreclkin [<n>-1:0] Output TX FIFO empty flag. Synchronous to tx_10g_clkout tx_10g_fifo_empty This signal is pulse-stretched; you must use a synchron‐...
Page 361 UG-01080 12-63 10G PCS Interface 2015.01.19 Name Direction Description RX control signals for the Interlaken, 10GBASE-R, and Basic protocols. These are synchronous to . The rx_10g_coreclkin following signals are defined: Interlaken mode: • [9]: Active-high synchronous status signal that indicates when block lock and frame lock are achieved •...
Page 362 UG-01080 12-64 10G PCS Interface 2015.01.19 Name Direction Description Basic mode: 67-bit mode with Block Sync: • [9]: Active-high synchronous status signal that indicates when Block Lock is achieved. • [8]: Active-high synchronous status signal that indicates a sync header error •...
Page 363 UG-01080 12-65 10G PCS Interface 2015.01.19 Name Direction Description Output Active high RX FIFO full flag. Synchronous to rx_10g_ rx_10g_fifo_full . This signal is pulse-stretched; you must use a clkout [<n>-1:0] synchronizer. Output RX FIFO partially full flag. Synchronous to...
Page 364 UG-01080 12-66 10G PCS Interface 2015.01.19 Name Direction Description Input For the Interlaken protocol, provides diagnostic status tx_10g_diag_status information reflecting the lane status message contained [2<n>-1:0] in the Framing Layer Diagnostic Word (bits[33:32]). This message is inserted into the next Diagnostic Word generated by the Frame Generation Block.
Page 365 UG-01080 12-67 10G PCS Interface 2015.01.19 Name Direction Description Output For the Interlaken protocol, asserted to indicate a rx_10g_frame_sync_err synchronization Control Word error was received in a [<n>-1:0] synchronization Control Word location within the metaframe. This signal is sticky if block lock is lost and does not update until block lock is re-established.This signal is...
Page 366 UG-01080 12-68 10G PCS Interface 2015.01.19 Name Direction Description Output Active-high status signal that is asserted when block rx_10g_blk_lock synchronizer acquires block lock. Valid for the [<n>-1:0] 10GBASE-R and Interlaken protocols, and any basic mode that uses the lock state machine to achieve and monitor block synchronization for word alignment.
Page 367: 6/×N Bonded Clocking
UG-01080 12-69 ×6/×N Bonded Clocking 2015.01.19 Name Direction Description Output When asserted, indicates an error only after the rx_10g_prbs_err rx_10g_ signal has been asserted. This signal pulses for prbs_done every error that occurs. An error can only occur once per word.
Page 368 UG-01080 12-70 ×6/×N Bonded Clocking 2015.01.19 Figure 12-8: x6 and xN Routing of Clocks ×N_top Clock Line (1) Transceiver Bank Local Clock Divider Central Clock Divider Local Clock Divider Local Clock Divider Central Clock Divider Local Clock Divider ×6 Clock Lines (1)
Page 369 UG-01080 12-71 ×6/×N Bonded Clocking 2015.01.19 Bonded clocks allow you to use the same PLL for up to 13 contiguous channels above and below the TX PLL for a total of 27 bonded channels as the following figure illustrates. Stratix V Transceiver Native PHY IP Core...
Page 370 UG-01080 12-72 ×6/×N Bonded Clocking 2015.01.19 Figure 12-9: Channel Span for xN Bonded Channels Transceiver Bank 4 Transceiver Bank 3 Transceiver Bank 2 Up to 7 Up to 13 channels channels above & above & Stratix V Transceiver Native PHY IP Core...
Page 371: Xn Non-Bonded Clocking
ATX, CMU and Fractional PLLs For data rates above 8 Gbps, Altera recommends the ATX PLL because it has better jitter performance. Refer to "Clock Network Maximum Data Rate Transmitter Specifications" in the Stratix V Device Datasheet for detailed information about maximum data rates for the three different PLLs. The supported data rates are somewhat higher when a design specifies up to 7 contiguous channels above and below the ATX PLL rather than the maximum of 13 contiguous channels above and below the ATX PLL.
Page 372: Sdc Timing Constraints Of Stratix V Native Phy
UG-01080 12-74 SDC Timing Constraints of Stratix V Native PHY 2015.01.19 SDC Timing Constraints of Stratix V Native PHY This section describes SDC examples and approaches to identify false timing paths. The Quartus II software reports timing violations for asynchronous inputs to the Standard PCS and 10G PCS.
Page 373: Dynamic Reconfiguration For Stratix V Native Phy
UG-01080 12-75 Dynamic Reconfiguration for Stratix V Native PHY 2015.01.19 Example 12-2: Using the max_delay Constraint to Identify Asynchronous Inputs You can use the set_max_delay constraint on a given path to create a constraint for asynchronous signals that do not have a specific clock relationship but require a maximum path delay. The following example illustrates this approach.
Page 374: Simulation Support
UG-01080 12-76 Simulation Support 2015.01.19 Example 12-5: Overriding Logical Channel 0 Channel Assignment Restrictions in Stratix V Device for ×6 or ×N Bonding If you are using ×6 or ×N bonding, transceiver dynamic reconfiguration requires that you assign the starting channel number. Logical channel 0 should be assigned to either physical transceiver channel 1 or channel 4 of a transceiver bank.
Page 375 UG-01080 12-77 Slew Rate Settings 2015.01.19 • Protocol declarations take priority over datarate. For example, XAUI has a per-lane datarate of 3.125 Gbps, but only a setting of "3" is allowed. A setting of "4" is not allowed for XAUI.
Page 376: Arria V Transceiver Native Phy Ip Core
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 377: Device Family Support
PLL connectivity, and the channel configurations at runtime. Device Family Support IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: • Final support—Verified with final timing models for this device.
Page 378: Performance And Resource Utilization
UG-01080 13-3 Performance and Resource Utilization 2015.01.19 Performance and Resource Utilization This section describes performance and resource utilization for the IP core. Because the Standard PCS and PMA are implemented in hard logic, the Arria V Native PHY IP Core requires minimal resources.
Page 379: Pma Parameters
UG-01080 13-4 PMA Parameters 2015.01.19 Name Range Description Number of data channels 1-36 Specifies the total number of data channels in each direction. Bonding mode Bonded or xN In Non–bonded mode, each channel is assigned a PLL. Non-bonded If one PLL drives multiple channels, PLL merging is or x1 required.
Page 380: Tx Pma Parameters
UG-01080 13-5 TX PMA Parameters 2015.01.19 Table 13-3: PMA Options Parameter Range Description Data rate Device Dependent Specifies the data rate. The maximum data rate is 12.5 Gbps. PMA direct interface width 8.10,16,20,64,80 Specifies the PMA to FPGA (12) fabric interface width for PMA Direct mode.
Page 381: Tx Pll Parameters
Arria V Native PHY. pll_clk[<p> -1 : 0] Use the Arria V Transceiver PLL IP Core to instantiate a CMU PLL. Use Altera Phase-Locked Loop (ALTERA_ PLL) Megafunction to instantiate a fractional PLL. Number of TX PLLs 1–4...
Page 382 UG-01080 13-7 TX PLL Parameters 2015.01.19 Table 13-5: TX PLL Parameters Parameter Range Description PLL type This is the only PLL type available. PLL base data rate Device Shows the base data rate of the clock input to the Dependent TX PLL.The PLL base data rate is computed...
Page 383: Rx Pma Parameters
UG-01080 13-8 RX PMA Parameters 2015.01.19 RX PMA Parameters Note: For more information about the CDR circuitry, refer to the Receiver PMA Datapath section in the Transceiver Architecture in Arria V Devices . Table 13-6: RX PMA Parameters Parameter Range...
Page 384 UG-01080 13-9 RX PMA Parameters 2015.01.19 The following table lists the best case latency for the most significant bit of a word for the RX deserializer for the PMA Direct datapath. PMA Direct mode is supported for Arria V GT, ST, and GZ devices only.
Page 385: Standard Pcs Parameters
UG-01080 13-10 Standard PCS Parameters 2015.01.19 FPGA Fabric Interface Width Bus Bits Used 10 bits [9:0] 16 bits {[17:10], [7:0]} 20 bits [19:0] 40 bits [39:0] 64 bits {[77:70], [67:60], [57:50], [47:40], [37:30], [27:20], [17:10], [7:0]} 80 bits [79:0] Related Information...
Page 386 • cpri–select this mode if you intend to implement CPRI or another protocol that requires deterministic latency. Altera recommends that you select the appropriate CPRI preset for the CPRI protocol. • gige–select this mode if you intend to implement either the 1.25 Gbps or 2.5 Gbps Ethernet protocol.
Page 387: Phase Compensation Fifo
UG-01080 13-12 Phase Compensation FIFO 2015.01.19 Phase Compensation FIFO The phase compensation FIFO assures clean data transfer to and from the FPGA fabric by compensating for the clock phase difference between the lowspeed parallel clock and FPGA fabric interface clock.
Page 388: Byte Ordering Block Parameters
UG-01080 13-13 Byte Ordering Block Parameters 2015.01.19 Parameter Range Description Enable rx_std_rmfifo_ On/Off When you turn this option On, the rate match FIFO full port outputs a FIFO full status flag. Related Information Transceiver Architecture in Arria V Devices Byte Ordering Block Parameters This section describes the byte ordering block parameters.
Page 389: Byte Serializer And Deserializer
UG-01080 13-14 Byte Serializer and Deserializer 2015.01.19 Parameter Range Description Byte order pattern User-specified 8- Specifies the search pattern for the byte ordering block. (hex) 10 bit pattern Byte order pad User–specified 8- Specifies the pad pattern that is inserted by the byte ordering...
Page 390: 8B/10B
UG-01080 13-15 8B/10B 2015.01.19 Table 13-13: Byte Serializer and Deserializer Parameters Parameter Range Description Enable TX byte serializer On/Off When you turn this option On, the PCS includes a TX byte serializer which allows the PCS to run at a lower clock frequency to accommodate a wider range of FPGA interface widths.
Page 391 FIFO is capable of inserting or deleting the first two bytes (K28.5//D2.2) of /C2/ ordered sets during auto-negotiation. However, the insertion or deletion of the first two bytes of /C2/ ordered Altera Knowledge Base sets can cause the auto-negotiation link to fail. For more information, visit Support Solution.
Page 392 UG-01080 13-17 Rate Match FIFO 2015.01.19 Table 13-16: Status Flag Mappings for Simplified Native PHY Interface Status Condition Protocol Mapping of Status Flags to RX Data Value PHY IP Core for PCI RXD[62:62] = rx_ 2'b11 = full Express (PIPE)
Page 393: Word Aligner And Bitslip Parameters
UG-01080 13-18 Word Aligner and BitSlip Parameters 2015.01.19 Status Condition Protocol Mapping of Status Flags to RX Data Value Basic double width RXD[62:62] = rx_ 2'b10 , or rmfifostatus[1:0] Serial RapidIO double width RXD[46:45] = rx_rmfifos- , or tatus[1:0] RXD[30:29] = rx_...
Page 394 UG-01080 13-19 Word Aligner and BitSlip Parameters 2015.01.19 Table 13-17: Word Aligner and BitSlip Parameters Parameter Range Description Enable TX bit slip On/Off When you turn this option On, the PCS includes the bitslip function. The outgoing TX data can be slipped by the number of bits...
Page 395: Bit Reversal And Polarity Inversion
UG-01080 13-20 Bit Reversal and Polarity Inversion 2015.01.19 Parameter Range Description Number of invalid words to lose Specifies the number of invalid data codes or 1–256 sync disparity errors that must be received before the word aligner loses synchronization. The default is 3.
Page 396 UG-01080 13-21 Bit Reversal and Polarity Inversion 2015.01.19 Table 13-18: Bit Reversal and Polarity Inversion Parameters Parameter Range Description Enable TX bit reversal On/Off When you turn this option On, the word aligner reverses TX parallel data before transmitting it to the PMA for serialization.
Page 397 UG-01080 13-22 Bit Reversal and Polarity Inversion 2015.01.19 Parameter Range Description Enable tx_std_polinv port On/Off When you turn this option On, the input is enabled. You can std_polinv use this control port to swap the positive and negative signals of a serial...
Page 398: Interfaces
UG-01080 13-23 Interfaces 2015.01.19 Interfaces The Native PHY includes several interfaces that are common to all parameterizations. The Native PHY allows you to enable ports, even for disabled blocks to facilitate dynamic reconfiguration. The Native PHY uses the following prefixes for port names: •...
Page 399 UG-01080 13-24 Common Interface Ports 2015.01.19 Table 13-19: Native PHY Common Interfaces Name Direction Description Clock Inputs and Output Signals Input The reference clock input to the TX PLL. tx_pll_refclk[<r>-1:0] Output TX parallel clock output from PMA. tx_pma_clkout[<n>-1:0] This clock is only available in PMA direct mode.
Page 400 UG-01080 13-25 Common Interface Ports 2015.01.19 Name Direction Description Input When asserted, resets for TX PMA, TX tx_analogreset[<n>-1:0] clock generation block, and serializer. Active high, edge sensitive reset signal. Note: For Arria V devices, while compiling a multi-channel transceiver design, you will...
Page 401 UG-01080 13-26 Common Interface Ports 2015.01.19 Name Direction Description Input PCS TX parallel data representing 4, 11- tx_parallel_data[43:0] bit words. Used when you enable the Standard datapath. Refer to Table 13-20for bit definitions. Refer to Table 13-21 various parameterizations. Output...
Page 402 UG-01080 13-27 Common Interface Ports 2015.01.19 Name Direction Description Output When asserted, the CDR is locked to the rx_is_lockedtoref[<n>-1:0] incoming reference clock. When you turn this signal on, the Input rx_clkslip[<n>-1:0] deserializer performs a clock slip operation to achieve word alignment.
Page 403 UG-01080 13-28 Common Interface Ports 2015.01.19 TX Data Word Description Force disparity, validates disparity field. tx_parallel_data[9] Specifies the current disparity as follows: tx_parallel_data[10] • 1'b0 = positive • 1'b1 = negative Signal Definitions with 8B/10B Disabled TX data bus tx_parallel_data[9:0]...
Page 404: Standard Pcs Interface Ports
UG-01080 13-29 Standard PCS Interface Ports 2015.01.19 RX Data Word Description Word alignment / synchronization status rx_parallel_data[10] Disparity error rx_parallel_data[11] Pattern detect rx_parallel_data[12] The following encodings are defined: rx_parallel_data[14:13] • 2’b00: Normal data • 2’b01: Deletion • 2’b10: Insertion (or Underflow with 9’h1FE or 9’h1F7)
Page 405 UG-01080 13-30 Standard PCS Interface Ports 2015.01.19 Figure 13-4: Standard PCS Interfaces Standard PCS Interface Ports tx_std_clkout[<n>-1:0] Polarity rx_std_polinv[<n>-1:0] rx_std_clkout[<n>-1:0] Inversion tx_std_polinv[< n>-1:0] Clocks tx_std_coreclkin[<n>-1:0] rx_std_coreclkin[<n>-1:0] rx_std_rmfifo_empty[< n>-1:0] Rate rx_std_rmfifo_full[< n>-1:0] Match FIFO rx_std_bitrev_ena[<n>-1:0] tx_std_bitslipboundarysel[5<n>-1:0] rx_std_pcfifo_full[< n>-1:0] Phase rx_std_bitslipboundarysel[5< n>-1:0] rx_std_pcfifo_empty[<n>-1:0]...
Page 406 UG-01080 13-31 Standard PCS Interface Ports 2015.01.19 Name Synchronous to Description tx_std_coreclkin/ rx_std_coreclkin Output RX phase compensation FIFO status rx_std_pcfifo_empty[<n>- empty flag. 1:0] Output TX phase compensation FIFO status full tx_std_pcfifo_full[<n>- flag. 1:0] Output TX phase compensation FIFO status tx_std_pcfifo_empty[<n>- empty flag.
Page 407 UG-01080 13-32 Standard PCS Interface Ports 2015.01.19 Name Synchronous to Description tx_std_coreclkin/ rx_std_coreclkin Input Polarity inversion for the 8B/10B decoder, rx_std_polinv[<n>-1:0] When set, the RX channels invert the polarity of the received data. You can use this signal to correct the polarity of...
Page 408 UG-01080 13-33 Standard PCS Interface Ports 2015.01.19 Name Synchronous to Description tx_std_coreclkin/ rx_std_coreclkin Output This signal operates when the word aligner rx_std_bitslipboun- is in bitslip word alignment mode. It darysel[5<n>-1:0] reports the number of bits that the RX block slipped to achieve deterministic latency.
Page 409: Sdc Timing Constraints
UG-01080 13-34 SDC Timing Constraints 2015.01.19 Name Synchronous to Description tx_std_coreclkin/ rx_std_coreclkin Output When asserted, indicates an error only rx_std_prbs_err after the signal has rx_std_prbs_done been asserted. This signal pulses for every error that occurs. Errors can only occur once per word.
Page 410: Dynamic Reconfiguration
UG-01080 13-35 Dynamic Reconfiguration 2015.01.19 Example 13-1: Using the set_false_path Constraint to Identify Asynchronous Inputs set_false_path -through {*8gbitslip*} -to [get_registers *8g_rx_pcs*SYNC_DATA_REG*] set_false_path -through {*8gbytordpld*} -to [get_registers *8g_rx_pcs*SYNC_DATA_REG*] set_false_path -through {*8gcmpfifoburst*} -to [get_registers *8g_rx_pcs*SYNC_DATA_REG*] set_false_path -through {*8gphfifoburstrx*} -to [get_registers *8g_rx_pcs*SYNC_DATA_REG*] set_false_path -through {*8gsyncsmen*} -to [get_registers...
Page 411: Simulation Support
UG-01080 13-36 Simulation Support 2015.01.19 For nonbonded clocks, each channel and each TX PLL has a separate dynamic reconfiguration interfaces. The MegaWizard Plug-In Manager provides informational messages on the connectivity of these interfaces. The following example shows the messages for the Arria V Native PHY with four duplex channels, four TX PLLs, in a nonbonded configuration.
Page 412: Arria V Gz Transceiver Native Phy Ip Core
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 413: Device Family Support For Arria V Gz Native Phy
• Final support—Verified with final timing models for this device. • Preliminary support—Verified with preliminary timing models for this device. Table 14-1: Device Family Support This tables lists the level of support offered by the Arria V GZ Transceiver Native PHY IP Core for Altera device families. Device Family...
Page 414: Performance And Resource Utilization For Arria V Gz Native Phy
UG-01080 14-3 Performance and Resource Utilization for Arria V GZ Native PHY 2015.01.19 Performance and Resource Utilization for Arria V GZ Native PHY Because the 10G PCS, Standard PCS, and PMA are implemented in hard logic, the Arria V GZ Native PHY IP Core uses less than 1% of the available ALMs, memory, primary and secondary logic registers.
Page 415: General Parameters For Arria V Gz Native Phy
UG-01080 14-4 General Parameters for Arria V GZ Native PHY 2015.01.19 Clicking Finish generates your customized Arria V GZ Native PHY IP Core. General Parameters for Arria V GZ Native PHY This section describes the datapath parameters in the General Options tab for the Arria V GZ native PHY.
Page 416 UG-01080 14-5 General Parameters for Arria V GZ Native PHY 2015.01.19 Name Range Description Bonding mode In Non-bonded or x1 mode, each channel is paired Non-bonded or x1 with a PLL. Bonded or ×6/xN If one PLL drives multiple channels, PLL merging is fb_compensation required.
Page 417: Pma Parameters For Arria V Gz Native Phy
UG-01080 14-6 PMA Parameters for Arria V GZ Native PHY 2015.01.19 PMA Parameters for Arria V GZ Native PHY This section describes the PMA parameters for the Arria V GZ native PHY. Table 14-3: PMA Options The following table describes the options available for the PMA. For more information about the PMA, refer to the PMA Architecture section in the Transceiver Architecture in Arria V GZ Devices.
Page 418 Arria V GZ ext_pll_clk[<p> -1 : 0] Native PHY. Use the Arria V GZ Transceiver PLL IP Core to instantiate a CMU or ATX PLL. Use Altera Phase- Locked Loop (ALTERA_ PLL) Megafunction to instantiate a fractional PLL. Number of TX PLLs...
Page 419 UG-01080 14-8 PMA Parameters for Arria V GZ Native PHY 2015.01.19 TX PLL<n> Table 14-5: TX PLL Parameters The following table describes how you can define multiple TX PLLs for your Native PHY. The Native PHY GUI provides a separate tab for each TX PLL.
Page 420 UG-01080 14-9 PMA Parameters for Arria V GZ Native PHY 2015.01.19 Parameter Range Description Selected reference clock You can define up to 5 frequencies for the PLLs in source your core. The Reference clock frequency selected for index 0 , is assigned to TX PLL<0>. The Reference clock frequency selected for index 1 , is assigned to TX PLL<1>, and so on.
Page 421 UG-01080 14-10 PMA Parameters for Arria V GZ Native PHY 2015.01.19 Parameter Range Description Enable rx_seriallpbken port On/Off When you turn this option On, the rx_seriallpbken is an input to the core. When your drive a 1 on this input port, the PMA operates in loopback mode with TX data looped back to the RX channel.
Page 422 UG-01080 14-11 PMA Parameters for Arria V GZ Native PHY 2015.01.19 Parameter Range Description Enable rx_set_lockedtodata On/Off When you turn this option On, the rx_set_lockedt- and rx_set_locktoref ports and rx_set_lockedtoref ports are outputs of the data PMA. Enable rx_pma_bitslip_port On/Off...
Page 423 UG-01080 14-12 PMA Parameters for Arria V GZ Native PHY 2015.01.19 FPGA Fabric Interface Width Arria V GZ Latency in UI 80 bits The following tables lists the bits used for all FPGA fabric to PMA interface widths. Regardless of the FPGA Fabric Interface Width selected, all 80 bits are exposed for the TX and RX parallel data ports.
Page 424: Standard Pcs Parameters For The Native Phy
UG-01080 14-13 Standard PCS Parameters for the Native PHY 2015.01.19 Standard PCS Parameters for the Native PHY This section shows the complete datapath and clocking for the Standard PCS and defines the parameters available in the GUI to enable or disable the individual blocks in the Standard PCS.
Page 425 • cpri select this mode if you intend to implement CPRI or another protocol that requires deterministic latency. Altera recommends that you select the appropriate CPRI preset for the CPRI protocol.
Page 426 UG-01080 14-15 Standard PCS Parameters for the Native PHY 2015.01.19 Phase Compensation FIFO The phase compensation FIFO assures clean data transfer to and from the FPGA fabric by compensating for the clock phase difference between the low-speed parallel clock and FPGA fabric interface clock. The following table describes the options for the phase compensation FIFO.
Page 427 UG-01080 14-16 Standard PCS Parameters for the Native PHY 2015.01.19 Parameter Range Description Enable RX byte ordering On/Off When you turn this option On, the PCS includes the byte ordering block. Byte ordering control mode Specifies the control mode for the byte manual ordering block.
Page 428 UG-01080 14-17 Standard PCS Parameters for the Native PHY 2015.01.19 Parameter Range Description Enable rx_std_byteorder_ena port On/Off Enables the optional rx_std_byte_order_ control input port. When this signal is asserted, the byte ordering block initiates a byte ordering operation if the Byte ordering control mode is set to manual.
Page 429 UG-01080 14-18 Standard PCS Parameters for the Native PHY 2015.01.19 Table 14-14: 8B/10B Encoder and Decoder Parameters Parameter Range Description Enable TX 8B/10B encoder On/Off When you turn this option On, the PCS includes the 8B/10B encoder. Enable TX 8B/10B disparity control...
Page 430 FIFO is capable of inserting or deleting the first two bytes (K28.5//D2.2) of /C2/ ordered sets during auto-negotiation. However, the insertion or deletion of the first two bytes of /C2/ ordered sets can cause the auto-negotiation link to fail. For more information, visit Altera Knowledge Base Support Solution.
Page 431 UG-01080 14-20 Standard PCS Parameters for the Native PHY 2015.01.19 Status Condition Protocol Mapping of Status Flags to RX Data Value PHY IP Core for PCI RXD[62:62] = rx_ (2'b10 AND (PAD Express (PIPE) , or rmfifostatus[1:0] OR EDB) = empty)
Page 432 UG-01080 14-21 Standard PCS Parameters for the Native PHY 2015.01.19 Status Condition Protocol Mapping of Status Flags to RX Data Value Basic double width RXD[62:62] = rx_ 2'b01 , or rmfifostatus[1:0] Serial RapidIO double width RXD[46:45] = rx_rmfifos- , or...
Page 433 UG-01080 14-22 Standard PCS Parameters for the Native PHY 2015.01.19 Parameter Range Description RX word aligner mode Specifies one of the following 3 modes for the bit_slip word aligner: sync_sm • Bit_slip : You can use bit slip mode to manual shift the word boundary.
Page 434 UG-01080 14-23 Standard PCS Parameters for the Native PHY 2015.01.19 Parameter Range Description Enable rx_std_wa_patternalign port On/Off Enables the optional rx_std_wa_patterna- control input port. A rising edge on this lign signal causes the word aligner to align the next incoming word alignment pattern when the word aligner is configured in manual mode.
Page 435 UG-01080 14-24 Standard PCS Parameters for the Native PHY 2015.01.19 Parameter Range Description Enable rx_std_bitrev_ena port On/Off When you turn this option On, asserting control port causes the RX std_bitrev_ena data order to be reversed from the normal order, LSB to MSB, to the opposite, MSB to LSB.
Page 436 UG-01080 14-25 Standard PCS Pattern Generators 2015.01.19 PRBS Verifier You can use the PRBS pattern generators for verification or diagnostics. The pattern generator blocks support the following patterns: • Pseudo-random binary sequence (PRBS) • Square wave Table 14-18: PRBS Parameters...
Page 437 UG-01080 14-26 Standard PCS Pattern Generators 2015.01.19 PCS-PMA Width 8-Bit 10-Bit 16-Bit 20-Bit PRBS-10 PRBS 15 PRBS 23 PRBS 31 Unlike the 10G PRBS verifier, the Standard PRBS verifier uses the Standard PCS word aligner. You must specify the word aligner size and pattern. The following table lists the encodings for the available choices.
Page 438 UG-01080 14-27 Standard PCS Pattern Generators 2015.01.19 PCS-PMA Width PRBS Patterns PRBS Pattern Select Word Aligner Size Word Aligner Pattern PRBS 7 3’b000 3’b100 0x0000043040 PRBS 23 3’b001 3’b110 0x00007FFFFF 20-bit PRBS 15 3’b101 3’b100 0x0000007FFF PRBS 31 3’b110 3’b110...
Page 439 UG-01080 14-28 Standard PCS Pattern Generators 2015.01.19 Offset OffsetBits Name Description 0xA3 [15:0] Stores the least significant 16 bits Word Aligner Pattern from the word aligner pattern as [15:0] specified in the previous table. 0xA4 [15] Disables the synchronization state Sync State Machine machine.
Page 440: 10G Pcs Parameters For Arria V Gz Native Phy
UG-01080 14-29 10G PCS Parameters for Arria V GZ Native PHY 2015.01.19 10G PCS Parameters for Arria V GZ Native PHY This section shows the complete datapath and clocking for the 10G PCS and defines parameters available in the GUI to enable or disable the individual blocks in the 10G PCS.
Page 441 UG-01080 14-30 10G PCS Parameters for Arria V GZ Native PHY 2015.01.19 Table 14-23: General and Datapath Parameters Parameter Range Description 10G PCS protocol mode Specifies the protocol that you intend to implement with the Native PHY. The protocol mode selected guides the MegaWizard in identifying legal settings for the 10G PCS datapath.
Page 442 UG-01080 14-31 10G PCS Parameters for Arria V GZ Native PHY 2015.01.19 Table 14-24: 10G TX FIFO Parameters Parameter Range Description TX FIFO Mode Specifies one of the following 3 modes: • interlaken : The TX FIFO acts as an elastic buffer.
Page 443 UG-01080 14-32 10G PCS Parameters for Arria V GZ Native PHY 2015.01.19 Parameter Range Description Enable tx_10g_fifo_pfull port On/Off When you turn this option On , the 10G PCS includes the active high tx_10g_ fifo_pfull port tx_10g_fifo_pfull is synchronous to...
Page 444 UG-01080 14-33 10G PCS Parameters for Arria V GZ Native PHY 2015.01.19 Table 14-25: 10G RX FIFO Parameters Parameter Range Description RX FIFO Mode Specifies one of the following 3 modes: • interlaken : Select this mode for the Interlaken protocol. To implement the deskew process.
Page 445 UG-01080 14-34 10G PCS Parameters for Arria V GZ Native PHY 2015.01.19 Parameter Range Description Enable RX FIFO alignment word deletion On/Off When you turn this option On, all (interlaken) alignment words (sync words), including the first sync word, are removed after frame synchronization is achieved.
Page 446 UG-01080 14-35 10G PCS Parameters for Arria V GZ Native PHY 2015.01.19 Parameter Range Description Enable rx_10g_fifo_insert port On/Off When you turn this option On, the 10G (10GBASE-R) PCS includes the rx_10g_fifo_insert port. This signal is asserted when a word is inserted into the RX FIFO.
Page 447 UG-01080 14-36 10G PCS Parameters for Arria V GZ Native PHY 2015.01.19 Table 14-26: Interlaken Frame Generator Parameters Parameter Range Description teng_tx_framgen_enable On/Off When you turn this option On, the frame generator block of the 10G PCS is enabled. teng_tx_framgen_user_length 0-8192 Specifies the metaframe length.
Page 448 UG-01080 14-37 10G PCS Parameters for Arria V GZ Native PHY 2015.01.19 zation process again. Lock status is available to the FPGA fabric. The following table describes the Interlaken frame synchronizer parameters. Table 14-27: Interlaken Frame Synchronizer Parameters Parameter Range...
Page 449 UG-01080 14-38 10G PCS Parameters for Arria V GZ Native PHY 2015.01.19 Parameter Range Description Enable rx_10g_frame_skip_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_skip_ output port. This signal is asserted to indicate the frame synchronization...
Page 450 UG-01080 14-39 10G PCS Parameters for Arria V GZ Native PHY 2015.01.19 10GBASE-R BER Checker The BER monitor block conforms to the 10GBASE-R protocol specification as described in IEEE 802.3-2008 Clause-49. After block lock is achieved, the BER monitor starts to count the number of invalid synchronization headers within a 125-ms period.
Page 451 UG-01080 14-40 10G PCS Parameters for Arria V GZ Native PHY 2015.01.19 Parameter Range Description Enable TX 64b/66b encoder On/Off When you turn this option On, the 10G PCS includes the TX 64b/66b encoder. Enable TX 64b/66b encoder On/Off When you turn this option On, the 10G PCS includes the RX 64b/66b decoder.
Page 452 UG-01080 14-41 10G PCS Parameters for Arria V GZ Native PHY 2015.01.19 Table 14-32: Interlaken Disparity Generator and Checker Parameters Parameter Range Description Enable Interlaken TX disparity generator On/Off When you turn this option On, the 10G PCS includes the disparity generator.
Page 453 UG-01080 14-42 10G PCS Parameters for Arria V GZ Native PHY 2015.01.19 Gearbox The gearbox adapts the PMA data width to a wider PCS data width when the PCS is not two or four times the PMA width. Table 14-34: Gearbox Parameters...
Page 454 UG-01080 14-43 10G PCS Pattern Generators 2015.01.19 Table 14-35: PRBS Parameters Parameter Range Description Enable rx_10g_prbs ports On/Off When you turn this option On, the PCS includes the rx_10g_prbs_done rx_10g_ signals prbs_err rx_10g_prbs_err_clr to provide status on PRBS operation. Related Information...
Page 455 UG-01080 14-44 10G PCS Pattern Generators 2015.01.19 Offset Bits Name Description [15:12] Specifies the number of consecutive 1s Square Wave Pattern and 0s. The following values are available: 1, 4, 5, 6, 8, and 10. [10] Enables the PRBS-7 polynomial in the TX PRBS 7 Enable transmitter.
Page 456 UG-01080 14-45 10G PCS Pattern Generators 2015.01.19 Offset Bits Name Description [14] Enables the PRBS-7 polynomial in the RX PRBS 7 Enable receiver. [13] Enables the PRBS-23 polynomial in the RX PRBS 23 Enable receiver. [12] Enables the PRBS-9 polynomial in the...
Page 457: Interfaces For Arria V Gz Native Phy
UG-01080 14-46 Interfaces for Arria V GZ Native PHY 2015.01.19 In addition you have the following options: • You can toggle the bit switch between two data patterns. Data Pattern Select • You can change the value of Seed A...
Page 458 UG-01080 14-47 Common Interface Ports for Arria V GZ Native PHY 2015.01.19 Figure 14-5: Arria V GZ Native PHY Common Interfaces Native PHY Common Interfaces ext_pll_clk[<p>-1:0] tx_serial_data[<n>-1:0] TX & RX tx_pll_refclk[< r>-1:0] rx_serial_data[<n>-1:0] Serial Ports Clock Input tx_pma_clkout[<n>-1:0] & Output Signals rx_pma_clkout[<n>-1:0]...
Page 459 UG-01080 14-48 Common Interface Ports for Arria V GZ Native PHY 2015.01.19 Name Direction Description Resets Input When asserted, resets the TX PLL. Active high, pll_powerdown edge sensitive reset signal. By default, the Arria [<n> -1:0] V GZ Native Transceiver PHY IP Core creates...
Page 460 UG-01080 14-49 Common Interface Ports for Arria V GZ Native PHY 2015.01.19 Name Direction Description Input PCS TX parallel data. Used when you enable tx_parallel_data either the Standard or 10G datapath. For the [<n> 64-1:0] Standard datapath, if you turn on Enable...
Page 461 UG-01080 14-50 Common Interface Ports for Arria V GZ Native PHY 2015.01.19 Name Direction Description Input When asserted, the RX detect block in the TX tx_pma_txdetectrx PMA detects the presence of a receiver at the other end of the channel. After receiving a...
Page 462 UG-01080 14-51 Common Interface Ports for Arria V GZ Native PHY 2015.01.19 Name Direction Description Output When asserted, the CDR is locked to the rx_is_lockedtoref incoming reference clock. [<n> -1:0] Input When you turn this signal on, deserializer rx_clkslip performs a clock slip operation to achieve word [<n>...
Page 463 UG-01080 14-52 Common Interface Ports for Arria V GZ Native PHY 2015.01.19 TX Data Word Description Specifies the current disparity as follows: tx_parallel_data[10] • 1'b0 = positive • 1'b1 = negative Signal Definitions with 8B/10B Disabled TX data bus. <w> is the width specified in the tx_parallel_data[<w>-1:0]...
Page 464: Standard Pcs Interface Ports
UG-01080 14-53 Standard PCS Interface Ports 2015.01.19 RX Data Word Description Synchronization status rx_parallel_data[10] Disparity error rx_parallel_data[11] Pattern detect rx_parallel_data[12] The following encodings are defined: rx_parallel_data[14:13] • 2’b00: Normal data • 2’b01: Deletion • 2’b10: Insertion (or Underflow with 9’h1FE or 9’h1F7)
Page 465 UG-01080 14-54 Standard PCS Interface Ports 2015.01.19 Figure 14-6: Standard PCS Interfaces Standard PCS Interface Ports rx_std_bitrev_ena[<n>-1:0] tx_std_clkout[<n>-1:0] tx_std_bitslipboundarysel[5<n>-1:0] rx_std_clkout[<n>-1:0] Clocks rx_std_bitslipboundarysel[5< n>-1:0] tx_std_coreclkin[<n>-1:0] Word rx_std_runlength_err[<n>-1:0] rx_std_coreclkin[<n>-1:0] Aligner rx_std_wa_patternalign[<n>-1:0] rx_std_comdet_ena[<n>-1:0] rx_std_wa_a1a2size[< n>-1:0] rx_std_bitslip[< n>-1:0] rx_std_pcfifo_full[< n>-1:0] Phase rx_std_pcfifo_empty[<n>-1:0] Polarity rx_std_polinv[<n>-1:0] Compensation tx_std_pcfifo_full[<...
Page 466 UG-01080 14-55 Standard PCS Interface Ports 2015.01.19 Name Synchro‐ Description nous to tx_ std_ coreclkin/ rx_std_ coreclkin Output RX phase compensation FIFO status rx_std_pcfifo_empty[<n>- empty flag. 1:0] Output TX phase compensation FIFO status full tx_std_pcfifo_full[<n>- flag. 1:0] Output TX phase compensation FIFO status tx_std_pcfifo_empty[<n>-...
Page 467 UG-01080 14-56 Standard PCS Interface Ports 2015.01.19 Name Synchro‐ Description nous to tx_ std_ coreclkin/ rx_std_ coreclkin Input Polarity inversion for the 8B/10B decoder, rx_std_polinv[<n>-1:0] When set, the RX channels invert the polarity of the received data. You can use...
Page 468 UG-01080 14-57 Standard PCS Interface Ports 2015.01.19 Name Synchro‐ Description nous to tx_ std_ coreclkin/ rx_std_ coreclkin Input BitSlip boundary selection signal. Specifies tx_std_bitslipboun- the number of bits that the TX bit slipper darysel[5<n>-1:0] must slip. Output This signal operates when the word aligner rx_std_bitslipboun- is in bitslip word alignment mode.
Page 469: 10G Pcs Interface
UG-01080 14-58 10G PCS Interface 2015.01.19 Name Synchro‐ Description nous to tx_ std_ coreclkin/ rx_std_ coreclkin Input When asserted, enables a circuit to detect a tx_std_elecidle[<n>-1:0] downstream receiver. This signal must be driven low when not in use because it...
Page 470 UG-01080 14-59 10G PCS Interface 2015.01.19 Figure 14-7: Arria V Native PHY 10G PCS Interfaces 10G PCS Interface Ports tx_10g_coreclkin[<n>-1:0] tx_10g_diag_status[2<n>-1:0] Frame rx_10g_coreclkin[<n>-1:0] tx_10g_burst_en[<n>-1:0] Generator Clocks tx_10g_clkout[<n>-1:0] tx_10g_frame[<n>-1:0] rx_10g_clkout[<n>-1:0] rx_10g_clk33out[<n>-1:0]t rx_10g_frame[<n>-1:0] rx_10g_frame_lock[<n>-1:0] tx_10g_control[8<n>-1:0] rx_10g_pyld_ins[<n>-1:0] tx_10g_data_valid[<n>-1:0] rx_10g_frame_mfrm_err[< n>-1:0] tx_10g_fifo_full[< n>-1:0] rx_10g_frame_sync_err[<n>-1:0] Frame tx_10g_fifo_pfull[<...
Page 471 UG-01080 14-60 10G PCS Interface 2015.01.19 Name Synchro‐ Description nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin TX parallel clock input that drive the write side of Input — tx_10g_coreclkin the TX FIFO. [<n>-1:0] Input — RX parallel clock input that drives the read side of rx_10g_coreclkin the RX FIFO.
Page 472 UG-01080 14-61 10G PCS Interface 2015.01.19 Name Synchro‐ Description nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin • [2]: Inversion signal, must always be set to 1'b0. • [1]: Sync Header, 1 indicates a control word • [0]: Sync Header, 1 indicates a data word 10G BaseR mode: •...
Page 473 UG-01080 14-62 10G PCS Interface 2015.01.19 Name Synchro‐ Description nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin When asserted, indicates if is valid Use of tx_data this signal depends upon the protocol you are implementing, as follows: • 10G BASE-R: Tie to 1'b1 •...
Page 474 UG-01080 14-63 10G PCS Interface 2015.01.19 Name Synchro‐ Description nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin RX control signals for the Interlaken, 10GBASE-R, and Basic protocols. The following signals are defined: Interlaken mode: • [9]: Active-high synchronous status signal that...
Page 475 UG-01080 14-64 10G PCS Interface 2015.01.19 Name Synchro‐ Description nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin Basic mode: 67-bit mode with Block Sync: • [9]: Active-high synchronous status signal that indicates when Block Lock is achieved. • [8]: Active-high synchronous status signal that indicates a sync header error •...
Page 476 UG-01080 14-65 10G PCS Interface 2015.01.19 Name Synchro‐ Description nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin Output Active valid data signal with the following use: rx_10g_data_valid [<n>-1:0] • 10GBASE-R: Always high • Interlaken: Toggles indicating when rx_data valid. • Basic - Phase compensation: Toggles indicating when is valid.
Page 477 UG-01080 14-66 10G PCS Interface 2015.01.19 Name Synchro‐ Description nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin Output Active-high 10G BaseR RX FIFO insertion flag Rx_10g_fifo_insert [<n>-1:0] When asserted, indicates that a word has been inserted into the TX FIFO. This signal is used for the 10GBASE-R protocol.
Page 478 UG-01080 14-67 10G PCS Interface 2015.01.19 Name Synchro‐ Description nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin Output For the Interlaken protocol, asserted to indicate rx_10g_frame_lock that the frame synchronizer state machine has [<n>-1:0] achieved frame lock. This signal is pulse-stretched, you must use a synchronizer.
Page 479 UG-01080 14-68 10G PCS Interface 2015.01.19 Name Synchro‐ Description nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin Output For the Interlaken protocol, asserted to indicate a rx_10g_frame_skip_err Skip Control Word error was received in a Skip [<n>-1:0] Control Word location within the metaframe.
Page 480 UG-01080 14-69 10G PCS Interface 2015.01.19 Name Synchro‐ Description nous to tx_ 10g_ coreclkin/ rx_10g_ coreclkin Bit-Slip Gearbox Feature Synchronizer Input User control bit-slip in the RX Gearbox. Slips one rx_10g_bitslip bit per rising edge pulse. [<n>-1:0] Input TX bit-slip is controlled by port.
Page 481: Sdc Timing Constraints Of Arria V Gz Native Phy
UG-01080 14-70 SDC Timing Constraints of Arria V GZ Native PHY 2015.01.19 SDC Timing Constraints of Arria V GZ Native PHY This section describes SDC examples and approaches to identify false timing paths. The Quartus II software reports timing violations for asynchronous inputs to the Standard PCS and 10G PCS.
Page 482: Dynamic Reconfiguration For Arria V Gz Native Phy
UG-01080 14-71 Dynamic Reconfiguration for Arria V GZ Native PHY 2015.01.19 Example 14-2: Using the max_delay Constraint to Identify Asynchronous Inputs You can use the set_max_delay constraint on a given path to create a constraint for asynchronous signals that do not have a specific clock relationship but require a maximum path delay. The following example illustrates this approach.
Page 483: Simulation Support
UG-01080 14-72 Simulation Support 2015.01.19 Example 14-5: Overriding Logical Channel 0 Channel Assignment Restrictions in Arria V GZ Device for ×6 or ×N Bonding If you are using ×6 or ×N bonding, transceiver dynamic reconfiguration requires that you assign the starting channel number. Logical channel 0 should be assigned to either physical transceiver channel 1 or channel 4 of a transceiver bank.
Page 484: Cyclone V Transceiver Native Phy Ip Core Overview
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 485: Cyclone Device Family Support
• on page 16-1 Cyclone Device Family Support IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: • Final support—Verified with final timing models for this device. • Preliminary support—Verified with preliminary timing models for this device.
Page 486: General Parameters
UG-01080 15-3 General Parameters 2015.01.19 Note: The Cyclone V Transceiver Native PHY provides presets for CPRI, GIGE, and the Low Latency Standard PCS. The presets specify the parameters required to the protocol specified. General Parameters This section lists the parameters available on the General Options tab.
Page 487: Pma Parameters
UG-01080 15-4 PMA Parameters 2015.01.19 Name Range Description Bonding mode Non-bonded or In Non-bonded or x1 mode, each channel is assigned a PLL. Bonded or xN If one PLL drives multiple channels, PLL merging is required. During compilation, the Quartus II Fitter, merges all the PLLs that meet PLL merging requirements.
Page 488: Tx Pma Parameters
UG-01080 15-5 TX PMA Parameters 2015.01.19 Table 15-3: PMA Options Parameter Range Description Data rate Device Specifies the data rate. The maximum data rate is Dependent 12.5 Gbps. TX local clock division factor 1, 2, 4, 8 Specifies the value of the divider available in the...
Page 489: Tx Pll Parameters
UG-01080 15-6 TX PLL Parameters 2015.01.19 Parameter Range Description Use external TX PLL On/Off When you turn this option On, the Native PHY does not include TX PLLs. Instead, the Native PHY includes a input clock port for connection to...
Page 490: Rx Pma Parameters
UG-01080 15-7 RX PMA Parameters 2015.01.19 Parameter Range Description PLL base data rate Device Shows the base data rate of the clock input to the TX PLL.The PLL base data rate is computed Dependent from the TX local clock division factor multiplied by the Data rate.
Page 491 UG-01080 15-8 RX PMA Parameters 2015.01.19 Table 15-6: RX PMA Parameters Parameter Range Description Enable CDR dynamic reconfigura‐ On/Off When you turn this option On, you can tion dynamically change the data rate of the CDR circuit. Number of CDR reference clocks 1–5...
Page 492: Standard Pcs Parameters
UG-01080 15-9 Standard PCS Parameters 2015.01.19 Standard PCS Parameters This section illustrates the complete datapath and clocking for the Standard PCS and defines the parameters available to enable or disable the individual blocks in the Standard PCS. Figure 15-2: The Standard PCS Datapath...
Page 493 CPRI preset for the CPRI protocol. • gige–select this mode if you intend to implement either the 1.25 Gbps or 2.5 Gbps Ethernet protocol. Altera recommends that you select the appropriate preset for the Ethernet protocol. Standard PCS/PMA interface...
Page 494: Phase Compensation Fifo
UG-01080 15-11 Phase Compensation FIFO 2015.01.19 Parameter Range Description Enable Standard PCS low latency On/Off When you turn this option On, all PCS functions mode are disabled except for the phase compensation FIFO, byte serializer and byte deserializer. This option creates the lowest latency Native PHY that allows dynamic reconfigure between multiple PCS datapaths.
Page 495: Byte Ordering Block Parameters
UG-01080 15-12 Byte Ordering Block Parameters 2015.01.19 Parameter Range Description Enable rx_std_pcfifo_full port On/Off When you turn this option On, the RX Phase compensation FIFO outputs a FIFO full status flag. Enable rx_std_pcfifo_empty port On/Off When you turn this option On, the RX Phase compensation FIFO outputs a FIFO empty status flag.
Page 496 UG-01080 15-13 Byte Ordering Block Parameters 2015.01.19 Parameter Range Description Shows width of the pattern that you must specify. This width depends upon the PCS width and whether or not 8B/10B encoding is used as follows: Byte ordering pattern Width...
Page 497: Byte Serializer And Deserializer
UG-01080 15-14 Byte Serializer and Deserializer 2015.01.19 Related Information Transceiver Architecture in Cyclone V Devices Byte Serializer and Deserializer The byte serializer and deserializer allow the PCS to operate at twice the data width of the PMA serializer. This feature allows the PCS to run at a lower frequency and accommodate a wider range of FPGA interface widths.
Page 498: Rate Match Fifo
UG-01080 15-15 Rate Match FIFO 2015.01.19 Parameter Range Description Enable TX 8B/10B disparity On/Off When you turn this option On, the PCS includes control disparity control for the 8B/10B encoder. You force the disparity of the 8B/10B encoder using control...
Page 499 FIFO is capable of inserting or deleting the first two bytes (K28.5//D2.2) of /C2/ ordered sets during auto-negotiation. However, the insertion or deletion of the first two bytes of /C2/ ordered sets can cause the auto-negotiation link to fail. For more information, visit Altera Knowledge Base Support Solution.
Page 500 UG-01080 15-17 Rate Match FIFO 2015.01.19 Status Condition Protocol Mapping of Status Flags to RX Data Value PHY IP Core for PCI RXD[62:62] = rx_ (2'b10 AND (PAD Express (PIPE) , or rmfifostatus[1:0] OR EDB) = empty) Basic double width...
Page 501: Word Aligner And Bitslip Parameters
UG-01080 15-18 Word Aligner and BitSlip Parameters 2015.01.19 Status Condition Protocol Mapping of Status Flags to RX Data Value Basic double width RXD[62:62] = rx_ 2'b01 , or rmfifostatus[1:0] Serial RapidIO double width RXD[46:45] = rx_rmfifos- , or tatus[1:0] RXD[30:29] = rx_...
Page 502 UG-01080 15-19 Word Aligner and BitSlip Parameters 2015.01.19 Parameter Range Description RX word aligner mode bit_slip Specifies one of the following 3 modes for the word aligner: sync_sm • Bit_slip: You can use bit slip mode to shift manual the word boundary. For every rising edge of...
Page 503: Bit Reversal And Polarity Inversion
UG-01080 15-20 Bit Reversal and Polarity Inversion 2015.01.19 Parameter Range Description Enable rx_std_wa_patternalign On/Off Enables the optional rx_std_wa_patternalign port control input port. Enable rx_std_wa_a1a2size port On/Off Enables the optional rx_std_wa_a1a2size control input port. Enable rx_std_bitslipboundarysel On/Off Enables the optional rx_std_wa_bitslipboun- port status output port.
Page 504 UG-01080 15-21 Bit Reversal and Polarity Inversion 2015.01.19 Parameter Range Description Enable TX polarity inversion On/Off When you turn this option On, the port controls polarity std_polinv inversion of TX parallel data before transmitting the parallel data to the PMA.
Page 505: Interfaces
UG-01080 15-22 Interfaces 2015.01.19 Parameter Range Description Enable rx_std_signaldetect port On/Off When you turn this option On, the optional output rx_std_signaldetect port is enabled. This signal is required for the PCI Express protocol. If enabled, the signal threshold detection circuitry senses whether the signal level...
Page 506 UG-01080 15-23 Common Interface Ports 2015.01.19 Figure 15-3: Common Interface Ports Native PHY Common Interfaces ext_pll_clk[<p>-1:0] tx_serial_data[<n>-1:0] TX & RX tx_pll_refclk[< r>-1:0] Clock Input rx_serial_data[<n>-1:0] Serial Ports tx_pma_clkout[<n>-1:0] & Output Signals rx_pma_clkout[<n>-1:0] rx_cdr_refclk[<r>-1:0] rx_seriallpbken[<n>-1:0] rx_setlocktodata[<n>-1:0] rx_setlocktoref[<n>-1:0] Control & pll_locked[<p>-1:0] pll_powerdown[<p>-1:0] Status Ports rx_is_lockedtodata[<n>-1:0]...
Page 507 UG-01080 15-24 Common Interface Ports 2015.01.19 Name Direction Description Input When asserted, resets the TX PLL. Active pll_powerdown[<p>-1:0] high, edge sensitive reset signal. By default, the Cyclone Native Transceiver PHY IP Core create a separate pll_ signal for each logical PLL.
Page 508 UG-01080 15-25 Common Interface Ports 2015.01.19 Name Direction Description TX and RX serial ports Output TX differential serial output data. tx_serial_data[<n>-1:0] Input RX differential serial output data. rx_serial_data[<n>-1:0] Control and Status ports Input When asserted, the transceiver enters rx_seriallpbken[<n>-1:0] serial loopback mode. Loopback drives serial TX data to the RX interface.
Page 509 UG-01080 15-26 Common Interface Ports 2015.01.19 Name Direction Description When you turn this signal on, the Input rx_clkslip[<n>-1:0] deserializer performs a clock slip operation to achieve word alignment. The clock slip operation alternates between skipping 1 serial bit and pausing the serial clock for 2 cycles to achieve word alignment.
Page 510 UG-01080 15-27 Common Interface Ports 2015.01.19 TX Data Word Description Specifies the current disparity as follows: tx_parallel_data[10] • 1'b0 = positive • 1'b1 = negative Signal Definitions with 8B/10B Disabled TX data bus tx_parallel_data[9:0] Unused tx_parallel_data[10] Table 15-18: Location of Valid Data Words for tx_parallel_data for Various FPGA Fabric to PCS...
Page 511: Cyclone V Standard Pcs Interface Ports
UG-01080 15-28 Cyclone V Standard PCS Interface Ports 2015.01.19 RX Data Word Description Pattern detect rx_parallel_data[12] The following encodings are defined: rx_parallel_data[14:13] • 2’b00: Normal data • 2’b01: Deletion • 2’b10: Insertion (or Underflow with 9’h1FE or 9’h1F7) • 2’b11: Overflow...
Page 512 UG-01080 15-29 Cyclone V Standard PCS Interface Ports 2015.01.19 Figure 15-4: Standard PCS Interfaces Standard PCS Interface Ports tx_std_clkout[<n>-1:0] Polarity rx_std_polinv[<n>-1:0] rx_std_clkout[<n>-1:0] Inversion tx_std_polinv[< n>-1:0] Clocks tx_std_coreclkin[<n>-1:0] rx_std_coreclkin[<n>-1:0] rx_std_rmfifo_empty[< n>-1:0] Rate rx_std_rmfifo_full[< n>-1:0] Match FIFO rx_std_bitrev_ena[<n>-1:0] tx_std_bitslipboundarysel[5<n>-1:0] rx_std_pcfifo_full[< n>-1:0] Phase rx_std_bitslipboundarysel[5<...
Page 513 UG-01080 15-30 Cyclone V Standard PCS Interface Ports 2015.01.19 Name Synchronous to Description tx_std_coreclkin/ rx_std_coreclkin Output TX phase compensation FIFO status full tx_std_pcfifo_full[<n>- flag. 1:0] Output TX phase compensation FIFO status tx_std_pcfifo_empty[<n>- empty flag. 1:0] Byte Ordering Input Byte ordering enable. When this signal is rx_std_byteorder_ena[<n>-...
Page 514 UG-01080 15-31 Cyclone V Standard PCS Interface Ports 2015.01.19 Name Synchronous to Description tx_std_coreclkin/ rx_std_coreclkin Input Polarity inversion, part of 8B10B encoder, tx_std_polinv[<n>-1:0] When set, the TX interface inverts the polarity of the TX data. Rate Match FIFO Output Rate match FIFO empty flag. When rx_std_rmfifo_empty[<n>-...
Page 515: Sdc Timing Constraints
UG-01080 15-32 SDC Timing Constraints 2015.01.19 Name Synchronous to Description tx_std_coreclkin/ rx_std_coreclkin Input Active when you place the word aligner in rx_st_wa_patternalign manual mode. In manual mode, you align words by asserting rx_st_wa_patternalign. rx_st_wa_patternalign is edge sensitive. For more information refer to the Word Aligner section in the Transceiver Architec‐...
Page 516: Dynamic Reconfiguration
UG-01080 15-33 Dynamic Reconfiguration 2015.01.19 The Quartus II software reports timing violations for asynchronous inputs to the Standard PCS. Because many violations are for asynchronous paths, they do not represent actual timing failures. You may choose one of the following three approaches to identify these false timing paths to the Quartus II or TimeQuest software.
Page 517: Simulation Support
UG-01080 15-34 Simulation Support 2015.01.19 For non-bonded clocks, each channel and each TX PLL has a separate dynamic reconfiguration interfaces. The MegaWizard Plug-In Manager provides informational messages on the connectivity of these interfaces. The following example shows the messages for the Cyclone V Native PHY with four duplex channels, four TX PLLs, in a nonbonded configuration.
Page 518: Transceiver Reconfiguration Controller Ip Core Overview
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 519: Transceiver Reconfiguration Controller System Overview
UG-01080 16-2 Transceiver Reconfiguration Controller System Overview 2015.01.19 Area Feature Stratix V Arria V Arria V GZ Cyclone V RX CDR reconfiguration Reconfiguration of PCS blocks TX PLL switching Transceiver ATX PLL switching — — Channel/PLL Reconfiguration TX local clock divider...
Page 520 UG-01080 16-3 Transceiver Reconfiguration Controller System Overview 2015.01.19 Figure 16-1: Transceiver Reconfiguration Controller Altera V-Series FPGA TX and RX Transceiver PHY Serial Data Streaming Data User Application Including MAC Transceiver Reconfiguration reconfig_from_xcvr[ <n> :0] Reconfiguration Management Controller Registers to Interface...
Page 521 UG-01080 16-4 Transceiver Reconfiguration Controller System Overview 2015.01.19 The Transceiver Reconfiguration Controller provides two modes to dynamically reconfigure transceiver settings: • Register Based—In this access mode you can directly reconfigure a transceiver PHY IP core using the Transceiver Reconfiguration Controller’s reconfiguration management interface. You initiate reconfi‐...
Page 522: Transceiver Reconfiguration Controller Performance And Resource Utilization
UG-01080 16-5 Transceiver Reconfiguration Controller Performance and Resource Utilization 2015.01.19 Transceiver Reconfiguration Controller Performance and Resource Utilization This section describes the approximate device resource utilization for a the Transceiver Reconfiguration Controller for Stratix V devices. The numbers of combinational ALUTs and logic registers are rounded to the nearest 50.
Page 523: Parameterizing The Transceiver Reconfiguration Controller Ip Core In Qsys
UG-01080 16-6 Parameterizing the Transceiver Reconfiguration Controller IP Core in Qsys 2015.01.19 Parameterizing the Transceiver Reconfiguration Controller IP Core in Qsys Complete the following steps to configure the Transceiver Reconfiguration Controller IP Core in Qsys: 1. On the Project Settings tab, select Arria V, Arria V GZ, Cyclone V, or Stratix V from the list.
Page 524 UG-01080 16-7 General Options Parameters 2015.01.19 Name Value Description Transceiver Calibration Functions Enable offset cancellation When enabled, the Transceiver Reconfigura‐ tion Controller includes the offset cancellation functionality. This option is always on. Offset cancellation occurs automatically at power-up and runs only once.
Page 525: Transceiver Reconfiguration Controller Interfaces
UG-01080 16-8 Transceiver Reconfiguration Controller Interfaces 2015.01.19 Name Value Description Enable PLL reconfiguration On/Off When enabled, the Transceiver Reconfigura‐ support block tion Controller includes logic to perform PLL reconfiguration. Transceiver Reconfiguration Controller Interfaces This section describes the top-level signals of the Transceiver Reconfiguration Controller.
Page 526: Transceiver Reconfiguration Interface
UG-01080 16-9 Transceiver Reconfiguration Interface 2015.01.19 Signal Name Direction Description Output When asserted, signals an Avalon-MM read reconfig_mif_read request. Input The read data. reconfig_mif_readdata[15:0] Input When asserted, indicates that the MIF Avalon-MM reconfig_mif_waitrequest slave is not ready to respond to a read request.
Page 527: Reconfiguration Management Interface
UG-01080 16-10 Reconfiguration Management Interface 2015.01.19 Signal Name Direction Description Output This optional signal is asserted while initial TX calibra‐ tx_cal_busy tion is in progress and no further reconfiguration operations should be performed. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP.
Page 528 UG-01080 16-11 Reconfiguration Management Interface 2015.01.19 Table 16-7: Reconfiguration Management Interface Signal Name Direction Description Input Avalon-MM clock input. The frequency range for the mgmt_clk_clk mgmt_ is 100-125 MHz for Stratix V and Arria V GZ clk_clk devices. It is 75-125 MHz for Arria V devices. For Cyclone V devices, the frequency range is 75-125MHz if the Cyclone V Hard IP for PCI Express IP Core is not enabled.
Page 529: Transceiver Reconfiguration Controller Memory Map
UG-01080 16-12 Transceiver Reconfiguration Controller Memory Map 2015.01.19 Signal Name Direction Description Input Read signal. Active high. reconfig_mgmt_read Related Information Avalon Interface Specifications Transceiver Reconfiguration Controller Memory Map Each register-based feature has its own Avalon-MM address space within the Transceiver Reconfiguration Controller.
Page 530: Transceiver Reconfiguration Controller Calibration Functions
(DCD). DCD calibration function reduces this distortion. DCD runs once during device power up and you can manually trigger DCD after power up. Altera recommends that you enable DCD for Arria V and Cyclone V devices if either of the following conditions is true: •...
Page 531: Auxiliary Transmit (Atx) Pll Calibration
UG-01080 16-14 Auxiliary Transmit (ATX) PLL Calibration 2015.01.19 Auxiliary Transmit (ATX) PLL Calibration ATX calibration tunes the parameters of the ATX PLL for optimal performance. This function runs once after power up. You can rerun this function by writing into the appropriate memory-mapped registers.
Page 532 UG-01080 16-15 Transceiver Reconfiguration Controller PMA Analog Control Registers 2015.01.19 Reconfig Addr Bits Register Name Description . When asserted, indicates an error. Error This bit is asserted if any of the following conditions occur: • The channel address is invalid.
Page 533: Transceiver Reconfiguration Controller Eyeq Registers
UG-01080 16-16 Transceiver Reconfiguration Controller EyeQ Registers 2015.01.19 Offset Bits Register Name Description [4:0] Pre-emphasis second post-tap The following encodings are defined: • 5’b00000 and 5’b10000: 0 • 5’b00001–5’b01111: -15 to -1 • 5’b10001–5b’11111: 1 to 15 0x10 [2:0] RX equalization DC gain...
Page 534 UG-01080 16-17 Transceiver Reconfiguration Controller EyeQ Registers 2015.01.19 EyeQ uses a phase interpolator and sampler to estimate the vertical and horizontal eye opening using the Table 16-12table. values that you specify for the horizontal phase and vertical height as described in the The phase interpolator generates a sampling clock and the sampler examines the data from the sampler output.
Page 535 UG-01080 16-18 Transceiver Reconfiguration Controller EyeQ Registers 2015.01.19 Note: All undefined register bits are reserved. Table 16-12: EyeQ Offsets and Values Note: The default value for all the register bits mentioned in this table is 0. Offset Bits Register Name...
Page 536: Eyeq Usage Example
UG-01080 16-19 EyeQ Usage Example 2015.01.19 Offset Bits Register Name Description [15:4] RMW Reserved You should not modify these bits. To update this register, first read the value of this register then change only the value for bits that are not reserved.
Page 537: Transceiver Reconfiguration Controller Dfe Registers
UG-01080 16-20 Transceiver Reconfiguration Controller DFE Registers 2015.01.19 as a diagnostic tool to perform in-system link analysis without interrupting the link traffic. The steps below provide BERB operation example: • Write 3'b111 to bit[2:0] in offset 0x0 to enable BERB •...
Page 538 UG-01080 16-21 Transceiver Reconfiguration Controller DFE Registers 2015.01.19 Reconfig Addr Bits Register Name Description .When asserted, indicates an invalid Error channel or address. . When asserted, indicates that a Busy reconfiguration operation is in progress. 7’h1A control and status . Writing a 1 to this bit triggers a read Read operation.
Page 539: Controlling Dfe Using Register-Based Reconfiguration
UG-01080 16-22 Controlling DFE Using Register-Based Reconfiguration 2015.01.19 Offset Bits Register Name Description Specifies the polarity of the fourth post tap as tap 4 polarity follows: • 0: negative polarity • 1: positive polarity [2:0] RW Specifies the coefficient for the fourth post tap.
Page 540: Turning On Triggered Dfe Mode
UG-01080 16-23 Turning on Triggered DFE Mode 2015.01.19 The register-based write to turn on continuous adaptive DFE for logical channel 0 is as shown in the following example: Example 16-1: Register-Based Write To Turn On Adaptive DFE for Logical Channel 0...
Page 541: Transceiver Reconfiguration Controller Aeq Registers
UG-01080 16-24 Transceiver Reconfiguration Controller AEQ Registers 2015.01.19 1. Read the DFE register busy bit (bit 8) until it is clear. control and status 2. Write the logical channel number of the channel to be updated to the DFE number logical channel register.
Page 542 UG-01080 16-25 Transceiver Reconfiguration Controller AEQ Registers 2015.01.19 Table 16-15: AEQ Registers Reconfig Addr Bits Register Name Description 7’h28 [9:0] The logical channel number of the AEQ logical channel number hardware to be accessed. Must be specified when performing dynamic updates. The...
Page 543: Transceiver Reconfiguration Controller Atx Pll Calibration Registers
UG-01080 16-26 Transceiver Reconfiguration Controller ATX PLL Calibration Registers 2015.01.19 Table 16-16: AEQ Offsets and Values Offset Bits Register Name Description Default Value When asserted, indicates that adaptation has 1b’0 adapt_done completed. In One-Time Adaptation Mode, AEQ stops searching new EQ settings even if the signal quality of incoming serial data is inadequate.
Page 544 UG-01080 16-27 Transceiver Reconfiguration Controller ATX PLL Calibration Registers 2015.01.19 Table 16-17: ATX Tuning Registers ATX Addr Bits Register Name Description 7’h30 [9:0] The logical channel number. The logical channel number Transceiver Reconfiguration Controller maps the logical address to the physical address.
Page 545: Transceiver Reconfiguration Controller Pll Reconfiguration
UG-01080 16-28 Transceiver Reconfiguration Controller PLL Reconfiguration 2015.01.19 Transceiver Reconfiguration Controller PLL Reconfiguration You can use the PLL reconfiguration registers to change the reference clock input to the TX PLL or the clock data recovery (CDR) circuitry. The PLL registers for dynamic reconfiguration feature are available when you select one of the following transceiver PHY IP cores: •...
Page 546 Note: If you dynamically reconfigure PLLs, you must provide your own reset logic by including the Altera Reset Controller IP Core or your own custom reset logic in your design. For more informa‐ tion about the Altera-provided reset controller, refer to Chapter 17, Transceiver PHY Reset Controller IP Core.
Page 547: Transceiver Reconfiguration Controller Pll Reconfiguration Registers
UG-01080 16-30 Transceiver Reconfiguration Controller PLL Reconfiguration Registers 2015.01.19 Related Information Transceiver Reset Control in Stratix V Devices • Transceiver Reset Control and Power-Down in Arria V Devices • Transceiver Reset Control and Power Down in Cyclone V Devices •...
Page 548: Transceiver Reconfiguration Controller Dcd Calibration Registers
UG-01080 16-31 Transceiver Reconfiguration Controller DCD Calibration Registers 2015.01.19 Reconfig Addr Bits Register Name Description 7’h44 [15:0] RW Specifies the read or write data. data Note: All undefined register bits are reserved. Table 16-20: PLL Reconfiguration Offsets and Values Offset...
Page 549: Transceiver Reconfiguration Controller Channel And Pll Reconfiguration
DCD runs automatically at power up. After power up, you can rerun DCD by writing to the DCD control register. Altera recommends that you run DCD calibration for Arria V and Cyclone V devices if the data rate is greater than 4.9152 Gbps.
Page 550: Channel Reconfiguration
UG-01080 16-33 Channel Reconfiguration 2015.01.19 Channel Reconfiguration If you turn on Enable channel/PLL reconfiguration in the Transceiver Reconfiguration Controller GUI, you can change the following channel settings: • TX PMA settings • RX PMA settings • RX CDR input clock •...
Page 551: Transceiver Reconfiguration Controller Streamer Module Registers
UG-01080 16-34 Transceiver Reconfiguration Controller Streamer Module Registers 2015.01.19 Transceiver Reconfiguration Controller Streamer Module Registers The Streamer module defines the following two modes for channel and PLL reconfiguration: • Mode 0—MIF. Uses a memory initialization file (.mif) to reconfigure settings.
Page 552 UG-01080 16-35 Transceiver Reconfiguration Controller Streamer Module Registers 2015.01.19 PHY Addr Bits Register Name Description . Writing a 1 to this bit triggers a read Read operation. This bit is self clearing. . Writing a 1 to this bit triggers a write Write operation.
Page 553: Mode 0 Streaming A Mif For Reconfiguration
UG-01080 16-36 Mode 0 Streaming a MIF for Reconfiguration 2015.01.19 Offset Bits Register Name Description When asserted, indicates the MIF type MIF or Channel mismatch specified is incorrect. For example, the logical channel is duplex, but the MIF type specifies an RX only channel. The following 5 MIF types are defined: •...
Page 554: Mif Generation
UG-01080 16-37 MIF Generation 2015.01.19 MIF Generation The MIF stores the configuration data for the transceiver PHY IP cores. The Quartus II software automatically generates MIFs after each successful compilation. MIFs are stored in the reconfig_mif folder of the project's working directory. This folder stores all MIFs associated with the compiled project for each transceiver PHY IP core instance in the design.
Page 555: Mif Format
UG-01080 16-38 MIF Format 2015.01.19 The Quartus II software automatically generates MIF for all designs that support POF generation with the following exceptions: • Designs that use bonded channels so that the same TX PLL output drives several channels • GT channels •...
Page 556: Xcvr_Diffmifgen Utility
UG-01080 16-39 xcvr_diffmifgen Utility 2015.01.19 Table 16-27: Required Lines for All MIFs Line Number Description Content Includes Specifies start of the reconfiguration Start of MIF opcode Specifies the type of MIF Type of MIF opcode Specifies the reference clock RefClk switch opcode...
Page 557 UG-01080 16-40 xcvr_diffmifgen Utility 2015.01.19 information necessary to change from 1 Gbps to 5 Gbps and from 5 Gbps to 1 Gbps. You can use these files to reduce reconfiguration and simulation times. utility can operate on up to five MIF files. This utility only works on MIF files at xcvr_diffmifgen the same revision level.
Page 558 UG-01080 16-41 xcvr_diffmifgen Utility 2015.01.19 Example 16-6: Two Partial MIF files The following example shows and the reduced MIF file, to_MIF_A created by the xcvr_diffmifgen utility: Example 16-7: Reduced MIF File to_MIF_A Note: The utility only works for Quartus II post-fit simulation and hardware.
Page 559: Reduced Mif Creation
UG-01080 16-42 Reduced MIF Creation 2015.01.19 Reduced MIF Creation The procedure described here is an alternative way to generate a reduced MIF file. You can also use the Utility. Follow these steps to generate a reduced MIF: xcvr_diffmifgen 1. Determine the content differences between the original MIF and the reconfigured MIF. For this example, assume there are bit differences at offset 5 and offset 20.
Page 560: Register-Based Read
UG-01080 16-43 Register-Based Read 2015.01.19 Example 16-8: Register-Based Write of Logical Channel 0 V Setting System Console is used for the following settings: #Setting logical channel 0 write_32 0x8 0x0 #Setting offset to VOD write_32 0xB 0x0 #Setting data register to 40...
Page 561: Direct Write Reconfiguration
UG-01080 16-44 Direct Write Reconfiguration 2015.01.19 Direct Write Reconfiguration Follow these steps to reconfigure a transceiver setting using a series of Avalon-MM direct writes. 1. Write the logical channel number to the Streamer channel register. logical 2. Write Direct Mode, 2'b01, to the Streamer register bits.
Page 562: Streamer-Based Reconfiguration
UG-01080 16-45 Streamer-Based Reconfiguration 2015.01.19 write_32 0x3A 0x5 #Read the busy bit to determine when the operation completes read_32 0x3a #Incrementing Streamer offset register offset address write_32 0x3B 0x1 #Read the busy bit to determine when the operation completes read_32 0x3a...
Page 563: Pattern Generators For The Stratix V And Arria V Gz Native Phys
UG-01080 16-46 Pattern Generators for the Stratix V and Arria V GZ Native PHYs 2015.01.19 write_32 0x3B 0x0 #Setting data register with the MIF base address write_32 0x3C 0x100 #Writing all data to the Streamer write_32 0x3A 0x1 #Setting Streamer Module offset for Start MIF stream...
Page 564: Enabling The Standard Pcs Prbs Generator Using Streamer-Based Reconfiguration
UG-01080 16-47 Enabling the Standard PCS PRBS Generator Using Streamer-Based Reconfiguration 2015.01.19 , (offset 0xA1, bits[15:14]) Sync badcg , (offset 0xA1, bit[13]) Enable Comma Detect , (offset, 0xA1, bit[11]) Enable Polarity 8. Now, you must set the proper value for the bit.
Page 565: Enabling The 10G Pcs Prbs Generator Or Verifier Using Streamer-Based Reconfiguration
UG-01080 16-48 Enabling the 10G PCS PRBS Generator or Verifier Using Streamer-Based 2015.01.19 Reconfiguration , (0x97, bit[9]) PRBS TX Enable , (0x97, bit[8:6]) PRBS Pattern Select 7. Assert the channel reset to begin testing on the new PRBS pattern. Enabling the 10G PCS PRBS Generator or Verifier Using Streamer-Based...
Page 566 UG-01080 16-49 Enabling the 10G PCS PRBS Generator or Verifier Using Streamer-Based 2015.01.19 Reconfiguration write_32 0x3A 0x6 //write the control and status register //with a value of 0x6 to address 0x3A to initiate a read read_32 0x3C //Read the value at address 0x3C RMW {3’b10-,{read_32 0x3C}} //Perform a read-modify-write...
Page 567: Disabling The Standard Pcs Prbs Generator And Verifier Using Streamer-Based Reconfiguration
UG-01080 16-50 Disabling the Standard PCS PRBS Generator and Verifier Using Streamer-Based 2015.01.19 Reconfiguration //Generator selection and setup read_32 0x3A //Read the control and status register //busy bit[8] until it is clear write_32 0x38 0x0 //write logical channel to 0x38...
Page 568 UG-01080 16-51 Understanding Logical Channel Numbering 2015.01.19 The transceiver PHY IP cores create a separate reconfiguration interface for each channel and each TX PLL. Each transceiver PHY IP core reports the number of reconfiguration interfaces it requires in the message pane of its GUI. You must take note of this number so that you can enter it as a parameter in the Transceiver Reconfiguration Controller.
Page 569 UG-01080 16-52 Understanding Logical Channel Numbering 2015.01.19 Figure 16-10: Transceiver Reconfiguration Controller Interface Bundles The following figure shows a design with two transceiver PHY IP core instances, each with four channels. For this design you would enter 16 for the Number of reconfiguration interfaces and 8, 8 for the Optional interface grouping parameter.
Page 570: Two Phy Ip Core Instances Each With Four Bonded Channels
UG-01080 16-53 Two PHY IP Core Instances Each with Four Bonded Channels 2015.01.19 Two PHY IP Core Instances Each with Four Bonded Channels This section describes logical channel numbering for two transceiver PHY instances, each with four bonded channels, connected to a Transceiver Reconfiguration Controller.
Page 571: One Phy Ip Core Instance With Eight Bonded Channels
UG-01080 16-54 One PHY IP Core Instance with Eight Bonded Channels 2015.01.19 Logical Interface Number PHY Instance, Interface, or PLL 12-15 Instance 1, TX PLL. The Fitter assigns all 4 logical TX PLLs to a single physical PLL. One PHY IP Core Instance with Eight Bonded Channels This section describes logical channel numbering for one transceiver instance with eight bonded channels.
Page 572: Two Phy Ip Core Instances Each With Non-Bonded Channels
UG-01080 16-55 Two PHY IP Core Instances Each with Non-Bonded Channels 2015.01.19 Note: Because all of the channels in a transceiver bank share a PLL, this original numbering allows the Fitter to select the optimal CMU PLL from a placement perspective by considering all of the TX PLLs in the bank.
Page 573: Transceiver Reconfiguration Controller To Phy Ip Connectivity
UG-01080 16-56 Transceiver Reconfiguration Controller to PHY IP Connectivity 2015.01.19 Table 16-32: Initial Number of Eight Bonded Channels Instance Channel Logical Channel Number Channel 0 Channel 1 Channel 2 Channel 3 Instance 0 CMU 0 CMU 1 CMU 2 CMU 3...
Page 574: Merging Tx Plls In Multiple Transceiver Phy Instances
UG-01080 16-57 Merging TX PLLs In Multiple Transceiver PHY Instances 2015.01.19 Figure 16-12: Correct Connections Stratix V GX, GS, or GT Device Transceiver Bank Reconfig to 3 Transceiver and from (unused) Channels Transceiver Transceiver (unused) Reconfiguration to Embedded Controller Processor...
Page 575: Sharing Reconfiguration Interface For Multi-Channel Transceiver Designs
UG-01080 16-58 Sharing Reconfiguration Interface for Multi-Channel Transceiver Designs 2015.01.19 The Quartus II Fitter can merge the TX PLLs for multiple transceiver PHY IP cores under the following conditions: • The PLLs connect to the same reset pin. • The PLLs connect to the same reference clock.
Page 576 UG-01080 16-59 Loopback Modes 2015.01.19 post-CDR mode, received data passes through the RX CDR and then loops back to the TX output buffer. The RX data is also available to the FPGA fabric. In the TX channel, only the TX buffer is active.
Page 577 UG-01080 16-60 Loopback Modes 2015.01.19 Figure 16-16: Serial Loopback Transceiver Tx PMA Serializer Tx P C S tx_dataout FPGA Serial Fabric loopback Rx PMA To FPGA fabric for verification Rx P C S serializer Related Information PCI Express Base Specification...
Page 578: Transceiver Phy Reset Controller Ip Core
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 579 UG-01080 17-2 Transceiver PHY Reset Controller IP Core 2015.01.19 Figure 17-1: Typical System Diagram for the Transceiver PHY Reset Controller IP Core This figure illustrates the typical use of Transceiver PHY Reset Controller in a design that includes a transceiver PHY instance and the Transceiver Reconfiguration Controller IP Core. You can use the phy_mgmt_clk and phy_mgmt_clk_reset as the clock and reset to the user-controller reset logic.
Page 580: Device Family Support For Transceiver Phy Reset Controller
• Final support—Verified with final timing models for this device. • Preliminary support—Verified with preliminary timing models for this device. Table 17-1: Device Family Support This table lists the level of support offered by the Transceiver PHY Reset Controller IP core for Altera device families. Device Family...
Page 581: Parameterizing The Transceiver Phy Reset Controller Ip
UG-01080 17-4 Parameterizing the Transceiver PHY Reset Controller IP 2015.01.19 Parameterizing the Transceiver PHY Reset Controller IP This section lists steps to configure the Transceiver PHY Reset Controller IP Core in the IP Catalog. You can customize the following Transceiver PHY Reset Controller parameters for different modes of operation by clicking Tools >...
Page 582 UG-01080 17-5 Transceiver PHY Reset Controller Parameters 2015.01.19 Name Range Description Enable TX PLL reset control On /Off When On, the Transceiver PHY Reset Controller IP core enables the reset control of the TX PLL. When Off, the TX PLL reset control is disabled.
Page 583: Transceiver Phy Reset Controller Interfaces
UG-01080 17-6 Transceiver PHY Reset Controller Interfaces 2015.01.19 Name Range Description RX Channel Enable RX channel reset control On /Off When On, the Transceiver PHY Reset Controller enables the control logic and associated status signals for RX reset. When Off, disables RX reset control and status signals.
Page 584 UG-01080 17-7 Transceiver PHY Reset Controller Interfaces 2015.01.19 Figure 17-2: Transceiver PHY Reset Controller IP Core Top-Level Signals Generating the IP core creates signals and ports based on your parameter settings. Transceiver PHY Reset Controller Top-Level Signals tx_digitalreset[<n>–1:0] pll_locked[<p>–1:0] tx_analogreset[<n>–1:0] pll_select[<p*n>–1:0] (1)
Page 585 UG-01080 17-8 Transceiver PHY Reset Controller Interfaces 2015.01.19 Signal Name Direction Clock Domain Description Input Asynchronous This is calibration status signal from the rx_cal_busy[<n> - Transceiver PHY IP core. When asserted, the 1:0] initial calibration is active. When deasserted, calibration has completed. It will not be asserted if you manually re-trigger the calibra‐...
Page 586 UG-01080 17-9 Transceiver PHY Reset Controller Interfaces 2015.01.19 Signal Name Direction Clock Domain Description Output Synchronous to the Digital reset for TX channels. The width of this tx_digital- Transceiver PHY signal depends on the number of TX channels. reset[<n>-1:0] Reset Controller This signal is asserted when any of the input clock.
Page 587: Timing Constraints For Bonded Pcs And Pma Channels
UG-01080 17-10 Timing Constraints for Bonded PCS and PMA Channels 2015.01.19 Signal Name Direction Clock Domain Description Output Synchronous to the Digital reset for RX. The width of this signal rx_digital- Transceiver PHY depends on the number of channels. This signal reset[<n>...
Page 588 UG-01080 17-11 Timing Constraints for Bonded PCS and PMA Channels 2015.01.19 Figure 17-3: Physical Routing Delay Skew in Bonded Channels FPGA Fabric PHY Reset Controller Channel[ n - 1] tx_digitalreset Bonded TX Channels Channel[1] Channel[0] You must provide a Synopsys Design Constraint (SDC) for the reset signals to guarantee that your design meets timing requirements.
Page 589 UG-01080 17-12 Timing Constraints for Bonded PCS and PMA Channels 2015.01.19 constraint, refer to the SDC and TimeQuest API Reference For more information about the set_max_skew Manual. Related Information SDC and TimeQuest API Reference Manual Transceiver PHY Reset Controller IP Core...
Page 590: Transceiver Pll Ip Core For Stratix V, Arria V, And Arria V Gz Devices
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 591 • on page 19-11 • Analog Settings for Stratix V Devices on page 19-34 Altera Phase-Locked Loop (ALTERA_PLL) Megafunction User Guide • Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices Altera Corporation Send Feedback...
Page 592: Parameterizing The Transceiver Pll Phy
UG-01080 18-3 Parameterizing the Transceiver PLL PHY 2015.01.19 Parameterizing the Transceiver PLL PHY The IP Catalog provides the following Transceiver PLL IP Cores: Arria V Transceiver, Arria V GZ Transceiver PLL, and Stratix V Transceiver PLL to be used with the Arria V, Arria V GZ and Stratix V Native PHYs, respectively.
Page 593: Transceiver Pll Signals
UG-01080 18-4 Transceiver PLL Signals 2015.01.19 Name Value Description Reference clock frequency Variable Specifies the frequency of the PLL input reference clock. The PLL must generate an output frequency that equals the Base data rate/2. You can use any Input clock frequency that allows the PLLs to generate this output frequency.
Page 594 UG-01080 18-5 Transceiver PLL Signals 2015.01.19 Related Information Component Interface Tcl Reference Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices Altera Corporation Send Feedback...
Page 595: Analog Parameters Set Using Qsf Assignments
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 596: Analog Settings For Arria V Devices
UG-01080 19-2 Analog Settings for Arria V Devices 2015.01.19 a. Double-click in the Assignment Name column and scroll to the bottom of the available assignments. b. Select VCCR_GXB/VCCT_GXB Voltage. c. In the Value column, select 1_0V from the list. The Quartus II software adds these instance assignments commands to the .qsf file for your project.
Page 597 Specifies the intended termination value for the specified refclk pin. The following 3 settings are available: • AC_COUPLING: Altera recommends this setting for all transceiver designs. Use it for AC coupled signals. This setting implements on-chip termination and on-chip signal biasing.
Page 598: Analog Settings Having Global Or Computed Values For Arria V Devices
UG-01080 19-4 XCVR_VCCR_ VCCT_VOLTAGE 2015.01.19 XCVR_VCCR_ VCCT_VOLTAGE Pin Planner and Assignment Editor Name VCCR_GXB VCCT_GXB Voltage Description Configures the VCCR_GXB and VCCT_GXB voltage for an GXB I/O pin by specifying the intended supply voltages for a GXB I/O pin. Options...
Page 599 UG-01080 19-5 PLL_BANDWIDTH_PRESET 2015.01.19 PLL_BANDWIDTH_PRESET Pin Planner and Assignment Editor Name PLL Bandwidth Preset Description Specifies the PLL bandwidth preset setting Options • Auto • Low • Medium • High Assign To PLL instance XCVR_RX_DC_GAIN Pin Planner and Assignment Editor Name...
Page 600 XCVR_RX_COMMON_MODE_VOLTAGE Pin Planner and Assignment Editor Name Receiver Buffer Common Mode Voltage Description Receiver buffer common-mode voltage. Note: Contact Altera for using this assignment. Related Information How to Contact Altera on page 21-42 Analog Parameters Set Using QSF Assignments Altera Corporation...
Page 601 UG-01080 19-7 XCVR_RX_LINEAR_EQUALIZER_CONTROL 2015.01.19 XCVR_RX_LINEAR_EQUALIZER_CONTROL Pin Planner and Assignment Editor Name Receiver Linear Equalizer Control Description Static control for the continuous time equalizer in the receiver buffer. The equalizer has 3 settings from 0– 2 corresponding to the increasing AC gain.
Page 602 UG-01080 19-8 XCVR_RX_SD_ON 2015.01.19 Assign To Pin - RX serial data XCVR_RX_SD_ON Pin Planner and Assignment Editor Name Receiver Cycle Count Before Signal Detect Block Declares Presence Of Signal Description Number of parallel cycles to wait before the signal detect block declares presence of signal. Only used for the PCIe PIPE PHY, SATA, and SAS protocols.
Page 603 XCVR_TX_COMMON_MODE_VOLTAGE Pin Planner and Assignment Editor Name Transmitter Common Mode Driver Voltage Description Transmitter common-mode driver voltage. Note: Contact Altera for using this assignment. Related Information How to Contact Altera on page 21-42 XCVR_TX_PRE_EMP_1ST_POST_TAP Pin Planner and Assignment Editor Name...
Page 604 UG-01080 19-10 XCVR_TX_RX_DET_MODE 2015.01.19 Options • TRUE • FALSE Assign To Pin - TX serial data XCVR_TX_RX_DET_MODE Pin Planner and Assignment Editor Name Transmitter Receiver Detect Block Mode Description Sets the mode for receiver detect block. Options 0–15 Assign To...
Page 605: Analog Settings For Arria V Gz Devices
UG-01080 19-11 Analog Settings for Arria V GZ Devices 2015.01.19 Description When set to , the PCS block controls the V and pre-emphasis coefficients for PCI DYNAMIC_CTL Express. When this assignment is set to the V and pre-emphasis are controlled by other...
Page 606 Specifies the intended termination value for the specified refclk pin. The following 3 settings are available: • AC_COUPLING: Altera recommends this setting for all transceiver designs. Use it for AC coupled signals. This setting implements on-chip termination and on-chip signal biasing.
Page 607 UG-01080 19-13 XCVR_TX_SLEW_RATE_CTRL 2015.01.19 a value to this setting and results in a Quartus II Fitter error as shown XCVR_ANALOG_SETTINGS_PROTOCOL in the following example: Error (21215) Error resolving parameter "pm_rx_sd_bypass_eqz_stages_234" value on instance "pci_interface_ddf2:u_pci_interface_2| PCIE_8x8Gb_HARDIP_2:PCIe2_Interface.U_PCIE_CORE| altpcie_sv_hip_ast_hwtcl:pcie_8x8gb_hardip_2_inst| altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b |sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native: inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_rx_pma:rx_pma. sv_rx_pma_inst|rx_pmas[8].rx_pma.rx_pma_buf": Only one QSF setting for the parameter is allowed.
Page 608: Analog Settings Having Global Or Computed Default Values For Arria V Gz Devices
UG-01080 19-14 XCVR_VCCR_VCCT_VOLTAGE 2015.01.19 Description Configure the VCCA_GXB voltage for a GXB I/O pin by specifying the intended VCCA_GXB voltage for a GXB I/O pin. If you do not make this assignment the compiler automatically sets the correct VCCA_GXB voltage depending on the configured data rate, as follows: •...
Page 609 UG-01080 19-15 master_ch_number 2015.01.19 Description Specifies the CDR bandwidth preset setting Options • Auto • Low • Medium • High Assign To PLL instance master_ch_number Pin Planner and Assignment Editor Name Parameter (Assignment Editor Only) Description For the PHY IP Core for PCI Express (PIPE), specifies the channel number of the channel acting as the master channel for a single transceiver bank or 2 adjacent banks.
Page 610 UG-01080 19-16 reserved_channel 2015.01.19 Options • Auto • Low • Medium • High Assign To PLL instance reserved_channel Pin Planner and Assignment Editor Name Parameter (Assignment Editor Only) Description Allows you to override the default channel placement of x8 variants. For the PHY IP Core for PCI Express...
Page 611 UG-01080 19-17 XCVR_RX_DC_GAIN 2015.01.19 assigns a value to . If you also XCVR_ANALOG_SETTINGS_PROTOCOL XCVR_RX_BYPASS_EQ_STAGES_234 assign a value to this parameter, a Quartus II Fitter error results as shown in the following example: Example 19-2: Error (21215) Error resolving parameter "pm_rx_sd_bypass_eqz_stages_234" value on instance "pci_interface_ddf2:u_pci_interface_2|...
Page 612 XCVR_RX_COMMON_MODE_VOLTAGE Pin Planner and Assignment Editor Name Receiver Buffer Common Mode Voltage Description Receiver buffer common-mode voltage. Note: Contact Altera for using this assignment. Related Information How to Contact Altera on page 21-42 XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE Pin Planner and Assignment Editor Name...
Page 613 UG-01080 19-19 XCVR_RX_SD_ENABLE 2015.01.19 Assign To Pin - RX serial data XCVR_RX_SD_ENABLE Pin Planner and Assignment Editor Name Receiver Signal Detection Unit Enable/Disable Description Enables or disables the receiver signal detection unit. During normal operation NORMAL_SD_ON=FALSE otherwise POWER_DOWN_SD=TRUE Used for the PCIe PIPE PHY, SATA and SAS protocols.
Page 614 XCVR_TX_COMMON_MODE_VOLTAGE Pin Planner and Assignment Editor Name Transmitter Common Mode Driver Voltage Description Transmitter common-mode driver voltage. Note: Contact Altera for using this assignment. Related Information How to Contact Altera on page 21-42 Analog Parameters Set Using QSF Assignments Altera Corporation...
Page 615 UG-01080 19-21 XCVR_TX_PRE_EMP_PRE_TAP_USER 2015.01.19 XCVR_TX_PRE_EMP_PRE_TAP_USER Pin Planner and Assignment Editor Name Transmitter Pre-emphasis Pre-Tap user Description Specifies the TX pre-emphasis pretap setting value, including inversion. Note: This parameter must be set in conjunction with XCVR_TX_VOD XCVR_TX_PRE_EMP_1ST_POST_TAP . All combinations of these settings are not legal. Refer to the XCVR_TX_PRE_EMP_2ND_POST_TAP Stratix V Device Datasheet for more information.
Page 616 UG-01080 19-22 XCVR_TX_PRE_EMP_2ND_POST_TAP 2015.01.19 Note: This parameter must be set in conjunction with XCVR_TX_VOD XCVR_TX_PRE_EMP_2ND_POST_TAP . All combinations of these settings are not legal. Refer to the Arria XCVR_TX_PRE_EMP_PRE_TAP V GZ Device Datasheet for more information. Options 0–31 Assign To...
Page 617 UG-01080 19-23 XCVR_TX_PRE_EMP_INV_PRE_TAP 2015.01.19 Assign To Pin - TX serial data Related Information Solution rd02262013_691 This solution provides the mapping of the Transceiver Toolkit pretap settings to the Quartus II transceiver QSF assignment. XCVR_TX_PRE_EMP_INV_PRE_TAP Pin Planner and Assignment Editor Name...
Page 618 UG-01080 19-24 XCVR_TX_RX_DET_ENABLE 2015.01.19 Related Information Arria V GZ Device Datasheet XCVR_TX_RX_DET_ENABLE Pin Planner and Assignment Editor Name Transmitter Receiver Detect Block Enable Description Enables or disables the receiver detector circuit at the transmitter. Options • TRUE • FALSE Assign To...
Page 619 UG-01080 19-25 XCVR_TX_VOD 2015.01.19 Assign To Pin - TX serial data XCVR_TX_VOD Pin Planner and Assignment Editor Name Transmitter Differential Output Voltage Description Differential output voltage setting. The values are monotonically increasing with the driver main tap current strength. Note: This parameter must be set in conjunction with...
Page 620: Analog Settings For Cyclone V Devices
Specifies the intended termination value for the specified refclk pin. The following 3 settings are available: • AC_COUPLING: Altera recommends this setting for all transceiver designs. Use it for AC coupled signals. This setting implements on-chip termination and on-chip signal biasing.
Page 621: Xcvr_Tx_Slew_Rate_Ctrl
UG-01080 19-27 XCVR_TX_SLEW_RATE_CTRL 2015.01.19 Assign To Pin - PLL refclk pin XCVR_TX_SLEW_RATE_CTRL Pin Planner and Assignment Editor Name Transmitter Slew Rate Control Description Specifies the slew rate of the output signal. The valid values span from the slowest rate to fastest rate with 1 representing the slowest rate.
Page 622 UG-01080 19-28 CDR_BANDWIDTH_PRESET 2015.01.19 CDR_BANDWIDTH_PRESET Pin Planner and Assignment Editor Name CDR Bandwidth Preset Description Specifies the CDR bandwidth preset setting Options • Auto • Low • Medium • High Assign To PLL instance PLL_BANDWIDTH_PRESET Pin Planner and Assignment Editor Name...
Page 623 UG-01080 19-29 XCVR_RX_DC_GAIN 2015.01.19 you cannot assign a value for any settings that this parameter controls. For example, for PCIe, the assigns a value to . If you also XCVR_ANALOG_SETTINGS_PROTOCOL XCVR_RX_BYPASS_EQ_STAGES_234 assign a value to this parameter, a Quartus II Fitter error results as shown in the following example: Example 19-3: Error (21215) Error resolving parameter "pm_rx_sd_bypass_eqz_stages_234"...
Page 624 XCVR_RX_COMMON_MODE_VOLTAGE Pin Planner and Assignment Editor Name Receiver Buffer Common Mode Voltage Description Receiver buffer common-mode voltage. Note: Contact Altera for using this assignment. Related Information How to Contact Altera on page 21-42 XCVR_RX_SD_ENABLE Pin Planner and Assignment Editor Name...
Page 625 UG-01080 19-31 XCVR_RX_SD_ON 2015.01.19 Description Number of parallel cycles to wait before the signal detect block declares loss of signal. Only used for the PCIe PIPE PHY, SATA, and SAS protocols. Options 0–29 Assign To Pin - RX serial data...
Page 626 XCVR_TX_COMMON_MODE_VOLTAGE Pin Planner and Assignment Editor Name Transmitter Common Mode Driver Voltage Description Transmitter common-mode driver voltage. Note: Contact Altera for using this assignment. Related Information How to Contact Altera on page 21-42 XCVR_TX_PRE_EMP_1ST_POST_TAP Pin Planner and Assignment Editor Name...
Page 627 UG-01080 19-33 XCVR_TX_RX_DET_ENABLE 2015.01.19 XCVR_TX_RX_DET_ENABLE Pin Planner and Assignment Editor Name Transmitter Receiver Detect Block Enable Description Enables or disables the receiver detector circuit at the transmitter. Options • TRUE • FALSE Assign To Pin - TX serial data XCVR_TX_RX_DET_MODE...
Page 628: Analog Settings For Stratix V Devices
UG-01080 19-34 XCVR_TX_VOD_PRE_EMP_CTRL_SRC 2015.01.19 XCVR_TX_VOD_PRE_EMP_CTRL_SRC Pin Planner and Assignment Editor Name Transmitter V Pre-emphasis Control Source Description When set to , the PCS block controls the V and pre-emphasis coefficients for PCI DYNAMIC_CTL Express. When this assignment is set to...
Page 629 Specifies the intended termination value for the specified refclk pin. The following 3 settings are available: • AC_COUPLING: Altera recommends this setting for all transceiver designs. Use it for AC coupled signals. This setting implements on-chip termination and on-chip signal biasing.
Page 630 UG-01080 19-36 XCVR_RX_BYPASS_EQ_STAGES_234 2015.01.19 Options • AC_COUPLING • DC_COUPLING_INTERNAL_100_OHMS • DC_COUPLING_EXTERNAL_RESISTOR Assign To Pin - PLL refclk pin XCVR_RX_BYPASS_EQ_STAGES_234 Pin Planner and Assignment Editor Name Receiver Equalizer Stage 2, 3, 4 Bypass Description Bypass continuous time equalizer stages 2, 3, and 4 to save power. This setting eliminates significant AC gain on the equalizer and is appropriate for chip-to-chip short range communication on a PCB.
Page 631 UG-01080 19-37 XCVR_VCCA_VOLTAGE 2015.01.19 Description Specifies the slew rate of the output signal. The valid values span from the slowest rate to fastest rate with 1 representing the slowest rate. Options 1–5 Assign To Pin - TX serial data XCVR_VCCA_VOLTAGE...
Page 632: Analog Settings Having Global Or Computed Default Values For Stratix V Devices
UG-01080 19-38 Analog Settings Having Global or Computed Default Values for Stratix V Devices 2015.01.19 Assign To Pin - TX & RX serial data Related Information Stratix V Device Datasheet Analog Settings Having Global or Computed Default Values for Stratix V Devices The following analog parameters have global or computed default values.
Page 633 UG-01080 19-39 PLL_BANDWIDTH_PRESET 2015.01.19 Example 19-4: Overriding Default Master Channel Example: set_parameter -name master_ch_number 4 -to "<design>:inst|altera_xcvr_native_sv:testx8_inst| sv_xcvr_native:gen_native_inst.xcvr_native_insts[0]. gen_bonded_group_native.xcvr_native_inst". Options 1, 4 Assign To Include in .qsf file Related Information Transceiver Configurations in Stratix V Devices Refer to Advance [SIC] Channel Placement Guidelines for PIPE Configurations in this document.
Page 634 UG-01080 19-40 XCVR_ANALOG_SETTINGS_PROTOCOL 2015.01.19 Description Allows you to override the default channel placement of x8 variants. For the PHY IP Core for PCI Express (PIPE), you can use this QSF assignment in conjunction with the assignment to master_ch_number specify channel 4 as the master channel. Available for Gen1, Gen2, and Gen3 variants.
Page 635 UG-01080 19-41 XCVR_GT_RX_DC_GAIN 2015.01.19 • BASIC • CEI • CPRI • INTERLAKEN • PCIE_GEN1 • PCIE_GEN2 • PCIE_GEN3 • QPI • SFIS • SONET • SRIO • TENG_1588 • TENG_BASER • TENG_SDI • XAUI Assign To Pin - TX and RX serial data...
Page 636 Pin Planner and Assignment Editor Name GT receiver Buffer Common Mode Voltage Description Receiver buffer common-mode voltage. This parameter is only for GT transceivers. Note: Contact Altera for using this assignment. Related Information How to Contact Altera on page 21-42...
Page 637 Pin Planner and Assignment Editor Name GT Transmitter Common Mode Driver Voltage Description Transmitter common-mode driver voltage. This parameter is only for GT transceivers. Note: Contact Altera for using this assignment. Related Information How to Contact Altera on page 21-42...
Page 638 UG-01080 19-44 XCVR_GT_TX_PRE_EMP_ PRE_TAP 2015.01.19 Options • ON • OFF Assign To Pin - TX serial data Related Information Stratix V Device Datasheet XCVR_GT_TX_PRE_EMP_ PRE_TAP Pin Planner and Assignment Editor Name GT Transmitter Preemphasis Pre-Tap Description Specifies the pre-tap pre-emphasis setting. This parameter is only for GT transceivers.
Page 639 UG-01080 19-45 XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE 2015.01.19 Description Receiver buffer common-mode voltage. Note: Contact Altera for using this assignment. Related Information How to Contact Altera on page 21-42 XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE Pin Planner and Assignment Editor Name Receiver Linear Equalizer Control (PCI Express) Description If enabled equalizer gain control is driven by the PCS block for PCI Express. If disabled equalizer gain...
Page 640 UG-01080 19-46 XCVR_RX_SD_OFF 2015.01.19 XCVR_RX_SD_OFF Pin Planner and Assignment Editor Name Receiver Cycle Count Before Signal Detect Block Declares Loss Of Signal Description Number of parallel cycles to wait before the signal detect block declares loss of signal. Only used for the PCIe PIPE PHY, SATA, and SAS protocols.
Page 641 XCVR_TX_COMMON_MODE_VOLTAGE Pin Planner and Assignment Editor Name Transmitter Common Mode Driver Voltage Description Transmitter common-mode driver voltage. Note: Contact Altera for using this assignment. Related Information How to Contact Altera on page 21-42 XCVR_TX_PRE_EMP_PRE_TAP_USER Pin Planner and Assignment Editor Name...
Page 642 UG-01080 19-48 XCVR_TX_PRE_EMP_2ND_POST_TAP_USER 2015.01.19 Related Information Solution rd02262013_691 • This solution provides the mapping of the Transceiver Toolkit pretap settings to the Quartus II transceiver QSF assignment. • Stratix V Device Datasheet XCVR_TX_PRE_EMP_2ND_POST_TAP_USER Pin Planner and Assignment Editor Name Transmitter Preemphasis Second Post-Tap user Description Specifies the transmitter pre-emphasis second post-tap setting value, including inversion.
Page 643 UG-01080 19-49 XCVR_TX_PRE_EMP_INV_2ND_TAP 2015.01.19 Description Specifies the second post-tap setting value. Note: This parameter must be set in conjunction with XCVR_TX_VOD XCVR_TX_PRE_EMP_1ST_POST_TAP . All combinations of these settings are not legal. Refer to the XCVR_TX_PRE_EMP_PRE_TAP Stratix V Device Datasheet for more information.
Page 644 UG-01080 19-50 XCVR_TX_PRE_EMP_PRE_TAP 2015.01.19 Description Inverts the transmitter pre-emphasis pretap. Specifies the TX pre-emphasis pretap setting value, including inversion. Options • TRUE • FALSE Assign To Pin - TX serial data Related Information Solution rd02262013_691 This solution provides the mapping of the Transceiver Toolkit pretap settings to the Quartus II transceiver QSF assignment.
Page 645 UG-01080 19-51 XCVR_TX_RX_DET_MODE 2015.01.19 Options • TRUE • FALSE Assign To Pin - TX serial data XCVR_TX_RX_DET_MODE Pin Planner and Assignment Editor Name Transmitter Receiver Detect Block Mode Description Sets the mode for receiver detect block. Options 0–15 Assign To...
Page 646 UG-01080 19-52 XCVR_TX_VOD_PRE_EMP_CTRL_SRC 2015.01.19 Description Differential output voltage setting. The values are monotonically increasing with the driver main tap current strength. Note: This parameter must be set in conjunction with XCVR_TX_PRE_EMP_1ST_POST_TAP , and . All combinations of these XCVR_TX_PRE_EMP_2ND_POST_TAP XCVR_TX_PRE_EMP_PRE_TAP settings are not legal.
Page 647: Migrating From Stratix Iv To Stratix V Devices Overview
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 648: Differences In Dynamic Reconfiguration For Stratix Iv And Stratix V Transceivers
Stratix IV to Stratix V devices. Stratix V devices that include transceivers must use the Altera Transceiver Reconfiguration Controller that contains the offset cancellation logic to compensate for variations due to PVT. Initially, each transceiver channel and each TX PLL has its own parallel, dynamic reconfiguration bus, named reconfig_from_xcvr[45:0] and reconfig_to_xcvr[69:0].
Page 649: Differences Between Xaui Phy Parameters For Stratix Iv And Stratix V Devices
UG-01080 20-3 Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices 2013.12.20 Stratix IV devices that include transceivers must use the ALTGX_RECONFIG IP Core to implement dynamic reconfiguration. The ALTGX_RECONFIG IP Core always includes the following two serial buses: •...
Page 650 UG-01080 20-4 Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices 2013.12.20 ALTGX Parameter Name (Default Value) XAUI PHY Parameter Name Comments Acceptable PPM threshold between receiver CDR VCO and receiver input reference clock (±1000) Analog power (Auto)
Page 651: Differences Between Xaui Phy Ports In Stratix Iv And Stratix V Devices
UG-01080 20-5 Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices 2013.12.20 Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices This section lists the differences between the top-level signals in Stratix IV GX and Stratix V GX/GS devices.
Page 652 UG-01080 20-6 Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices 2013.12.20 (20) Stratix IV GX Devices Stratix V Devices Signal Name Width Signal Name Width — Not available — cal_blk_powerdown [2<n> -1:0] [<n> *2 -1:0] rx_syncstatus rx_syncstatus [2<n>...
Page 653: Differences Between Phy Ip Core For Pcie Phy (Pipe) Parameters In Stratix Iv And Stratix V Devices
UG-01080 20-7 Differences Between PHY IP Core for PCIe PHY (PIPE) Parameters in Stratix IV and 2013.12.20 Stratix V Devices Differences Between PHY IP Core for PCIe PHY (PIPE) Parameters in Stratix IV and Stratix V Devices This section lists the PHY IP Core for PCI Express PHY (PIPE) parameters and the corresponding ALTGX megafunction parameters.
Page 654: Differences Between Phy Ip Core For Pcie Phy (Pipe) Ports For Stratix Iv And Stratix
UG-01080 20-8 Differences Between PHY IP Core for PCIe PHY (PIPE) Ports for Stratix IV and Stratix V 2013.12.20 Devices ALTGX Parameter Name (Default Value) CI Express PHY (PIPE) Comments Parameter Name Train receiver CDR from pll_inclk (false) TX PLL bandwidth mode (Auto) RX CDR bandwidth mode (Auto) Acceptable PPM threshold (±300)
Page 655 UG-01080 20-9 Differences Between PHY IP Core for PCIe PHY (PIPE) Ports for Stratix IV and Stratix V 2013.12.20 Devices Table 20-5: PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals (21) Stratix IV GX Device Signal Name...
Page 656 UG-01080 20-10 Differences Between PHY IP Core for PCIe PHY (PIPE) Ports for Stratix IV and Stratix V 2013.12.20 Devices (21) Stratix IV GX Device Signal Name Stratix V GX Device Signal Name Width [<n>-1:0] pipephydonestatus pipe_phystatus [3<n>-1:0] pipestatus pipe_rxstatus Non-PIPE Ports [<n>--1:0]...
Page 657: Differences Between Custom Phy Parameters For Stratix Iv And Stratix V Devices
UG-01080 20-11 Differences Between Custom PHY Parameters for Stratix IV and Stratix V Devices 2013.12.20 (21) Stratix IV GX Device Signal Name Stratix V GX Device Signal Name Width phy_mgmt_clk_reset phy_mgmt_clk [8:0] phy_mgmt_address Not available phy_mgmt_read [31:0] phy_mgmt_readdata phy_mgmt_write [31:0]...
Page 658 UG-01080 20-12 Differences Between Custom PHY Parameters for Stratix IV and Stratix V Devices 2013.12.20 ALTGX Parameter Name (Default Value) Custom PHY Parameter Name What is the deserializer block width? Deserializer block width: (22) Single Auto Double Single Double Additional Options...
Page 659: Differences Between Custom Phy Ports In Stratix Iv And Stratix V Devices
UG-01080 20-13 Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices 2013.12.20 Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices This section lists the differences between the top-level signals in Stratix IV GX and Stratix V GX/GS devices.
Page 660 UG-01080 20-14 Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices 2013.12.20 (23) ALTGX Custom PHY Width [<n>-1:0] rx_freqlocked rx_is_lockedtodata Transceiver Control and Status Signals — gxb_powerdown phy_mgmt_clk_reset — — rx_dataoutfull — — tx_dataoutfull There are both —...
Page 661 Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 662: Additional Information For The Transceiver Phy Ip Core
UG-01080 21-2 Additional Information for the Transceiver PHY IP Core 2015.01.19 Chapter Document Changes Made Version 1G/10Gbps Ethernet Made the following changes: PHY IP Core • Updated the chapter to indicate new IP instantiation flow using the IP Catalog. • Changed the device family support to final for this IP core in Table 5-2: Device Family Support.
Page 663 UG-01080 21-3 Additional Information for the Transceiver PHY IP Core 2015.01.19 Chapter Document Changes Made Version Custom PHY IP Core 2.7 Made the following changes: • Updated the chapter to indicate new IP instantiation flow using the IP Catalog. • Changed the device family support to final for this IP core in Table 9-1: Device Family Support.
Page 664 UG-01080 21-4 Additional Information for the Transceiver PHY IP Core 2015.01.19 Chapter Document Changes Made Version Stratix V Transceiver Made the following changes: Native PHY IP Core • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
Page 665 UG-01080 21-5 Additional Information for the Transceiver PHY IP Core 2015.01.19 Chapter Document Changes Made Version Arria V GZ Made the following changes: Transceiver Native • Updated the chapter to indicate new IP instantiation flow using PHY IP Core the IP Catalog.
Page 666: Revision History For Previous Releases Of The Transceiver Phy Ip Core
UG-01080 21-6 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Chapter Document Changes Made Version Transceiver PHY Made the following changes: Reset Controller IP • Updated the chapter to indicate new IP instantiation flow using Core the IP Catalog.
Page 667 UG-01080 21-7 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Chapter Document Changes Made Version Backplane Ethernet Made the following changes: 10GBASE-KR PHY • Corrected an error in the description of pcs_mode_rc[5:0] Table 4-17: Dynamic Reconfiguration Interface Signals. Added back the option for GigE data mode and 10G data mode with FEC.
Page 668 UG-01080 21-8 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Chapter Document Changes Made Version 1G/10GbE Ethernet Made the following changes: PHY IP Core • Corrected an error in the description of pcs_mode_rc[5:0] Table 5-15: Dynamic Reconfiguration Interface Signals. Added back the option for GigE data mode and 10G data mode with FEC.
Page 669 UG-01080 21-9 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Chapter Document Changes Made Version Deterministic Made the following changes: Latency PHY IP Core signal in Table 11-8: • Corrected the description of tx_datak Avalon-ST TX Interface.
Page 670 UG-01080 21-10 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Chapter Document Changes Made Version Arria V GZ Made the following changes: Transceiver Native • Removed the description for ports from PHY IP Core rx_clklow rx_fref Table 14-38: Native PHY Common Interfaces.
Page 671 UG-01080 21-11 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Chapter Document Changes Made Version Analog Parameters Made the following changes: Set Using QSF • Corrected values for Assignments XCVR_REFCLK_PIN_TERMINATION should be COUPLING_INTERNAL_100_OHM DC_COUPLING_ INTERNAL_100_OHMS • Removed the options for...
Page 672 UG-01080 21-12 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Chapter Document Changes Made Version 1G/10GbE Ethernet Made the following changes: PHY IP Core • Corrected definition of . This signal is synchronous gxmii_rx_d tx_clkout_1g • Added frequency for .
Page 673 UG-01080 21-13 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Chapter Document Changes Made Version Stratix V Transceiver Made the following changes: Native PHY IP Core • Corrected Figure 12-4 showing the 10G PCS datapath. This datapath does not include hard IP blocks to implement KR-FEC.
Page 674 UG-01080 21-14 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Chapter Document Changes Made Version Transceiver Reconfi‐ Made the following changes: guration Controller • Updated table for "Device Support for Dynamic Reconfigura‐ IP Core Overview tion" to indicate that Arria...
Page 675 UG-01080 21-15 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version 1G/10Gbps Ethernet PHY IP Core Backplane Ethernet Added descriptions of FEC-related bits: C2[8], CB[26:25]. 10GBASE-KR PHY IP Core PHY IP Core for PCI...
Page 676 UG-01080 21-16 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version Introduction April 2013 Update to introduction. Renamed heading "Additional Transceiver PHYs" to "Non-Protocol-Specific Transceiver PHYs." Getting Started April 2013 No changes from previous release.
Page 677 UG-01080 21-17 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version Transceiver Reconfiguration Controller April 2013 Rename table 16-13 to DFE Registers. Fix typo in Reconfig Addr column changed 7’h11 to 7’h19. In Table 16-8, removed the DCD Calibration registers row.
Page 678 UG-01080 21-18 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version March 2013 Made the following changes: • Improved the description of automatic speed detection. • Updated speed grade information. • Updated definition of...
Page 679 UG-01080 21-19 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version Stratix V Native PHY March 2013 Updated definition of User external TX PLL to include information on how to instantiate an external PLL.
Page 680 February 2013 • Reformatted. 10GBASE-R PHY February 2013 • Reformatted. • Corrected definition of the PLL type parameter. Altera recommends the ATX PLL for data rates greater than 8 Gbps. Backplane Ethernet 10GBASE-KR PHY February 2013 • Reformatted. • Removed description of PMA...
Page 681 UG-01080 21-21 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version February 2013 • Reformatted. • Corrected definition of . This signal is used and rx_data_ready indicates that the PCS is ready to receive data.
Page 682 UG-01080 21-22 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version February 2013 • Reformatted. • Removed QPI signals from Figure showing Arria V Native PHY Common Interfaces. These signals are not available for Arria V devices.
Page 683 UG-01080 21-23 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version November 2012 • Expanded discussion of the Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Native PHY IP Cores.
Page 684 UG-01080 21-24 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version November 2012 • Added Gen3 support. • Added Arria V GZ support. • Added ×2 support. • Added discussion of link equalization for Gen3.
Page 685 UG-01080 21-25 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version Arria V Transceiver Native PHY November 2012 • Added support for Standard datapath. • Added support for multiple PLLs. • Moved Analog Options to a separate chapter.
Page 686 UG-01080 21-26 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version November 2012 • Created separate chapter for analog parameters that were previously listed in the individual transceiver PHY chapters. • Changed default value for XCVR_GT_RX_COMMON_MODE_VOLTAGE to 0.65V.
Page 687 UG-01080 21-27 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version June 2012 • Added the following QSF settings to all transceiver PHY: XCVR_ TX_PRE_EMP_PRE_TAP_USER XCVR_TX_PRE_EMP_2ND_POST_TAP_ , and 11 new settings for GT transceivers.
Page 688 UG-01080 21-28 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version PHY IP Core for PCI Express (PIPE) June 2012 • Added the following QSF settings to all transceiver PHY: XCVR_ TX_PRE_EMP_PRE_TAP_USER XCVR_TX_PRE_EMP_2ND_POST_TAP_ , and 11 new settings for GT transceivers.
Page 689 UG-01080 21-29 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version June 2012 • Added the following QSF settings to all transceiver PHY: XCVR_ TX_PRE_EMP_PRE_TAP_USER XCVR_TX_PRE_EMP_2ND_POST_TAP_ , and 11 new settings for GT transceivers.
Page 690 UG-01080 21-30 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version June 2012 • DFE now automatically runs offset calibration and phase interpolator (PI) phase calibration at power on. • Added section explaining how to generate a reduced MIF file.
Page 691 UG-01080 21-31 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version Low Latency PHY February 2012 • Added register definitions for Low Latency PHY. Deterministic Latency PHY February 2012 • Removed register. The Deterministic pma_rx_signaldetect Latency PHY does not support this functionality.
Page 692 UG-01080 21-32 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version December 2011 • Changed definition of . This signal is phy_mgmt_clk_reset active high and level sensitive. Custom December 2011 • Added ×N and feedback compensation options for bonded clocks.
Page 693 UG-01080 21-33 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version December 2011 • Added duty cycle distortion (DCD) signal integrity feature. • Added PLL and channel reconfiguration using a memory initial‐...
Page 694 UG-01080 21-34 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version Interlaken Transceiver PHY November 2011 • Added signal which indicates that all lanes of TX tx_sync_done data are synchronized. • is required in this release.
Page 695 UG-01080 21-35 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version November 2011 • Added MIF support to allow transceiver reconfiguration from a .mif file that may contain updates to multiple settings.
Page 696 UG-01080 21-36 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version May 2011 • Added simulation section. • Revised Figure 1–1 on page 1–1 to show the Transceiver Reconfiguration Controller as a separately instantiated IP core.
Page 697 UG-01080 21-37 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version May 2011 • Added details about the 0 ready latency for tx_ready • Added PLL support to lane rate parameter description in Interlaken PHY General Options.
Page 698 UG-01080 21-38 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version May 2011 • Added presets for the 2.50 GIGE and 1.25GIGE protocols. • Moved dynamic reconfiguration for the transceiver outside of the Custom PHY IP Core.
Page 699 UG-01080 21-39 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version Migrating from Stratix IV to Stratix V May 2011 • Added discussion of dynamic reconfiguration for Stratix IV and Stratix V devices.
Page 700 UG-01080 21-40 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version December 2010 • • Added Stratix V support • Changed from 16 to 9 bits. phy_mgmt_address • Renamed management interface, adding phy_ prefix •...
Page 701 UG-01080 21-41 Revision History for Previous Releases of the Transceiver PHY IP Core 2015.01.19 Date Document Changes Made Version December 2010 • Added simulation support in ModelSim SE • Added PIPE low latency configuration option • Changed from 16 to 9 bits.
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