Altera PHY IP Core User Manual page 71

Chapter 5: Interlaken PHY IP Core
Parameter Settings
Table 5–4. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 2)
QSF Assignment Name
XCVR_VCCA_VOLTAGE
XCVR_VCCR_VCCT_VOLTAGE
Table 5–5
want to optimize some of these settings. In
bold type. For computed analog parameters, the default value listed is for the initial
setting, not the recomputed setting.
Table 5–5. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3)
QSF Assignment Name
CDR_BANDWIDTH_PRESET
PLL_BANDWIDTH_PRESET
XCVR_RX_DC_GAIN
March 2012 Altera Corporation
Pin Planner and
Assignment Editor
Name
Configure the VCCA_GXB voltage for a
GXB I/O pin by specifying the intended
VCCA_GXB voltage for a GXB I/O pin.
If you do not make this assignment the
compiler automatically sets the correct
VCCA_GXB Voltage VCCA_GXB voltage depending on the
configured data rate, as follows:
■
■
Configure the VCCR_GXB and
VCCT_GXB voltage for an GXB I/O pin
by specifying the intended supply
voltages for a GXB I/O pin. If your
design uses decision feedback
equalization (DFE) or adaptive
equalization (AEQ), you must set this
parameter to 1.0V.
VCCR_GXB
Otherwise, if you do not make this
VCCT_GXB Voltage
assignment the compiler
automatically sets the correct
VCCR_GXB and VCCT_GXB voltage
depending on the configured data rate
as follows:
■
■
lists the analog parameters with global or computed default values. You may
Pin Planner and
Assignment Editor
Name
Analog Parameters with Global Default Value
Specifies the CDR bandwidth preset
CDR Bandwidth Preset
setting.
Specifies the PLL bandwidth preset
PLL Bandwidth Preset
setting
Receiver Buffer DC Gain Controls the amount of a stage
Control receive-buffer DC gain.
Description
Data rate <= 6.5 Gbps: 2_5V
Data rate > 6.5 Gbps: 3_0V or
3_3V for Stratix V ES silicon
Data rate <= 6.5 Gbps: 0_85V
Data rate > 6.5 Gbps: 1_0V
Table 5–5, the default value is shown in
Description
5–5
Assign
Options
To
2_5V
Pin
3_0V
0_85V
Pin
1_0V
Options Assign To
Auto
Low PLL
Medium instance
High
Auto
Low PLL
Medium instance
High
0–4 Pin
Altera Transceiver PHY IP Core
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