Register Descriptions - Altera PHY IP Core User Manual

9–20
Table 9–17. Avalon-MM PHY Management Interface (Part 2 of 2)
Signal Name
phy_mgmt_read
phy_mgmt_waitrequest

Register Descriptions

Table 9–18
interface using word addresses and a 32-bit embedded processor. A single address
space provides access to all registers.
1
Writing to reserved or undefined register addresses may have undefined side effects.
Table 9–18. Deterministic Latency PHY IP Core Registers (Part 1 of 3)
Word
Bits R/W
Addr
0x021 [31:0] RW
0x022 [31:0] R
0x041 [31:0] RW
W
0x042 [1:0]
R
Altera Transceiver PHY IP Core
User Guide
Direction
Input Read signal.
When asserted, indicates that the Avalon-MM slave interface is
unable to respond to a read or write request. When asserted,
Output
control signals to the Avalon-MM slave interface must remain
constant.
specifies the registers that you can access over the PHY management
Register Name
PMA Common Control and Status Registers
cal_blk_powerdown
pma_tx_pll_is_locked
Reset Control Registers–Automatic Reset Controller
reset_ch_bitmask
reset_control (write)
reset_status(read)
Chapter 9: Deterministic Latency PHY IP Core
Description
Description
Writing a 1 to channel <n> powers down the calibration
block for channel <n>.
Bit[P] indicates that the TX CMU PLL (P) is locked to the
input reference clock. There is typically one
pma_tx_pll_is_locked bit per system.
Reset controller channel bitmask for digital resets. The
default value is all 1s. Channel <n> can be reset when
bit<n> = 1.
Writing a 1 to bit 0 initiates a TX digital reset using the reset
controller module. The reset affects channels enabled in the
reset_ch_bitmask. Writing a 1 to bit 1 initiates a RX
digital reset of channels enabled in the
reset_ch_bitmask.
Reading bit 0 returns the status of the reset controller TX
ready bit. Reading bit 1 returns the status of the reset
controller RX ready bit.
Interfaces
March 2012 Altera Corporation