Altera PHY IP Core User Manual page 105

Chapter 7: Custom PHY IP Core
Parameter Settings
Table 7–3. General Options (Part 3 of 3)
Name
Avalon data interfaces
Enable embedded reset control
Table 7–4
pma_rx_setlocktodata and pma_rx_set_locktoref registers. As
setting either pma_rx_setlocktodata or pma_rx_set_locktoref disables the automatic
reset controller.
Table 7–4. Reset Mode
rx_set_locktoref
March 2012 Altera Corporation
Value
When you turn this option On, the order of symbols is changed.
On/Off This option is typically required if you are planning to import your
Custom PHY IP core into a Qsys system.
When On, the automatic reset controller resets your design at
power up. When Off you can design you own reset logic using
tx_analogreset, rx_analogreset, tx_digitalreset,
rx_digitalreset, and pll_powerdown which are top-level ports
of the Custom Transceiver PHY. You must turn this option Off to
implement your own reset controller.
By default, the CDR circuitry is in automatic lock mode whether you
use the embedded reset controller or design your own reset logic.
You can switch the CDR to manual mode by writing the
On/Off
pma_rx_setlocktodata or
to 1. If either the pma_rx_set_locktodata and
pma_rx_set_locktoref is set, the CDR automatic lock mode is
disabled as
reset control and status registers, refer to
page 7–21.
For more information about reset in Stratix V devices, refer to
Transceiver Reset Control in Stratix V Devices
Stratix V Device Handbook.
shows the resulting reset controller mode for various combinations of the
rx_set_locktodata
1 0
X 1
0 0
Description
pma_rx_set_locktoref registers
Table 7–4 illustrates. For more information about the
CDR Lock Mode
Manual RX CDR locked to reference
Manual RX CDR locked to data
Automatic RX CDR
7–5
Table 7–21 on
in volume 3 of the
Table 7–4 indicates,
Altera Transceiver PHY IP Core
User Guide