Running A Simulation Testbench - Altera PHY IP Core User Manual

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Running a Simulation Testbench

When you generate your transceiver PHY IP core, the Quartus II software generates
the HDL files that define your parameterized IP core. In addition, the Quartus II
software generates an example Tcl script to compile and simulate your design in
ModelSim.
Figure 1–2. Directory Structure for Generated Files
Table 1–2
PHY IP core and the simulation environment which are in clear text.
Table 1–2. Generated Files (Part 1 of 2)
File Name
<project_dir>
<instance_name>.v or .vhd
<instance_name>.qip
<instance_name>.bsf
<project_dir>/<instance_name>/
<instance_name>_phy_assignments.qip
<project_dir>/<instance_name>_sim/
altera_xcvr_<PHY_IP_name>/
modelsim_example_script.tcl
Altera Transceiver PHY IP Core
User Guide
Figure 1–2 illustrates the directory structure for the generated files.
<project_dir>
<instance_name>.v or .vhd - the parameterized transceiver PHY IP core
<instance_name>.qip - lists all files used in the transceiver PHY IP design
<instance_name>.bsf - a block symbol file for you transceiver PHY IP core
<project_dir>/<instance_name> - includes PHY IP Verilog HDL and
SystemVerilog design files for synthesis
<instance_name>_sim/altera_xcvr<PHY_IP_name> - includes plain text
files that describe all necessary files required for a successful simulation. The
plain text files contain the names of all required files and the correct order
for reading these files into your simulation tool.
modelsim_example_script.tcl - this is an example file for compilation and
simulation of the transceiver PHY IP core
<instance_name>_sim/cadence -
Simulation files for Cadence simulation tools
<instance_name>_sim/mentor -
Simulation files for Mentor simulation tools
<instance_name>_sim/synopsys -
Simulation files for Synopsys simulation tools
describes the key files and directories for the parameterized transceiver
Description
The top-level project directory.
The top-level design file.
A list of all files necessary for Quartus II compilation.
A Block Symbol File (.bsf) for your transceiver PHY.
The directory that stores the HDL files that define the protocol-specific
PHY IP core. These files are used for synthesis.
Includes an example of the PLL_TYPE assignment statement required to
specify the PLL type for each PLL in the design. The available types are
clock multiplier unit (CMU) and auxiliary transmit (ATX).
The simulation directory.
The example Tcl script to compile and simulate the parameterized
transceiver PHY IP core. You must edit this script to include the following
information:
The simulation language
■
The top-level transceiver PHY variation name
■
The name of your testbench
■
Chapter 1: Introduction
Running a Simulation Testbench
March 2012 Altera Corporation