Page 1 Stratix GX Transceiver User Guide 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com UG-STXGX-3.0 P25-10021-02...
Page 2 Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U.S.
Page 3: Table Of Contents
SONET Mode ............................ 1–6 XAUI Mode ............................1–7 GigE Mode ............................1–8 Loopback ............................1–9 Built-In Self Test ..........................1–9 Chapter 2. Stratix GX Analog Description Introduction ............................2–1 Transmitter Analog ..........................2–2 Transmitter Buffer ..........................2–2 Transmitter PLL ..........................2–5 Serializer (Parallel-to-Serial Converter) ..................
Page 4 Contents Stratix GX Transceiver User Guide Byte Serializer ..........................3–17 8B/10B Encoder ..........................3–17 Basic Mode Clocking ........................... 3–20 Basic Mode Channel Clocking ...................... 3–20 Basic Mode Inter-Transceiver Block Clocking ................3–24 Basic Mode MegaWizard Plug-In ..................... 3–29 Basic Mode MegaWizard Plug-In Manager Considerations ........... 3–29 Basic Mode altgxb MegaWizard Options ...................
Page 5 Introduction ............................7–1 Serial Loopback ............................7–1 Parallel Loopback ..........................7–2 Reverse Serial Loopback ........................7–3 Chapter 8. Stratix GX Built-In Self Test (BIST) Introduction ............................8–1 Pattern Generator ..........................8–2 PRBS Mode Generator ........................8–2 Incremental Mode Generator ......................8–3 High-Frequency Mode Generator ....................
Page 6 Contents Stratix GX Transceiver User Guide Chapter 9. Reset Control & Power Down Introduction ............................9–1 Power On Reset (POR) .......................... 9–1 USER Reset & Enable Signals ......................9–1 Recommended Resets ........................... 9–4 Receiver & Transmitter Reset ......................9–4 Receiver Reset ..........................9–32 Transmitter Reset ...........................
Page 7: About This User Guide
How to Contact ® For the most up-to-date information about Altera products, go to the Altera world-wide web site at www.altera.com. For technical support on Altera this product, go to www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below.
Page 8: Typographic Conventions
Typographic Conventions Stratix GX Transceiver User Guide Typographic This document uses the typographic conventions shown below. Conventions Visual Cue Meaning Bold Type with Initial Command names, dialog box titles, checkbox options, and dialog box options are Capital Letters shown in bold, initial capital letters. Example: Save As dialog box.
Page 9: Chapter 1. Introduction
Gigabit Stratix GX devices are organized into four-channel blocks with four 3.1875 Gbps full-duplex channels per block and up to 20 channels (in five Transceiver blocks) per device. Each self-contained Stratix GX gigabit transceiver...
Page 10: Transceiver Block Architecture
You can divide the transceiver block into an analog section Architecture and a digital section, as shown in Figure 1–1. Figure 1–1. Block Diagram of a Stratix GX Gigabit Transceiver Block Analog Section Digital Section Word Deserializer Aligner...
Page 11: Digital Overview
Each transmitter PLL supports multiplication factors of 2, 4, 5, 8, 10, 16, or 20. Either external reference clocks or a variety of clock sources within the Stratix GX device drive the PLLs.
Page 12 The realignment function uses a barrel shifter and works with the pattern detector. Additionally, the word aligner has a manual data realignment mode that lets you control the data realignment in user mode without consistent alignment characters. 1–4 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 13: Modes Of Operation
An embedded channel aligner aligns byte boundaries across multiple channels and synchronizes the data entering the logic array from the gigabit transceiver block’s four channels. The Stratix GX channel aligner is optimized for a 10-Gigabit Ethernet XAUI 4-channel implementation. The channel aligner includes the control circuitry and channel alignment character detection defined by the XAUI protocol.
Page 14: Sonet Mode
Refer to the SONET Mode chapter for more details on the configurability of this mode. Figure 1–3 shows a block diagram of a duplex channel configured in SONET mode. 1–6 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 15: Xaui Mode
Receiver Transmitter XAUI Mode Stratix GX transceivers contain embedded macros dedicated to supporting the XAUI protocol, specified in clause 47 of the IEEE 802.3ae specification. These macros includes synchronization, channel deskew, rate matching, XGXS to XGMII, and XGMII to XGXS code-group conversion.
Page 16: Gige Mode
Receiver Transmitter GigE Mode Stratix GX devices in GigE mode can use the 8B/10B encoder/decoder, rate matcher, synchronizer, and byte serializer/deserializer built-in hard macros. Refer to the GigE Mode chapter for more information about this mode. The rate matcher and word aligner each have a dedicated state machine governing their functions.
Page 17: Loopback
Additionally, serial and parallel loopback paths let you test the FPGA logic without monitoring external signals. The reverse loopback path enables external system testing with minimal device interaction. Altera Corporation 1–9 January 2005 Stratix GX Transceiver User Guide...
Page 18 Modes of Operation 1–10 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 19: Chapter 2. Stratix Gx Analog Description
2. Stratix GX Analog Description Introduction This chapter describes how to serialize the parallel data for transmission and convert received data into parallel data. Data transmission and reception is performed by pseudo current mode logic (PCML) buffers. These transceiver buffers support programmable pre-emphasis, equalization, and programmable V settings in I/O buffers.
Page 20: Transmitter Analog
3.1875 gigabits per second (Gbps) and are capable of driving 40 inches of FR4 trace across two connectors. In addition, the buffer contains programmable output voltage, programmable pre-emphasis circuitry, and internal termination circuitry. 2–2 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 21 Stratix GX Analog Description Programmable Voltage Output Differential (V Stratix GX transceivers let you customize the differential output voltage ) to handle different length, backplane, and receiver requirements (see Figure 2–3). You can select the V (differential) from a range of 400...
Page 22 ISI effects from the transmission medium. In Stratix GX transceivers, the programmable pre-emphasis settings can have one of six values (0 to 5). You should experiment with the pre-emphasis values to determine the optimal setting based on your system variables.
Page 23 1,600-mV limit. Programmable Transmitter Termination The Stratix GX transmitter buffer includes a 100-, 120-, or 150-Ω programmable on-chip differential termination resistor. The Stratix GX transmitter buffers are current-mode drivers, so the resultant V is a function of the transmitter termination value.
Page 24 MHz reference clock is divided by 2, yielding a 311-MHz clock at the PFD. This 311-MHz reference clock is then multiplied by a factor of 8 to achieve the 2,488-MHz clock at the VCO. 2–6 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 25 (that is, the Stratix GX PLL driving a global clock that is used for the transmitter PLL reference clock source). Table 2–3. Multiplication Values as a Function of the Reference Clock...
Page 26 You can set the bandwidth for Stratix GX devices to either low or high. The –3-dB frequencies for these settings can vary due to the non-linear nature and frequency dependencies of the circuit.
Page 27: Receiver Analog
The internal termination in the receiver buffer can support AC and DC coupling with programmable differential termination settings of 100, 120, or 150 Ω.. Altera Corporation 2–9 January 2005 Stratix GX Transceiver User Guide...
Page 28 PLL to your design. If the pll_areset (analog reset) signal goes high, the RX_Vcm value is less than the 1.1 V. This value varies unpredictably because the circuit is tristated. RX_Vcm is referenced from the Stratix GX receiver analog power supply. 2–10...
Page 29 Transmission Line Enable Stratix GX-to-Stratix GX Receiver DC Coupling You can configure the Stratix GX receiver buffers so that DC-coupled Stratix GX-to-Stratix GX communication is possible. The Stratix GX transmitter’s common-mode is typically around 750 mV, while the receiver common mode by default is approximately 1.1 V. However, by enabling DC coupling, the receiver common mode is biased to allow interoperability with the Stratix GX transmitter.
Page 30: Receiver Pll
ISI effects from the transmission medium. In Stratix GX transceivers, the programmable equalizer settings can have one of five values (0 through four). You should experiment with the equalization values to determine the optimal setting based on your system variables.
Page 31 2 and then the /m factor compensates the frequency difference. For example, given a data rate of 2,488 Mbps with a reference clock of 622 MHz, the reference clock must be assigned to the REFCLKB port, Altera Corporation 2–13 January 2005 Stratix GX Transceiver User Guide...
Page 32 PLL where the clock is multiplied back up by a factor of 8 or 10, which results in total multiplication factor of 2. 2–14 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 33 (RX_CRUCLK) is directly fed from the source listed and does not factor any pre-clock synthesis (that is, a Stratix GX PLL driving a global clock used for the receiver PLL reference clock source). Table 2–5. Multiplication Values as a Function of the Reference Clock...
Page 34: Clock Recovery Unit
Clock Recovery Unit The CRU in each Stratix GX receiver channel recovers the clock from the serial data stream on RX_IN. You can set the CRU to automatically or manually alter the receiver PLL phase and frequency to match the bit transition on the incoming data stream.
Page 35 When the rx_locktorefclk[] signal is asserted, it forces the CRU PLL to lock to the reference clock (RX_CRUCLK). Asserting the rx_locktodata[] signal forces the CRU PLL to lock to data, whether Altera Corporation 2–17 January 2005 Stratix GX Transceiver User Guide...
Page 36 PLD logic array clock, the rx_rlv signal is asserted for more than two clock cycles in 8- or 10-bit data modes and three clock cycles in 16- or 20-bit data modes. 2–18 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 37: Deserializer (Serial-To-Parallel Converter)
8b10b, set the legal run length threshold values within the range of 5 to 160 UI in multiples of five. See the Stratix GX FPGA Family data sheet to verify the guaranteed maximum run length. Deserializer (Serial-to-Parallel Converter)
Page 38: Megawizard Analog Features
Invalid settings are automatically flagged to avoid illegal configurations. Although you can instantiate the Stratix GX block directly by calling out the altgxb megafunction, Altera recommends using the MegaWizard Plug-In Manager to instantiate your altgxb megafunction, reducing the likelihood of invalid settings.
Page 39 Selectable PPM difference tolerance {125, 250, 500, 1000} between the Receiver PLL VCO and the CRU clock: This is one of three parameters that affect the rx_freqlocked signal. If an out-of-tolerance event occurs, rx_freqlocked goes low. Altera Corporation 2–21 January 2005 Stratix GX Transceiver User Guide...
Page 40 Figure 2–14. MegaWizard Plug-In Manager - ALTGXB (Page 2 of 7) - General (2) Notes (1), Notes to Figure 2–14: For information, refer to the Loopback Modes chapter. For more information, refer to the Stratix GX Built-In Self Test (BIST) chapter. 2–22 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 41 In 8-bit or 16-bit mode, set the run length threshold from 4 to 124 in steps of 4. In 10-bit and 20-bit mode, or if using 8b10b, set the run length threshold from 5 to 160 in steps of 5. Altera Corporation 2–23 January 2005 Stratix GX Transceiver User Guide...
Page 42 Notes to Figure 2–16: Stratix GX to Stratix GX DC coupling only. Lets the receiver accept a 1.5-V PCML signal from a Stratix GX transmitter buffer. The Use equalizer control signal option enables dynamic equalization via the optional rx_equalizerctrl input port.
Page 43 The CRU PLL is within the prescribed PPM frequency threshold setting (125 PPM, 250 PPM, 500 PPM, 1,000 PPM) of the CRU reference clock. b. The reference clock and CRU PLL output are phase matched (~ phases are within 0.08 UI). Altera Corporation 2–25 January 2005 Stratix GX Transceiver User Guide...
Page 44 Plug-In Manager using the Select the preemphasis control setting. The valid values are 1 through 5, where 1 is the smallest pre-emphasis value and 5 is the largest. The amount of pre-emphasis is based on your V values. 2–26 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 45 Stratix GX Analog Description Figure 2–19. MegaWizard Plug-In Manager - ALTGXB (Page 7of 7) - Summary Altera Corporation 2–27 January 2005 Stratix GX Transceiver User Guide...
Page 46 MegaWizard Analog Features 2–28 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 47: Chapter 3. Basic Mode
Stratix GX devices. The basic mode includes SERDES and parallel interconnect functionality.
Page 48: Basic Mode Receiver Architecture
This feature eliminates the need to factor in receiver skew margins between the clock and data. However, with this clocking methodology, the word boundary of the re-timed data can be altered. Stratix GX devices offer an embedded 3–2 Altera Corporation...
Page 49 Figure 3–3 shows the various components of the word aligner in basic mode. The functionality is described in the following sections. Figure 3–3. Components in the Stratix GX Word Aligner Word Aligner Manual Pattern Alignment Mode...
Page 50 SONET is specified as the protocol. Table 3–1. Pattern Detector Comma Patterns in Basic Mode Pattern Detect Mode Data Width Disparity 10-bit 10-bits, 20-bits ± 7-bit 10-bits, 20-bits ± Two consecutive 8-bit characters 8-bits, 16-bits 3–4 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 51 Basic Mode Manual Alignment Modes The Stratix GX device supports manual alignment in 10-bit, 16-bit, and bit-slipping modes. Manual 10-Bit Alignment Mode You can configure the word aligner to align to a 10-bit word boundary if you use 8B/10B encoding or if you specify the data width to be either 10- or 20-bits wide.
Page 52 The comma is detected at time n+2, but it exists on a different boundary than the current locked boundary. Because the bit orientation of the Stratix GX device is LSB to MSB, it follows, from the waveform, that the comma exists across time n+2 and n+3.
Page 53 You must deassert and reassert the rx_enacdet signal to retrigger the word aligner. The next transition occurs at time n+5, where rx_enacdet is Altera Corporation 3–7 January 2005 Stratix GX Transceiver User Guide...
Page 54 This scheme is useful if the comma changes dynamically when the Stratix GX device is in user mode. Because the controller is implemented in the logic array, a custom controller can be built to dynamically change the comma without needing to reprogram the Stratix GX device.
Page 55: 8B/10B Decoder
MSB. The data received must come from the supported Dx.y or Kx.y list. All 8B/10B control signals (Disparity error, control detect, and code error) are pipelined with the data in the Stratix GX receiver block and are edge-aligned with the data.
Page 56 Kx.y list, the rx_errdetect signal goes high. This signal is aligned with the invalid code word that is received at the device logic array and/or the code word that triggered the disparity error. 3–10 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 57 K28.5 from the RD+ column was received. Based on the current running disparity at the end of time n+5, a positive disparity K28.5 code (from the RD-) column is expected at time n+5. Altera Corporation 3–11 January 2005 Stratix GX Transceiver User Guide...
Page 58 K28.5 code (BC + ctrl). The rx_ctrldetect=1'b1 is aligned with 8'hbc, indicating that it is a control code. Figure 3–10. Control Code Detection clock rx_out[7:0] rx_ctrldetect D3.4 D24.3 D28.5 K28.5 D15.0 D0.0 D31.5 D28.1 Code Group 3–12 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 59: Byte Deserializer
A (1010100000) is located in the MSB of the 20-bit output, and this is reflected with patterndetect [1] going high. The output of the byte deserializer is AX, CB, ED, and so on. Altera Corporation 3–13 January 2005 Stratix GX Transceiver User Guide...
Page 60 You must implement logic for byte position alignment, if necessary, once data enters the logic array, as seen in Figure 3–13. In this example, the byte position selection logic determines the proper byte position based on the pattern detect signal. 3–14 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 61: Receiver Phase Compensation Fifo Buffer
The clock that feeds the RX_CORECLK must be derived from the RX_CLKOUT of its associated receiver channel. The receiver phase compensation FIFO buffer can only account for phase differences. Altera Corporation 3–15 January 2005 Stratix GX Transceiver User Guide...
Page 62: Basic Mode Transmitter Architecture
In this case, you must ensure that there is no frequency difference between the TX_CORECLK and the Transmitter PLL clock. The transmitter phase compensation FIFO buffer can only account for phase differences. 3–16 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 63: Byte Serializer
For the input of D1, the output is D1LSB and then D1MSB. 8B/10B Encoder The 8B/10B encoder is part of the Stratix GX transceiver block. The purpose of the 8B/10B encoder is to translate 8-bit data and a 1-bit control identifier (via tx_ctrlenable) into a 10-bit DC-balanced data stream.
Page 64 If the reset for the 8B/10B encoder is asserted, the 8B/10B decoder receiving the data might receive an invalid code error, sync error, control detect, and/or disparity error while txdigitalreset is high. 3–18 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 65 12 valid control code-groups. If an invalid control code is entered, the resulting 10-bit code might also be invalid (might not map to a valid Dx.y or Kx.y code), depending on the value entered. Altera Corporation 3–19 January 2005 Stratix GX Transceiver User Guide...
Page 66: Basic Mode Clocking
CRU, which is rx_clkout. This recovered clock is also fed into the device so that in a multi-crystal environment, some level of clock domain decoupling can be implemented to interface with a system clock. 3–20 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 67 This separation is required if the output reference clock frequency from the transmitter PLL exceeds the 325-MHz phase frequency detector of the receiver PLL. For more information on this feature, refer to the Stratix GX Analog Description chapter. This configuration is shown in Figure 3–20.
Page 68 The rx_coreclk and tx_coreclk must be frequency matched with their respective read and write ports. Figure 3–21 shows the clock configuration with these optional input ports enabled. 3–22 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 69 Output Output clock from transmitter PLL equivalent to coreclk_out . Available as port if transmitter PLL is TX_PLL_CLK used. Output Output clock from transceiver. In this mode, rx_clkout is the recovered clock of the respective RX_CLKOUT channel. Altera Corporation 3–23 January 2005 Stratix GX Transceiver User Guide...
Page 70: Basic Mode Inter-Transceiver Block Clocking
MegaWizard Plug-In Manager’s built-in functions. Support for the number of channels offered varies depending on which Stratix GX device is selected. Because of the various configurations of input and output clocks, you must carefully consider the clocking schemes between transceiver blocks to prevent pitfalls later in the design cycle.
Page 71 In a multi transceiver block configuration, this routing can lead to timing violations because the coreclk_out per transceiver block cannot guarantee phase relationship. Therefore, the TX_CORECLK with a common clock is recommended for synchronous transmission. Altera Corporation 3–25 January 2005 Stratix GX Transceiver User Guide...
Page 72 Each transceiver block is able to share a common reference clock through the inter-transceiver lines. You can reduce the Stratix GX logic array clock usage by using the inter- transceiver lines. The inter-transceiver lines are used when a REFCLKB input port from one transceiver block or channel drives any other transceiver blocks or channels.
Page 73 Global Clocks, I/O Bus, General Routing refclkb Global Clocks, I/O Bus, General Routing Receiver PLLs Transceiver Block 3 Transmitter Global Clocks, I/O Bus, General Routing refclkb Global Clocks, I/O Bus, General Routing Receiver PLLs Altera Corporation 3–27 January 2005 Stratix GX Transceiver User Guide...
Page 74: Basic Mode Clocking
TX PLL refclkb Global Clks, I/O Bus, Gen Routing Receiver PLLs Transceiver Block 3 Global Clks, I/O Bus, Gen Routing TX PLL refclkb Global Clks, I/O Bus, Gen Routing Receiver PLLs 3–28 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 75: Basic Mode Megawizard Plug-In
Basic Mode Basic Mode Altera recommends that the Stratix GX transceiver block be instantiated and parameterized through the altgxb megafunction in the MegaWizard MegaWizard Plug-In Manager. The MegaWizard Plug-In Manager offers a graphical user interface (GUI) that organizes the altgxb options into Plug-In easy-to-use sections.
Page 76 16 bits is double width. Without 8B/10B, 8 bits is single width, 16 bits is double width, 10 bits is single width, and 20 bits is double width. Refer to the Stratix GX Analog Description chapter for more information. The rxdigitalreset port resets the digital blocks in the receiver channel. Each active receiver channel has its own digital reset.
Page 77 Figure 3–26. MegaWizard Plug-In Manager - ALTGXB (Page 4 of 9) - General (2) Notes (1), Notes to Figure 3–26: For more information, refer to the Loopback Modes chapter. For more information, refer to the Stratix GX Built-In Self Test (BIST) chapter. Altera Corporation 3–31 January 2005 Stratix GX Transceiver User Guide...
Page 78 You can enable or disable 8B/10B. With 8B/10B active, data width must be 8-bits or 16-bits. For more information, refer to the Stratix GX Analog Description chapter. rx_enacdet: supports word aligner to byte align to the word alignment pattern. When rx_enacdet is held high, the word aligner aligns to the byte boundary, if the comma is detected.
Page 79 Figure 3–28: For more information, refer to the Stratix GX Analog Description chapter. Data rate versus input clock frequency must adhere to the set multiplication factor of 2, 4, 5, 8, 10, 16, 20 of the input clock. Multiplication factors of 2, 4, 5 must use the dedicated refclkb pins.
Page 80 Notes to Figure 3–29: For more information, refer to the Stratix GX Analog Description chapter. The rx_clkout signal is a recovered clock output from individual receiver channels. One rx_clkout signal is available per channel. The rx_locked signal is an active low signal that indicates that the receiver PLL is phase locked to the reference clock.
Page 81 Figure 3–30. MegaWizard Plug-In Manager - ALTGXB (Page 8 of 9) - Transmitter Note (1) Notes to Figure 3–30: For more information, refer to the Stratix GX Analog Description chapter. Altera Corporation 3–35 January 2005 Stratix GX Transceiver User Guide...
Page 82 Basic Mode MegaWizard Plug-In Figure 3–31. MegaWizard Plug-In Manager - ALTGXB (Page 9 of 9) - Summary 3–36 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 83: Chapter 4. Sonet Mode
Serial data rate range from 614 Mbps to 3.1875 Gbps (non-encoded) ■ Input reference clock range from 38.375 to 650 MHz ■ Supports parallel interface width of 8 or 16 bits ■ Word aligner supports 16-bit or bit-slip mode Altera Corporation 4–1 January 2005...
Page 84: Sonet Mode Receiver Architecture
This feature eliminates the need to factor in receiver skew margins between the clock and data. However, with this clocking methodology, the word boundary of the re-timed data can be altered. Stratix GX transceivers offer an 4–2 Altera Corporation...
Page 85 Figure 4–3 shows the various components of the word aligner in SONET mode. The functionality is described in the following sections. Figure 4–3. Stratix GX Word Aligner Components Word Aligner Pattern Manual Detector Alignment Mode...
Page 86 The value of the signal is forwarded to the device, along with the byte that was in the word aligner when the rx_a1a2size[] signal was sampled. 4–4 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 87 SONET alignment mode for an A1A2 pattern. In this example, a SONET A1A2 Framing pattern is used (16'b0001010001101111). In this case, the A1 is represented by 8'b01101111, and A2 is represented by 8'b00010100. Altera Corporation 4–5 January 2005 Stratix GX Transceiver User Guide...
Page 88 Each time a bit is slipped, the bit that arrived at the receiver earlier is skipped. When the word boundary matches what is specified as the 4–6 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 89 This scheme is useful if the comma changes dynamically when the Stratix GX device is in user mode. Because the controller is implemented in the logic array, a custom controller can be built to dynamically change the comma without needing to reprogram the Stratix GX device. The pattern detect circuitry matches only the pattern that is specified in the MegaWizard Plug-In Manager and is not dynamically adjustable.
Page 90: Byte Deserializer
MSB transmitted first option. Figure 4–6. Receiver Byte Deserializer in 8/16-Bit Mode With Finishing Alignment Pattern in MSB inclk data_in[7..0] 01101111 00010100 11000110 11110001 10101010 11001100 data_out[15..0] xxxxxxxxxxxxxxxxxxxx 0001010001101111 1111000111000110 patterndetect[0] patterndetect[1] 4–8 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 91 Figure 4–8. In this example, the byte position selection logic determines the proper byte position based on the pattern detect signal. Altera Corporation 4–9 January 2005 Stratix GX Transceiver User Guide...
Page 92: Receiver Phase Compensation Fifo Module
FIFO module, clocked by rx_coreclk, is fed by rx_clkout. An FPGA global clock, regional clock, or fast regional clock resource is required to make the connection 4–10 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 93: Sonet Mode Transmitter Architecture
This connection occurs using the logic array routing. In this case, the software defaults to using an FPGA global clock, regional clock, or fast regional clock resource. Altera Corporation 4–11 January 2005 Stratix GX Transceiver User Guide...
Page 94: Byte Serializer
This section covers describes the internal clocking and the external clocks of the transceiver in SONET mode. By default, the MegaWizard Plug-In Manager parameterizes the altgxb megafunction with the clock configuration shown in Figure 4–11. 4–12 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 95 PLL and allows for the separation of receiver and transmitter reference clocks. This separation is required if the output reference clock frequency from the transmitter PLL exceeds the 325 MHz phase Altera Corporation 4–13 January 2005 Stratix GX Transceiver User Guide...
Page 96 SONET Mode Clocking frequency detector of the receiver PLL. For more information on this feature, refer to the Stratix GX Analog Description chapter. This configuration is shown in Figure 4–12. If double width is used (16-bit bus) and the data rate is above 2,600 Mbps,...
Page 97 SONET Mode The coreclk_out is the output from the transmitter PLL. A ® coreclk_out is available for each transceiver block that is used. Altera recommends clocking the logic that is feeding the transmitter with this clock. The read clock of the receiver phase compensation FIFO module and the write clock of the transmitter phase compensation FIFO module are optionally enabled to manually feed in a clock from the FPGA logic array.
Page 98 PLL, available as a port when the transmitter PLL is instantiated. Output Output clock from the coreclk_out transmitter PLL equivalent to . Available TX_PLL_CLK as a port if the transmitter PLL is used. 4–16 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 99: Sonet Mode Inter-Transceiver Block Clocking
Quartus II MegaWizard Plug-In Manager’s built-in functions. The number of supported channels varies based on which Stratix GX device you select. Because of the various configurations of input and output clocks, consider the clocking schemes between inter-transceiver blocks carefully to prevent problems later in the design cycle.
Page 100 SONET Mode Clocking One of the clocking interfaces to consider while designing with Stratix GX devices is the transceiver-to-FPGA interface. This clocking scheme is further classified as the FPGA-to-transmitter channel and the FPGA-to-receiver channel to the PLD. In SONET mode, the read port of the transmitter phase compensation FIFO module is either clocked by the coreclk_out or by the tx_coreclk signal.
Page 101 Another inter-transceiver block consideration is the selection of the dedicated refclkb pin. Stratix GX channels are arranged in banks of four, or transceiver blocks. Each transceiver block has the ability to share a common reference clock through the inter-transceiver (IQ) lines. The Altera Corporation 4–19...
Page 102 SONET Mode Clocking Stratix GX logic array clock usage can be reduced by using the IQ lines. The IQ lines are used when a refclkb input port from one transceiver block or channel drives any other transceiver blocks or channels. The Quartus II software automatically determines the IQ line usage.
Page 103 Global Clocks, I/O Bus, General Routing refclkb Global Clocks, I/O Bus, General Routing Receiver PLLs Transceiver Block 3 Transmitter Global Clocks, I/O Bus, General Routing refclkb Global Clocks, I/O Bus, General Routing Receiver PLLs Altera Corporation 4–21 January 2005 Stratix GX Transceiver User Guide...
Page 104 Global Clks, I/O Bus, Gen Routing refclkb Global Clks, I/O Bus, Gen Routing Receiver PLLs Transceiver Block 3 Transmitter Global Clks, I/O Bus, Gen Routing refclkb Global Clks, I/O Bus, Gen Routing Receiver PLLs 4–22 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 105: Sonet Mode Megawizard Plug-In Manager
Manager to help prevent illegal configurations. The MegaWizard Plug-In Manager also grays out any options that do not apply to SONET mode. Although you can instantiate the Stratix GX block directly by calling out the altgxb megafunction, Altera recommends using the MegaWizard Plug-In Manager to instantiate the altgxb megafunction to reduce the chance of invalid settings.
Page 106 8 bits is single width and 16 bits is double width. Refer to the Stratix GX Analog Description chapter for more information. The rxdigitalreset port resets the digital blocks in the receiver channel. Each active receiver channel contains its own digital reset.
Page 107 Figure 4–18. MegaWizard Plug-In Manager - ALTGXB (Page 4 of 9) - General (2) Notes (1), Notes to Figure 4–18: For more information, refer to the Loopback Modes chapter. For more information, refer to the Stratix GX Built-In Self Test (BIST) chapter. Altera Corporation 4–25 January 2005 Stratix GX Transceiver User Guide...
Page 108 Figure 4–19: For more information, refer to the Stratix GX Analog Description chapter. The rx_enacdet port lets the word aligner byte align to the word alignment pattern (active high synchronous signal). The signal must go low then high to trigger word re-alignment. If this option is de-selected, the word aligner is not active, but the pattern detect signal is still functional.
Page 109 SONET mode. For more information, refer to the Stratix GX Analog Description chapter. SONET data rate is set at 2488.32 Mbps by default. Other data rates are possible, but they must adhere to the set refclkb multiplication factor of 2, 4, 5, 8, 10, 16, 20 of the input clock.
Page 110 4–21: Indicates to the word aligner to either align to an A1A2 or A1A1A2A2 pattern. Low = A1A2, High = A1A1A2A2. For more information, refer to the Stratix GX Analog Description chapter. Transmitter PLL and receiver PLL lock indicator. For...
Page 111 The low byte is still transmitted first. This feature is used in conjunction with receiver and word aligner bit-flip in SONET mode. For more information, refer to the Stratix GX Analog Description chapter. Altera Corporation 4–29...
Page 112 SONET Mode MegaWizard Plug-In Manager Figure 4–23. MegaWizard Plug-In Manager - ALTGXB (Page 9 of 9) - Summary 4–30 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 113: Chapter 5. Xaui Mode
8B/10B encoder and decoder ■ Word aligner supports 10-bit code-group ■ Channel deskew ■ Rate compensation or elastic buffer ■ XGMII-to -PCS code conversion on transmit ■ PCS-to -XGMII code conversion on receive ■ Byte deserializer Altera Corporation 5–1 January 2005...
Page 114 3.125 Gbps. At the XAUI receiver, the incoming data is decoded and mapped back to the 32 bit XGMII format. This process provides a transparent extension of the physical reach of the XGMII and also reduces the interface pin count. 5–2 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 115 XGMII characters to the PCS code-groups used in XAUI. The idle characters are mapped to a pseudorandom sequence of ||A||, ||R||, and ||K|| code-groups. Altera Corporation 5–3 January 2005 Stratix GX Transceiver User Guide...
Page 116 This section describes the supported digital architecture, clocking schemes, and software implementation of the XAUI mode. Figure 5–3 shows a block diagram of a duplex channel configured in XAUI mode. 5–4 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 117: Xaui Mode Receiver Architecture
Figure 5–4. Block diagram of Receiver Digital Components in XAUI Mode Analog Section Digital Section Deserializer Word Aligner Clock Channel Recovery Unit Phase Rate Aligner Compensation 8B/10B Matcher Byte FIFO Buffer Decoder Serializer Reference Receiver Clock Receiver Altera Corporation 5–5 January 2005 Stratix GX Transceiver User Guide...
Page 118: Word Aligner
However, with this clocking methodology, the word boundary of the re-timed data can be altered. Stratix GX transceivers offer an embedded word alignment circuit that can be used in conjunction with the pattern detector to align the word boundary of the re-timed data to a specified comma.
Page 119 Invalid code-groups are not supported during the synchronization stage. XAUI Synchronization Mode When a Stratix GX transceiver is configured to the XAUI protocol, the built-in pattern detector, word aligner, and XAUI state machines adhere to the PCS synchronization specification. The code-group synchronization is achieved upon the reception of four /K28.5/ commas.
Page 120 Figure 5–6. IEEE 802.3ae PCS Synchronization State Diagram Note to Figure 5–6: lane_sync_status<n> signal_detect<n> , and signal_detectCHANGE<n> refer to the number of the received lane n where n = 0 to 3. 5–8 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 121: Channel Aligner
/A/ code-group to deskew the channels. Figure 5–7. Example of Lane Skew at Receiver Input Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3 Altera Corporation 5–9 January 2005 Stratix GX Transceiver User Guide...
Page 122 XAUI Mode Receiver Architecture Figure 5–8. IEEE802.3ae PCS Deskew State Diagram 5–10 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 123: Rate Matcher
IPG or idle conditions. This circuitry compensates for ±100 ppm frequency variations. 8B/10B Decoder The 8B/10B decoder is part of the Stratix GX transceiver blocks. The purpose of the 8B/10B decoder is to restore the 8-bit data + 1-bit control identifier from the 10-bit code.
Page 124 MSB. The data that is received must be from the supported Dx.y or Kx.y list. All 8B/10B control signals (disparity error, control detect, and code error) are pipelined with the data in the Stratix GX receiver block and are edge-aligned with the data.
Page 125 K28.5 from the RD+ column was received. Based on the current running disparity at the end of time n+5, a positive disparity K28.5 code (from the RD-) column is expected at time n+5. Altera Corporation 5–13 January 2005 Stratix GX Transceiver User Guide...
Page 126 8'hbc, which indicates that this code is a control code. The reset of the code received is data. Figure 5–11. Control Code Detection clock rx_out[7:0] rx_ctrldetect D3.4 D24.3 D28.5 K28.5 D15.0 D0.0 D31.5 D28.1 Code Group 5–14 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 127: Pcs - Xgmii Code Conversion
XAUI Mode PCS - XGMII Code Conversion In XAUI mode, the 8b/10b decoder in Stratix GX transceivers is controlled by a global receiver state machine that maps various PCS code-groups into specific 8-bit XGMII codes. Table 5–3 lists the PCS code group to XGMII character mapping.
Page 128 LSB of the 16-bit output. Correspondingly, patterndetect[0] goes high. In this case, the output is BA, DC, FE, and so on. 5–16 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 129 Figure 5–14. Receiver Byte Deserializer Data Recovery in Logic Array Gigabit Transceiver Block Logic Array rx_out_post[17..10] rx_out[17..10] rx_out_post[17..0] rx_out_align[17..0] Phase Compensation FIFO {rx_out[7..0], rx_out_post[17..10]} Buffer rx_out_post[7..0] rx_out[7..0] Byte Boundary Selection Logic Altera Corporation 5–17 January 2005 Stratix GX Transceiver User Guide...
Page 130: Receiver Phase Compensation Fifo Module
The read port of the phase compensation FIFO module is clocked by the transmitter PLL clock. The write clock is clocked by tx_coreclk. You can select the tx_coreclk as an optional transmitter input port to 5–18 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 131: Byte Serializer
The LSB is transmitted before the MSB in the transmitter byte serializer. Figure 5–16 shows the order of data transmitted. For the input of D1, the output is D1LSB and then D1MSB. Altera Corporation 5–19 January 2005 Stratix GX Transceiver User Guide...
Page 132: Xgmii Character To Pcs Code-Group Mapping
XAUI Mode Transmitter Architecture XGMII Character to PCS Code-Group Mapping In XAUI mode, the 8b/10b encoder in the Stratix GX transceiver is controlled by a global transmitter state machine that maps various 8-bit XGMII codes to 10-bit PCS code-groups. This state machine complies with the IEEE 802.3ae PCS transmit specification.
Page 133: 8B/10B Encoder
Values in TXD column are in hexadecimal. 8B/10B Encoder The 8B/10B encoder is part of the Stratix GX transceiver blocks. The purpose of the 8B/10B encoder is to translate 8-bit data and a 1-bit control identifier (via tx_ctrlenable) into a 10-bit DC balanced data stream.
Page 134 (10'hxxx) until the first of three K28.5 is sent (Figure 5–19 shows three don’t-cares). Normal user data follows the third K28.5. 5–22 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 135 10-bit code might be encoded as an invalid code, which does not map to a valid Dx.y or Kx.y code), or a valid Dx.y code, depending on the value entered. Altera Corporation 5–23 January 2005 Stratix GX Transceiver User Guide...
Page 136: Xaui Mode Clocking
D24.6+ (0xD8 from the RD+ column). An 8B/10B decoder decodes this value incorrectly (based on the 8B/10B Fibre Channel specification). XAUI Mode This section describes the clocking supported by the Stratix GX device in XAUI mode. Clocking XAUI Mode Channel Clocking This section describes clocking of the transceiver, internal clocking details, and external clock ports in XAUI mode.
Page 137 Chapter 2, Stratix GX Analog Description for more information). This configuration is shown in Figure 5–22. Refer to the Stratix GX FPGA Family data sheet for information on parallel interface speeds for other device speed grades. Altera Corporation 5–25 January 2005...
Page 138 FIFO module on the transmit side. 5–26 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 139 . If not available as a port, is tx_pll_clk fed by through logic array routing. coreclk_out Output Output clock from the transmitter PLL equivalent to coreclk_out tx_pll_clk Available as port if the transmitter PLL is used. Altera Corporation 5–27 January 2005 Stratix GX Transceiver User Guide...
Page 140: Xaui Inter-Transceiver Block Clocking
XAUI mode is transceiver-block-based and can only support lanes in multiples of four. One of the clocking interfaces in the Stratix GX device is the interface between the transceiver and the FPGA, which can be further divided into FPGA-transmit of a transceiver and FPGA-receive of a transceiver. In...
Page 141 PLL output clock, which is a transceiver internal clock. Altera recommends implementing channel bonding across the transceiver blocks used in Stratix GX devices to ensure that there is no skew between the transceiver blocks (if each transceiver is operating, no...
Page 142 In a multi-transceiver block situation, data striping across the channels is common. Skew introduced between transceiver blocks by passive and active elements of the link must be de-skewed in the PLD core (channel alignment) to ensure error-free data. 5–30 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 143 Each transceiver block has the ability to share a common reference clock through the Inter-Transceiver (IQ) lines. You can reduce the Stratix GX logic array clock usage by using the IQ lines. The IQ lines are used when a refclkb input port from one transceiver block or channel drives any other transceiver blocks or channels.
Page 144: Xaui Mode Clocking
It is important to use this information when placing refclkb pins. (When placing refclkb pins, see Appendix C, REFCLKB Pin Constraints for information about analog reads and refclkb pin usage constraints.) 5–32 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 145 Global Clks, I/O Bus, Gen Routing refclkb Global Clks, I/O Bus, Gen Routing Receiver PLLs Transceiver Block 3 TX PLL Global Clks, I/O Bus, Gen Routing refclkb Global Clks, I/O Bus, Gen Routing Receiver PLLs Altera Corporation 5–33 January 2005 Stratix GX Transceiver User Guide...
Page 146: Xaui Mode Megawizard Plug-In Manager
MegaWizard Plug-In Manager grays out any options that do not apply to XAUI mode. Although it is possible to instantiate the Stratix GX block directly by calling out the altgxb megafunction, Altera recommends using the MegaWizard Plug-In Manager to instantiate the altgxb megafunction to reduce the chance of invalid settings.
Page 147 You can select between 4 and the maximum number of channels available on the device in increments of 4. 16 bits is double width. For more information, refer to the Stratix GX Analog Description chapter. The rxdigitalreset port resets the digital blocks in the receiver channel. Each active receiver channel has its own digital reset.
Page 148 Figure 5–29. MegaWizard Plug-In Manager - ALTGXB (Page 4 of 9) - General (2) Notes (1), Notes to Figure 5–29: For more information, refer to the Loopback Modes chapter. For more information, refer to the Stratix GX Built-In Self Test (BIST) chapter. 5–36 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 149 Notes (1), Notes to Figure 5–30: For more information, refer to the Stratix GX Analog Description chapter. Word aligner in XAUI mode is always set as a 10-bit K28.5 pattern. Both positive and negative disparities are checked. Altera Corporation 5–37...
Page 150 For more information, refer to the Stratix GX Analog Description chapter. For more information, refer to the Stratix GX Analog Description chapter. The Force Signal Detect option is always on and cannot be turned off. Because the signal detect circuitry is always forced, the rx_signaldetect is always set in XAUI mode.
Page 151 XAUI mode. Because the signal detect circuitry is always forced, the rx_signaldetect signal is always set in XAUI and GIGE modes, supporting backward compatibility with existing designs. See the Stratix GX Analog Description chapter for additional information. Indicates when the word aligner has aligned to the byte boundary. The...
Page 152 Figure 5–33: For more information, refer to the Stratix GX Analog Description chapter. tx_coreclk: You can optionally choose the write clock of the transmitter phase comp FIFO buffer. This clock should be frequency locked with the internal reference clock because the phase comp FIFO buffer cannot tolerate frequency variations and contains no error flags.
Page 153 XAUI Mode Figure 5–34. MegaWizard Plug-In Manager - ALTGXB (Page 9 of 9) - Summary Altera Corporation 5–41 January 2005 Stratix GX Transceiver User Guide...
Page 154 XAUI Mode MegaWizard Plug-In Manager 5–42 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 155: Chapter 6. Gige Mode
® The Gigabit Ethernet (GigE) mode in Stratix GX devices supports a subset of the IEEE GigE standard. Stratix GX devices have Physical Coding Sub-layer (PCS) functions and Physical Medium Attachment (PMA) functions as Hard Intellectual Property (IP). Stratix GX devices provide the following GigE features: ■...
Page 156 Data Link Physical Medium Stratix GX devices are used for the PCS and the PMA layers of the GigE physical layer. Stratix GX devices in GigE mode use built-in hard macros for the 8B/10B encoder/decoder, rate matcher, synchronizer, or the byte serializer/deserializer.
Page 157 Rate Compensation Aligner 8B/10B Clock Matcher FIFO Buffer Byte Decoder Recovery Deserializer Unit Reference Receiver Clock Transmitter Reference Clock Serializer Phase Byte Compensation 8B/10B Serializer FIFO Buffer Encoder Receiver Transmitter Altera Corporation 6–3 January 2005 Stratix GX Transceiver User Guide...
Page 158: Word Aligner
Figure 6–3 shows the digital components of the Stratix GX receiver that are active in GigE mode. Receiver Architecture Figure 6–3. Block Diagram of the Stratix GX Receiver Digital Components in GigE Mode Analog Section Digital Section Word Deserializer Aligner...
Page 159 This step is necessary because the Stratix GX block uses a non-source-synchronous serial stream. To correctly align the byte boundary at the receiver, the Stratix GX device sends a unique synchronization pattern to the receiver that does not occur between any Dx.y or Kx.y code combinations, namely, a...
Page 160 The rx_syncstatus signal goes high when synchronization is complete, indicating that the data is valid. In the example, D1 is the first valid data. 6–6 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 161 {/K28.5/ /Dx.y/} code groups are the fastest way to achieve synchronization. GigE mode requires a special synchronization sequence that follows the IEEE 802.3 GMII PCS synchronization specification, as shown in Figure 6–7. Altera Corporation 6–7 January 2005 Stratix GX Transceiver User Guide...
Page 162 GigE Mode Receiver Architecture Figure 6–7. Synchronization Diagram State Machine 6–8 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 163: Rate Matcher
Rate Matcher The GigE mode operates in multi-crystal environments, which can tolerate a frequency variation of ± 100 ppm between crystals. Stratix GX devices have embedded circuitry to perform clock rate compensation by inserting or removing the /I2/ code group from the interpacket gap (IPG) or idle stream.
Page 164 /I2/ GMII Idle Stratix GX devices have a built-in rate matcher that is 12 words deep, which is a FIFO buffer with control logic. Stratix GX devices implement rate matching in GigE mode by adding or removing /I2/ ordered sets.
Page 165: 8B/10B Decoder
(MSB) last. The data received must be from the supported Dx.y or Kx.y list. All 8B/10B control signals (disparity error, control detect, and code error) are pipelined with the data in the Stratix GX receiver block and are edge-aligned with the data.
Page 166 0’s), the expected RD code must toggle back and forth between RD- and RD+. At time n + 3, the 8B/10B decoder received an RD+ K28.5 code (10’h283), which would make the current running disparity negative. 6–12 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 167 K28.5 code (BC + ctrl). The rx_ctrldetect=1’b1 port is aligned with 8’hbc, indicating that it is a control code. The rest of the code received is data. Altera Corporation 6–13 January 2005 Stratix GX Transceiver User Guide...
Page 168: Receiver Phase Compensation Fifo Buffer
The receiver phase compensation FIFO buffer is always used, and you cannot bypass it. GigE Mode Figure 6–15 shows the digital components of the Stratix GX transmitter that are active in GigE mode. Transmitter Architecture 6–14...
Page 169: Transmitter Phase Compensation Fifo Buffer
CORECLK_OUT port feeds the TX_CORECLK port. This connection occurs using the logic array routing. As a result, the software defaults to using an FPGA global clock, regional clock, or fast regional clock resource. Altera Corporation 6–15 January 2005 Stratix GX Transceiver User Guide...
Page 170: Gige Transmitter Synchronization
GigE Transmitter Synchronization The transmitter must send out the GigE synchronization sequence to synchronize the target receiver. Stratix GX devices do not have a built-in macro that performs this function on power-up or txdigitalreset. This function must be implemented in user logic to send out a /K28.5/, /Dx.y/, /K28.5/, /Dx.y/, /K28.5/, /Dx.y/ sequence.
Page 171: 8B/10B Encoder
/I1/ /I2/ Order Set 8B/10B Encoder The 8B/10B encoder is part of the Stratix GX transceiver block. The 8B/10B encoder translates 8-bit data and a 1-bit control identifier (by using the tx_ctrlenable signal) into a 10-bit, DC-balanced data stream. For more information about the 8B/10B code, refer to the 8B/10B Code section in the Appendix.
Page 172 Although one set of invalid data is shown between the txdigitalreset signal going low and the first of three automatic K28.5, there can be more than one invalid data set. 6–18 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 173 /K24.1/ can be encoded to be 10’b0110001100 (0x18C), which is equivalent to a /D24.6/+ (0xD8 from the RD+ column). An 8B/10B decoder decodes this incorrectly (based on the 8B/10B Fibre Channel specification). Altera Corporation 6–19 January 2005 Stratix GX Transceiver User Guide...
Page 174: Gige Mode Clocking
GigE mode is selected. The wizard also offers clock options, other than default, to facilitate your clocking schemes. Figure 6–21. Default Configuration of altgxb Megafunction in GigE Mode 6–20 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 175 PLL and also enables the separation of receiver and transmitter reference clocks. This configuration is shown Figure 6–22. For more information on parallel interface speeds, refer to the Stratix GX FPGA Family data sheet. Altera Corporation 6–21...
Page 176 PLL reference clock. This input clock port is available only when the receiver PLL is not trained by the transmitter PLL. 6–22 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 177 FIFO buffer. Before you can enable this feature, you must set the receiver to 8-bit mode. Figure 6–23 shows the clock configuration with these optional input ports enabled. Altera Corporation 6–23 January 2005 Stratix GX Transceiver User Guide...
Page 178 Input to transmitter PLL. Available as a port when transmitter PLL is instantiated. INCLK Input Input to CRU. Available as a port when CRU is not trained by transmitter PLL. RX_CRUCLK 6–24 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 179: Gige Mode Inter-Transceiver Clocking
Quartus II MegaWizard built-in functions. The number of supported channels varies based on the type of Stratix GX device you select. Because of the various configurations of the input and output clocks, consider the clocking schemes between transceiver blocks carefully to avoid future problems in the design cycle.
Page 180 Each transceiver block has the ability to share a common reference clock through the inter-transceiver lines (IQ lines). The Stratix GX logic array clock usage can be reduced by using the IQ lines. The IQ lines are used when a REFCLKB input port from one transceiver block or channel drives other transceiver blocks or channels.
Page 181 IQ lines and which transceiver block REFCLKB drives the REFCLKB pin. This data is based on the number of transceiver channels in the Stratix GX device. Table 6–3. REFCLKB Pin to Inter-Transceiver Line Connections REFCLKB Pin in...
Page 182 Global Clocks, I/O Bus, General Routing refclkb Global Clocks, I/O Bus, General Routing Receiver PLLs Transceiver Block 3 Transmitter Global Clocks, I/O Bus, General Routing refclkb Global Clocks, I/O Bus, General Routing Receiver PLLs 6–28 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 183 For example, if a REFCLKB pin is required to feed a transmitter PLL using an inter-transceiver line, the REFCLKB pin cannot be in transceiver block 1, because IQ2 only feeds the receiver PLLs. Altera Corporation 6–29 January 2005 Stratix GX Transceiver User Guide...
Page 184 Global Clks, I/O Bus, Gen Routing refclkb Global Clks, I/O Bus, Gen Routing Receiver PLLs Transceiver Block 3 TX PLL Global Clks, I/O Bus, Gen Routing refclkb Global Clks, I/O Bus, Gen Routing Receiver PLLs 6–30 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 185: Gige Mode Megawizard Considerations
MegaWizard Plug-In also disables any options that do not apply to GigE mode. Although you can instantiate the Stratix GX block directly by calling out the altgxb megafunction, Altera recommends that you use the MegaWizard Plug-In Manager to instantiate your altgxb megafunction to reduce the chance of invalid settings.
Page 186 8 bits: single width For more information, refer to the Stratix GX Analog Description chapter. rxdigitalreset: resets the digital blocks in the receiver channel. Each active receiver channel has its own digital reset.
Page 187 Figure 6–28. MegaWizard Plug-In - ALTGXB (Page 4 of 9) - General (2) Notes (1), Notes to Figure 6–28: For more information, refer to the Loopback Modes chapter. For more information, refer to the Stratix GX Built-In Self Test (BIST) chapter. Altera Corporation 6–33 January 2005 Stratix GX Transceiver User Guide...
Page 188 Enable this if the device is an engineering sample device. For more information, refer to the Stratix GX Analog Description chapter. The word aligner in GigE mode is always set as a 10-bit K28.5 pattern. Both positive and negative disparities are checked.
Page 189 Figure 6–30: For more information, refer to the Stratix GX Analog Description chapter. The GigE data rate is set to 1250 Mbps by default. Possible multiplication factors of the input clock are 2, 4, 5, 8, 10, 16, and 20. Multiplication factors of 2, 4, and 5 must use the refclkb pins. A multiplication factor of 2 also requires that the receiver PLL be trained by the transmitter PLL.
Page 190 For more information, refer to the Stratix GX Analog Description chapter. Receiver PLL lock indicator. For rx_locked, Low = receiver PLL locked to reference clock. The rx_signaldetect is only available in XAUI or GigE mode. Refer to the Stratix GX Analog Description chapter for additional information.
Page 191 Figure 6–32: For more information, refer to the Stratix GX Analog Description chapter. tx_coreclk. You can optionally choose the write clock of the transmitter phase comp FIFO buffer. This clock should be frequency locked with the internal reference clock because the phase comp FIFO buffer cannot tolerate frequency variations and contains no error flags.
Page 192: Design Example
`define reset 3'd0 `define donothing 3'd1 `define sync 3'd2 `define tx_err 3'd3 6–38 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 193 .pllenable(1'b1), .inclk(clk), .rx_in(rx_in), .rx_slpbk(1'b1), .rxanalogreset(1'b0), .tx_in(txdata), .tx_ctrlenable(txctrl), .rxdigitalreset(reset), .txdigitalreset(1'b0), .rx_disperr(disperr), .rx_patterndetect(patterndetect), .rx_ctrldetect(ctrldetect), .tx_out(txout), .rx_errdetect(errdetect), .coreclk_out(coreclk), .rx_out(rxout), .rx_syncstatus(syncstatus)); //governing counter always@(posedge clk) globalcntr <= globalcntr +1; //control character counter always@(posedge clk) Altera Corporation 6–39 January 2005 Stratix GX Transceiver User Guide...
Page 194 //sending control characters nextst=`count; //sending counter values nextst=`tx_err; //sending 4 illegal codes nextst=`donothing; //do nothing until resync default: nextst= curst; endcase always @(posedge clk) curst<=nextst; always@(posedge clk) case(curst) `reset: //resets receiver 6–40 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 195 `count: //sends out value of a counter begin reset<=0; txctrl<=0; txdata<=datacntr; `txk: //sends out all 12 K codes begin reset<=0; txctrl<=1; txdata<=kdata; default: begin reset<=0; txctrl<=0; txdata<=datacntr; endcase endmodule Altera Corporation 6–41 January 2005 Stratix GX Transceiver User Guide...
Page 196 [0:0] sub_wire1; wire [0:0] sub_wire2; wire [0:0] sub_wire3; wire [7:0] sub_wire4; wire [0:0] sub_wire5; wire [0:0] sub_wire6; wire [0:0] sub_wire7; wire [0:0] rx_disperr = sub_wire0[0:0]; wire [0:0] rx_patterndetect = sub_wire1[0:0]; 6–42 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 197 = 0, altgxb_component.use_auto_bit_slip = "ON", altgxb_component.use_rate_match_fifo = "ON", altgxb_component.signal_threshold_select = 80, altgxb_component.use_double_data_mode = "OFF", altgxb_component.use_preemphasis_ctrl_signal = "OFF", altgxb_component.protocol = "GIGE", altgxb_component.clk_out_mode_reference = "ON", altgxb_component.rx_bandwidth_type = "LOW", altgxb_component.disparity_mode = "ON", Altera Corporation 6–43 January 2005 Stratix GX Transceiver User Guide...
Page 198: Simulation Waveform & Hardware Verification Results
There is good correlation between the SignalTap II logic analyzer results and the Quartus II software simulation. Figure 6–34. GigE Synchronization Sequence SignalTap II Results 6–44 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 199 /K28.4/ code group (8’h9C + ctrl). In the example, four invalid codes are transmitted with zero valid codes in between. Figure 6–36. Loss of Synchronization SignalTap II Logic Analyzer Results Figure 6–37. Loss of Synchronization Quartus II Simulation Results Altera Corporation 6–45 January 2005 Stratix GX Transceiver User Guide...
Page 200 Design Example 6–46 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 201: Chapter 7. Loopback Modes
The serial data is the data that is transmitted from the Stratix GX device. Once the data enters the receiver in serial form, it can use any of the receiver blocks and is then fed into the FPGA logic array.
Page 202: Parallel Loopback
Parallel Loopback Figure 7–1. Stratix GX Block in Serial Loopback Mode BIST PRBS Verifier BIST Word Deserializer Incremental Aligner Channel Verifier Aligner Rate Matcher 8B/10B Phase Decoder Byte Compensation Clock FIFO Deserializer Recovery Unit Byte Phase Serializer 8B/10B Serializer Compensation...
Page 203: Reverse Serial Loopback
Loopback Modes Figure 7–2. Stratix GX Block in Parallel Loopback Mode BIST PRBS Verifier BIST Word Deserializer Incremental Aligner Channel Verifier Aligner Rate Matcher 8B/10B Phase Compensation Decoder Byte Clock FIFO Deserializer Recovery Unit Phase Byte Serializer 8B/10B Compensation Serializer...
Page 204 Reverse Serial Loopback Figure 7–3. Stratix GX Block in Reverse Serial Loopback Mode BIST PRBS Verifier BIST Word Deserializer Incremental Aligner Channel Verifier Aligner Rate Phase Matcher 8B/10B Compensation Decoder Byte Clock FIFO Deserializer Recovery Unit Phase Byte Serializer 8B/10B...
Page 205: Chapter 8. Stratix Gx Built-In Self Test (Bist)
Figure 8–1 shows a simplified block diagram of the BIST circuitry. Figure 8–1. Image of Stratix GX Built-In Self Test txdigitalreset[] tx_out[] Built-In Self Test rxdigitalreset[]...
Page 206: Pattern Generator
PRBS generator yields 2 -1 unique patterns. Table 8–1 lists the modes and their associated polynomials. Table 8–1. BIST Generator PRBS Modes Data Width PRBS Mode Polynomials 8-bit 10-bit 16-bit 20-bit 8–2 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 207: Incremental Mode Generator
Stratix GX Built-In Self Test (BIST) PRBS mode is enabled when the PRBS option is enabled in the Quartus II software. The 8b-10b encoder/decoder is bypassed automatically in this mode. You can use PRBS generation to test the functionality of both the transmitter and receiver, to test if the BIST verifier is enabled, or to measure the quality of the transmission medium.
Page 208: Low-Frequency Mode Generator
Once again, this approach is useful only for a first-order approximation. Use extractions of RLGC values with 2D and 3D field solvers to determine more accurate loss coefficients. 8–4 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 209: Mix-Frequency Mode Generator
Stratix GX Built-In Self Test (BIST) Low-frequency mode is enabled when you select the SELF_ option 3 in the Quartus II software under what self test mode do you want to use? You must enable the 8b/10b encoder to generate the high-frequency pattern.
Page 210: Incremental Mode Verifier
Table 8–2. Verification Modes Verification Mode Comma Loopback Modes 16'b1000000011111111 Serial or parallel (A1A2 mode) 10'b111111111 Serial or parallel (10-bit mode) Incremental 10'b0011111010 Serial or parallel or post (10-bit mode) 8B/10B parallel 8–6 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 211: Design Examples
Stratix GX Built-In Self Test (BIST) Design The purpose of these design examples are to show how to instantiate and operate the various BIST modes in Stratix GX devices. The following Examples reference designs cover: ■ PRBS BIST generator and verification design ■...
Page 212 [19:0] counter; reg reset; always @ (posedge clk) counter = counter +1; always @ (counter) begin if ((counter >= 20'b11111111111111100000) && (counter <= 20'b11111111111111111111)) reset = 1'b1; else reset = 1'b0; 8–8 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 213 Stratix GX Built-In Self Test (BIST) endmodule altgxb Instantiation (PRBS_BIST.v) module PRBS_BIST ( inclk, rx_in, rx_slpbk, rxdigitalreset, tx_out, coreclk_out, rx_clkout, rx_bistdone, rx_bisterr); input[ 0:0] inclk; input[ 0:0] rx_in; input [0:0] rx_slpbk; input [0:0] rxdigitalreset; output [0:0] tx_out; output [0:0] coreclk_out;...
Page 214 = "OFF", altgxb_component.intended_device_family = "Stratix GX", altgxb_component.use_equalizer_ctrl_signal = "OFF", altgxb_component.rx_enable_dc_coupling = "OFF", altgxb_component.run_length_enable = "OFF", altgxb_component.pll_use_dc_coupling = "OFF", altgxb_component.operation_mode = "DUPLEX", altgxb_component.use_8b_10b_mode = "OFF", altgxb_component.use_rx_clkout = "ON", altgxb_component.data_rate_remainder = 0, 8–10 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 215: Design 2: Incremental Bist Generator & Verification Design
Stratix GX Built-In Self Test (BIST) altgxb_component.data_rate = 3125, altgxb_component.align_pattern = "P1111111111", altgxb_component.use_rx_cruclk = "OFF", altgxb_component.number_of_quads = 1; endmodule Results A quick method for verifying whether the BIST verification passes or fails ® ® is to use the SignalTap II logic analyzer in the Quartus II software.
Page 216 VCC; assign reset = reset_wire; assign VCC = 1; Incr_BIST Incr_BIST_inst( .inclk(inclk), .rx_in(rx_in), .rx_slpbk(VCC), .rxdigitalreset(reset_wire), 8–12 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 217 Stratix GX Built-In Self Test (BIST) .coreclk_out(coreclk_out), .rx_bistdone(rx_bistdone), .rx_bisterr(rx_bisterr), .rx_clkout(rx_clkout), .tx_out(tx_out)); reset_mod reset_mod_inst( .clk(inclk), .reset(reset_wire)); endmodule Reset Module Design (reset_mod.v) module reset_mod(clk, reset); input clk; output reset; reg [19:0] counter; reg reset; always @ (posedge clk) counter = counter +1;...
Page 218 = 16, altgxb_component.pll_inclock_period = 6250, altgxb_component.use_symbol_align = "ON", altgxb_component.rx_ppm_setting = 1000, altgxb_component.pll_bandwidth_type = "LOW", altgxb_component.dwidth_factor = 2, altgxb_component.number_of_channels = 1, altgxb_component.vod_ctrl_setting = 1000, altgxb_component.align_pattern_length = 10, altgxb_component.use_self_test_mode = "ON", 8–14 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 219 Stratix GX Built-In Self Test (BIST) altgxb_component.lpm_type = "altgxb", altgxb_component.use_fifo_mode = "ON", altgxb_component.use_vod_ctrl_signal = "OFF", altgxb_component.equalizer_ctrl_setting = 0, altgxb_component.use_auto_bit_slip = "ON", altgxb_component.use_rate_match_fifo = "OFF", altgxb_component.signal_threshold_select = 80, altgxb_component.self_test_mode = 1, altgxb_component.use_double_data_mode = "ON", altgxb_component.use_preemphasis_ctrl_signal = "OFF", altgxb_component.protocol = "CUSTOM", altgxb_component.clk_out_mode_reference = "ON", altgxb_component.rx_bandwidth_type = "LOW",...
Page 220: Design 3: High-Frequency Transmitter Generator Design
[0:0] sub_wire0; wire [0:0] sub_wire1; wire [0:0] tx_out = sub_wire0[0:0]; wire [0:0] coreclk_out = sub_wire1[0:0]; altgxb altgxb_component .inclk (inclk), .tx_out (sub_wire0), .coreclk_out (sub_wire1)); defparam altgxb_component.force_disparity_mode = "OFF", altgxb_component.channel_width = 16, 8–16 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 221 Stratix GX Built-In Self Test (BIST) altgxb_component.pll_inclock_period = 6250, altgxb_component.pll_bandwidth_type = "LOW" altgxb_component.dwidth_factor = 2, altgxb_component.number_of_channels = 1 altgxb_component.vod_ctrl_setting = 1000, altgxb_component.use_self_test_mode = "ON", altgxb_component.lpm_type = "altgxb", altgxb_component.use_fifo_mode = "ON", altgxb_component.use_vod_ctrl_signal = "OFF", altgxb_component.self_test_mode = 2, altgxb_component.use_double_data_mode = "ON", altgxb_component.use_preemphasis_ctrl_signal = "OFF",...
Page 222: Design 4: Low-Frequency Transmitter Generator Design
( inclk, tx_out, coreclk_out); input [0:0] inclk; output [0:0] tx_out; output [0:0] coreclk_out; wire [0:0] sub_wire0; wire [0:0] sub_wire1; wire [0:0] tx_out = sub_wire0[0:0]; wire [0:0] coreclk_out = sub_wire1[0:0]; 8–18 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 223 Stratix GX Built-In Self Test (BIST) altgxb altgxb_component ( inclk (inclk), .tx_out (sub_wire0), .coreclk_out (sub_wire1)); defparam altgxb_component.force_disparity_mode = "OFF", altgxb_component.channel_width = 16, altgxb_component.pll_inclock_period = 6250, altgxb_component.pll_bandwidth_type = "LOW", altgxb_component.dwidth_factor = 2, altgxb_component.number_of_channels = 1, altgxb_component.vod_ctrl_setting = 1000, altgxb_component.use_self_test_mode = "ON", altgxb_component.lpm_type = "altgxb",...
Page 224: Design 5: Mix-Frequency Transmitter Generator Design
Instantiation (mix_freq_BIST.v) module mix_freq_BIST ( inclk, tx_out, coreclk_out); input [0:0] inclk; output[0:0] tx_out; output[0:0] coreclk_out; wire [0:0] sub_wire0; wire [0:0] sub_wire1; wire [0:0] tx_out = sub_wire0[0:0]; wire [0:0] coreclk_out = sub_wire1[0:0]; 8–20 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 225 Stratix GX Built-In Self Test (BIST) altgxb altgxb_component ( inclk (inclk), .tx_out (sub_wire0), .coreclk_out (sub_wire1)); defparam altgxb_component.force_disparity_mode = "OFF", altgxb_component.channel_width = 16, altgxb_component.pll_inclock_period = 6250, altgxb_component.pll_bandwidth_type = "LOW", altgxb_component.dwidth_factor = 2, altgxb_component.number_of_channels = 1, altgxb_component.vod_ctrl_setting = 1000, altgxb_component.use_self_test_mode = "ON", altgxb_component.lpm_type = "altgxb",...
Page 226 Design Examples Figure 8–9. Mix-Frequency BIST Measured on tx_out[] 8–22 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 227: Chapter 9. Reset Control & Power Down
Power On Reset At power on, the Stratix GX transceiver uses built-in circuits that handle the reset of the digital and analog circuits. After power on reset (POR), the (POR) Stratix GX block is guaranteed to be in a known state.
Page 228 The analog circuitry is powered down when the rxanalogreset signal goes high. Although there is no specific requirement on the duration of the rxanalogreset signal, Altera lab experiments have shown that 1 ms is a safe value. If you use the...
Page 229 The slow clock is divided down by the deserialization factor from rx_clkout. Altera recommends synchronizing rxdigitalreset to the FPGA or the logic array clock. Table 9–1. Reset Signal Map to Stratix GX Blocks rxdigitalreset rxanalogreset...
Page 230: Recommended Resets
Output Clock Data Path Width Double Width Single Width (16/20) (8/10) Receive Receive Transmit Transmit Parallel Clock Parallel Clock Parallel Clock Parallel Clock rx_coreclk tx_coreclk rx_clkout rx_clkout inclk tx_coreclk inclk 9–4 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 231 = low pll_areset = low rxanalogreset = low transmit_digitalreset receive_digitalreset txdigitalreset = low = high = high rxdigitalreset = high txdigitalreset rxdigitalreset = high = high rx_freqlocked = high? Altera Corporation 9–5 January 2005 Stratix GX Transceiver User Guide...
Page 232 See the Stratix GX FPGA Family data sheet for the amount of time loaded into the timer. When the timer counts down, rx_clkout is stable.
Page 233 We have made every effort to ensure that this design example works correctly. If you have a question or problem that is not answered by the information then please contact Altera Support. **************************************************************** Reset Sequence for the ALTGXB. The configuration of GXB for which...
Page 234 //Parameter value of T (2ms)based on the fastest clock (or 3.1875 Gbps) parameter WAITSTATE_TIMER_VALUE = 1000000; reg [19:0]waitstate_timer; //timer - for actual value, refer stratix data sheet assign rxanalogreset = rxanalogreset_inclk; 9–8 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 235 //Wait untill the TXPLL is locked to inclk and TX PLL has a stable output clock which is also fed to RX CRU else if (pll_locked) begin state <= STABLE_TX_PLL; rxdigitalreset_inclk<= 1'b1; rxanalogreset_inclk <= 1'b0; txdigitalreset<= 1'b0; pll_areset <= 1'b0; else begin Altera Corporation 9–9 January 2005 Stratix GX Transceiver User Guide...
Page 236 //Decrement a Timer of 2ms (Refer Stratix GX Datasheet for accurate value)after rx_freqlocked is asserted //This time is given to ensure the recovered clock to be stable (No freq variations) and is locked...
Page 237 @(posedge rx_coreclk or posedge async_reset) if(async_reset) begin rxdigitalreset_rx_coreclk_Q <= 1'b1; rxdigitalreset <= 1'b1; else begin if(receive_digitalreset) begin rxdigitalreset_rx_coreclk_Q <= 1'b1; rxdigitalreset <= 1'b1; Altera Corporation 9–11 January 2005 Stratix GX Transceiver User Guide...
Page 238 We have made every effort to ensure that this design example works correctly. If you have a question or problem that is not answered by the information then please contact Altera Support. **************************************************************** Reset Sequence for the ALTGXB. The configuration of GXB for which...
Page 239 //GXB transmit digital reset output pll_areset;//GXB power down signal reg rxdigitalreset; wire rxanalogreset; reg txdigitalreset; reg pll_areset; reg [2:0] state; reg rxdigitalreset_inclk; reg rxanalogreset_inclk; Altera Corporation 9–13 January 2005 Stratix GX Transceiver User Guide...
Page 240 <= 1'b0; state <= IDLE; if(transmit_digitalreset) txdigitalreset <= 1'b1; else txdigitalreset <= 1'b0; STROBE_TXPLL_LOCKED: if (sync_reset) //Synchronous Reset can be asserted in IDLE state (After reset seq has finished) 9–14 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 241 1'b0; pll_areset <= 1'b0; WAIT_STATE: if (sync_reset) //Synchronous Reset can be asserted in IDLE state (After reset seq has finished) begin rxdigitalreset_inclk <= 1'b1; rxanalogreset_inclk <= 1'b1; txdigitalreset <= 1'b1; Altera Corporation 9–15 January 2005 Stratix GX Transceiver User Guide...
Page 242 //Decrement a Timer of 2ms (Refer Stratix GX Datasheet for accurate value)after rx_freqlocked is asserted //This time is given to ensure the recovered clock to be stable (No freq variations) and is locked...
Page 243 PLLs with their respective input reference clocks (inclk and rx_cruclk). In this configuration, both the transmit and receive parts of the transceiver are used. Figure 9–5 shows the possible clock options for the selected transceiver configuration. Altera Corporation 9–17 January 2005 Stratix GX Transceiver User Guide...
Page 244 Clock Single Width Double Width (8/10) (16/20) Transmit Transmit Parallel Receive Clock Parallel Parallel Clock Clock rx_clkout rx_coreclk tx_coreclk inclk rx_clkout tx_coreclk inclk Figure 9–6 shows the transmitter reset sequence. 9–18 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 245 PLL is stable (pll_locked = 1'b1) before deasserting tx_digitalreset. This ensures that the output of the transmitter PLL is stable before releasing any of the logic that it feeds. Altera Corporation 9–19 January 2005 Stratix GX Transceiver User Guide...
Page 246 Recommended Resets Figure 9–7. Transmitter Reset Sequence Waveform Reset Signals pll_areset tx_digitalreset Stable TXPLL Clock Output Status pll_locked Figure 9–8 shows the receiver reset sequence. 9–20 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 247 You should be able to monitor the BER (for example, a synchronization state machine based on the Stratix GX transceiver data) to determine whether the system is initialized and working properly. See the Stratix GX FPGA Family data sheet for the value of Trx_freqlock2phaselock. Altera Corporation 9–21...
Page 248 Appendix C, REFCLKB Pin Constraints for information about the effects of analog resets (pll_arest, rx_analogreset). Copyright (c) Altera Corporation, 2004. This file may contain proprietary and confidential information of Altera Corporation 9–22 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 249 //Input : Reset the receiver section input rx_freqlocked; //rx_freqlocked signal from receive; Transition from 'lock to reference clock mode' to 'lock to data mode' input pll_locked; // Transmit PLL of GXB locked Altera Corporation 9–23 January 2005 Stratix GX Transceiver User Guide...
Page 250 IDLE state (After reset seq has finished) begin txdigitalreset <= 1'b1; pll_areset <= 1'b1; state<= STROBE_TXPLL_LOCKED; else begin pll_areset <= 1'b0; state <= IDLE; if(transmit_digitalreset) txdigitalreset <= 1'b1; else txdigitalreset <= 1'b0; 9–24 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 251 <= 1'b1; rxdigitalreset_rx_cruclk <= 1'b1; waitstate_timer <= WAITSTATE_TIMER_VALUE; else begin if(sync_reset) begin rxanalogreset <= 1'b1; rxdigitalreset_rx_cruclk<= 1'b1; waitstate_timer <= WAITSTATE_TIMER_VALUE; else begin rxanalogreset <= 1'b0; if (rx_freqlocked) begin if(waitstate_timer == 0) Altera Corporation 9–25 January 2005 Stratix GX Transceiver User Guide...
Page 252 @(posedge rx_coreclk or posedge async_reset) if(async_reset) begin rxdigitalreset_rx_coreclk_Q <= 1'b1; rxdigitalreset <= 1'b1; else begin if(receive_digitalreset) begin rxdigitalreset_rx_coreclk_Q <= 1'b1; rxdigitalreset <= 1'b1; else begin rxdigitalreset_rx_coreclk_Q <= rxdigitalreset_rx_cruclk; rxdigitalreset <= rxdigitalreset_rx_coreclk_Q; 9–26 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 253 Transmit and Receive : Both used Datapath : Single Width(8/10 bits) or Double Width(16/20 bits) receive parallel clock: rx_clkout Functional Mode :'Any' RX PLL CRU : rx_cruclk Altera Corporation 9–27 January 2005 Stratix GX Transceiver User Guide...
Page 254 //GXB transmit digital reset output pll_areset;//GXB power down signal reg rxdigitalreset; reg txdigitalreset; reg pll_areset; reg [2:0] state; reg rxdigitalreset_rx_cruclk; reg rxdigitalreset_rx_clkout_Q; reg rxanalogreset; parameter IDLE = 3'b000; parameter STROBE_TXPLL_LOCKED = 3'b001; 9–28 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 255 //Wait untill the TXPLL is locked to inclk and TX PLL has a stable output clock which is also fed to RX CRU else if (pll_locked) begin state <= STABLE_TX_PLL; txdigitalreset<= 1'b0; pll_areset <= 1'b0; else Altera Corporation 9–29 January 2005 Stratix GX Transceiver User Guide...
Page 256 <= 1'b0; if (rx_freqlocked) begin if(waitstate_timer == 0) begin waitstate_timer <= waitstate_timer; if(receive_digitalreset) rxdigitalreset_rx_cruclk <= 1'b1; else rxdigitalreset_rx_cruclk <= 1'b0; else begin waitstate_timer <= waitstate_timer - 1'b1; 9–30 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 257 @(posedge rx_clkout or posedge async_reset) if(async_reset) begin rxdigitalreset_rx_clkout_Q <= 1'b1; rxdigitalreset <= 1'b1; else begin if(receive_digitalreset) begin rxdigitalreset_rx_clkout_Q <= 1'b1; rxdigitalreset <= 1'b1; else begin rxdigitalreset_rx_clkout_Q <= rxdigitalreset_rx_cruclk; rxdigitalreset <= rxdigitalreset_rx_clkout_Q; endmodule Altera Corporation 9–31 January 2005 Stratix GX Transceiver User Guide...
Page 258: Receiver Reset
Double Width (8/10) (16/20) Receive Parallel Clock Receive Parallel Clock rx_clkout rx_coreclk rx_clkout The flow chart in Figure 9–11 shows a situation where only the receive channel requires a reset sequence. 9–32 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 259 T ms. When the timer counts down the value, it signifies that rx_clkout is stable. The reset controller then deasserts the rx_digital reset, which completes the reset sequence. Altera Corporation 9–33 January 2005 Stratix GX Transceiver User Guide...
Page 260 Recommended Resets See the Stratix GX FPGA Family data sheet for the value of Trx_freqlock2phaselock. Figure 9–12. Receiver Reset Sequence Waveform Reset Signals rx_analogreset rx_digitalreset Stable Recovered Clock Output Status rx_freqlocked Trx_freqlock2phaselock Design Example 1 This design example shows a receive only configuration where inclk is the transmit PLL input reference clock, the output of transmit PLL trains receive CRU, and rx_coreclk is the receive parallel interface clock.
Page 261 //Input : Reset the receiver section input rx_freqlocked; //rx_freqlocked signal from receive; Transition from 'lock to reference clock mode' to 'lock to data mode' input pll_locked; // Transmit PLL of GXB locked Altera Corporation 9–35 January 2005 Stratix GX Transceiver User Guide...
Page 262 (sync_reset) //Synchronous Reset can be asserted in IDLE state (After reset seq has finished) begin rxdigitalreset_inclk <= 1'b1; rxanalogreset_inclk <= 1'b1; pll_areset <= 1'b1; waitstate_timer <= WAITSTATE_TIMER_VALUE; state<= STROBE_TXPLL_LOCKED; else 9–36 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 263 <= STROBE_TXPLL_LOCKED; else if (rx_freqlocked) begin state <= WAIT_STATE; waitstate_timer <= waitstate_timer - 1'b1 ; rxdigitalreset_inclk<= 1'b1; rxanalogreset_inclk <= 1'b0; pll_areset <= 1'b0; else begin state <= STABLE_TX_PLL; rxdigitalreset_inclk<= 1'b1; Altera Corporation 9–37 January 2005 Stratix GX Transceiver User Guide...
Page 264 //Decrement a Timer of 2ms (Refer Stratix GX Datasheet for accurate value)after rx_freqlocked is asserted //This time is given to ensure the recovered clock to be stable (Cannot have any freq variations) and...
Page 265 ■ This design example does not cover all the digital reset scenarios in a system that resets the digital logic of the GXB. Altera Corporation 9–39 January 2005 Stratix GX Transceiver User Guide...
Page 266 We have made every effort to ensure that this design example works correctly. If you have a question that is not answered by the information then please contact Altera Support. **************************************************************** Reset Sequence for the ALTGXB. The configuration of GXB for which...
Page 267 <= 1'b1; waitstate_timer <= WAITSTATE_TIMER_VALUE; state <= STROBE_TXPLL_LOCKED; else case (state) IDLE: if (sync_reset) //Synchronous Reset can be asserted in IDLE state (After reset seq has finished) begin rxdigitalreset_inclk <= 1'b1; Altera Corporation 9–41 January 2005 Stratix GX Transceiver User Guide...
Page 268 IDLE state (After reset seq has finished) begin rxdigitalreset_inclk <= 1'b1; rxanalogreset_inclk <= 1'b1; pll_areset <= 1'b1; state <= STROBE_TXPLL_LOCKED; else if (rx_freqlocked) begin state <= WAIT_STATE; 9–42 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 269 //Decrement a Timer of 2ms (Refer Stratix GX Datasheet for accurate value)after rx_freqlocked is asserted //This time is given to ensure the recovered clock to be stable (Cannot have any freq variations) and...
Page 270 CRU and the transmitter PLL output clock option disabled. The flow chart in Figure 9–11 on page 9–33 and the waveform shown in Figure 9–12 on page 9–34 are valid for this configuration also. 9–44 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 271 However, you can make changes to the design to avoid this if, for example, you want to debug your design without the core being reset. Altera Corporation 9–45 January 2005 Stratix GX Transceiver User Guide...
Page 272 //Input: async reset from system input receive_digitalreset; //Input : Reset the receiver section input rx_freqlocked; //rx_freqlocked signal from receive; Transition from 'lock to reference clock mode' to 'lock to data mode' 9–46 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 273 <= 1'b1; rxdigitalreset_rx_cruclk<= 1'b1; waitstate_timer <= WAITSTATE_TIMER_VALUE; else begin rxanalogreset <= 1'b0; if (rx_freqlocked) begin if(waitstate_timer == 0) begin waitstate_timer <= waitstate_timer; if(receive_digitalreset) rxdigitalreset_rx_cruclk <= 1'b1; else rxdigitalreset_rx_cruclk <= 1'b0; else Altera Corporation 9–47 January 2005 Stratix GX Transceiver User Guide...
Page 274 @(posedge rx_coreclk or posedge async_reset) if(async_reset) begin rxdigitalreset_rx_coreclk_Q <= 1'b1; rxdigitalreset <= 1'b1; else begin if(receive_digitalreset) begin rxdigitalreset_rx_coreclk_Q <= 1'b1; rxdigitalreset <= 1'b1; else begin rxdigitalreset_rx_coreclk_Q <= rxdigitalreset_rx_cruclk; rxdigitalreset <= rxdigitalreset_rx_coreclk_Q; endmodule 9–48 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 275 Transmit and Receive : Receive Only Datapath : Single Width(8/10 bits) or Double Width(16/20 bits) receive parallel clock: rx_clkout Functional Mode :'Any' RX PLL CRU : rx_cruclk ***************************************************************/ Altera Corporation 9–49 January 2005 Stratix GX Transceiver User Guide...
Page 276 [19:0]waitstate_timer; //timer - for actual value, refer stratix data sheet //Receive Reset Sequence always @(posedge rx_cruclk or posedge async_reset) if(async_reset) begin rxanalogreset <= 1'b1; rxdigitalreset_rx_cruclk <= 1'b1; waitstate_timer <= WAITSTATE_TIMER_VALUE; 9–50 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 277 To reset the rx_clkout domain logic in PLD fabric following reset is useful*/ Altera Corporation 9–51 January 2005 Stratix GX Transceiver User Guide...
Page 278: Transmitter Reset
(txdigitalreset) based on tx_coreclk are synchronized internally by the reset controller in the Stratix GX hard IP. This configuration only demonstrates the reset sequence. You might want to add additional escape states and other system-specific features in your design.
Page 279 = high txdigitalreset = high pll_areset = low txdigitalreset = high pll_areset = low pll_locked = high txdigitalreset = high pll_areset = low transmit_digitalreset = high txdigitalreset = low Altera Corporation 9–53 January 2005 Stratix GX Transceiver User Guide...
Page 280 However, you can make changes to the design to avoid this if, for example, you want to debug your design without the core being reset. 9–54 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 281 //Input: synchronous reset from the system input async_reset; //Input: async reset from system input transmit_digitalreset; //Input: Reset only the transmit digital section input pll_locked; // Transmit PLL of GXB locked Altera Corporation 9–55 January 2005 Stratix GX Transceiver User Guide...
Page 282 <= 1'b1; pll_areset <= 1'b1; state <= STROBE_TXPLL_LOCKED; //Wait untill the TXPLL is locked to inclk and TX PLL has a stable output clock which is also fed to RX CRU 9–56 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 283: Power Down
Power Down The Quartus II software automatically selects the power-down feature when you configure the Stratix GX device. All unused transceiver channels and transceiver blocks in a design are powered down to reduce the overall power consumption. The power-down feature cannot be used on the fly to turn the transceiver channels/transceiver blocks on/off without reconfiguration.
Page 284 Either leave these pins floating or connect refclkb(+) to GXB_GND through a 10-kΩ resistor and connect refclkb(-) to GXB_VCC through a 10-kΩ resistor to improve the device’s immunity to noise. Altera recommends driving the reference resistor pin low for the powered down transceiver block. Transmitter output is tri-stated at the lowest V setting and is toggling at any other setting.
Page 285: Appendix A. Data & Control Codes
The running disparity is calculated based on the sub-blocks of the 10-bit code. The 10-bit code is divided into 2 sub blocks, a 6-bit sub-block (abcdei) and a 4-bit sub-block (fghj), as shown in Figure A–2. Altera Corporation A–1 January 2005...
Page 286 The current running disparity at the end of a sub-block is negative if any of the following are true: The sub-block contains more zeros than ones. ● The 6-bit sub-block is 6'b111000. ● The 4-bit sub-block is 4'b1100. ● A–2 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 287: Supported Codes
001010 1011 D5.0 000 00101 101001 1011 101001 0100 D6.0 000 00110 011001 1011 011001 0100 D7.0 000 00111 111000 1011 000111 0100 D8.0 000 01000 111001 0100 000110 1011 Altera Corporation A–3 January 2005 Stratix GX Transceiver User Guide...
Page 288 101001 1001 D6.1 001 00110 011001 1001 011001 1001 D7.1 001 00111 111000 1001 000111 1001 D8.1 001 01000 111001 1001 000110 1001 D9.1 001 01001 100101 1001 100101 1001 A–4 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 289 011001 0101 D7.2 010 00111 111000 0101 000111 0101 D8.2 010 01000 111001 0101 000110 0101 D9.2 010 01001 100101 0101 100101 0101 D10.2 010 01010 010101 0101 010101 0101 Altera Corporation A–5 January 2005 Stratix GX Transceiver User Guide...
Page 290 000111 0011 D8.3 011 01000 111001 0011 000110 1100 D9.3 011 01001 100101 1100 100101 0011 D10.3 011 01010 010101 1100 010101 0011 D11.3 011 01011 110100 1100 110100 0011 A–6 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 291 000110 1101 D9.4 100 01001 100101 1101 100101 0010 D10.4 100 01010 010101 1101 010101 0010 D11.4 100 01011 110100 1101 110100 0010 D12.4 100 01100 001101 1101 001101 0010 Altera Corporation A–7 January 2005 Stratix GX Transceiver User Guide...
Page 292 100101 1010 D10.5 101 01010 010101 1010 010101 1010 D11.5 101 01011 110100 1010 110100 1010 D12.5 101 01100 001101 1010 001101 1010 D13.5 101 01101 101100 1010 101100 1010 A–8 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 293 010101 0110 D11.6 110 01011 110100 0110 110100 0110 D12.6 110 01100 001101 0110 001101 0110 D13.6 110 01101 101100 0110 101100 0110 D14.6 110 01110 011100 0110 011100 0110 Altera Corporation A–9 January 2005 Stratix GX Transceiver User Guide...
Page 294 110100 1000 D12.7 111 01100 001101 1110 001101 0001 D13.7 111 01101 101100 1110 101100 1000 D14.7 111 01110 011100 1110 011100 1000 D15.7 111 01111 010111 0001 101000 1110 A–10 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 295 001001 1110 D28.7 111 11100 001110 1110 001110 0001 D29.7 111 11101 101110 0001 010001 1110 D30.7 111 11110 011110 0001 100001 1110 D31.7 111 11111 101011 0001 010100 1110 Altera Corporation A–11 January 2005 Stratix GX Transceiver User Guide...
Page 296 8B/10B Code A–12 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 297: Appendix B. Ports & Parameters
Controls bit slipping Input port [NUMBER_OF_CHANNELS - rx_bitslip[] circuitry in the word 1..0] wide. If you enable the rx_bitslip aligner. port, the port cannot be rx_enacdet[] connected and the USE_AUTO_BIT_SLIP parameter must be set to Altera Corporation B–1 January 2005...
Page 298 3..0] wide. Use the following settings: setting. Incoming Signal Equalizer Control Setting Reserved Reserved Reserved Control signal for Input port [NUMBER_OF_CHANNELS - rx_locktorefclk[] transceiver block 1..0] wide. receiver PLL to lock to the reference clock. B–2 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 299 Reverse serial Input port [NUMBER_OF_CHANNELS - tx_srlpbk[] loopback input. 1..0] wide. Dynamically enables reverse serial loopback from rx_in[] port to the tx_out[] port Altera Corporation B–3 January 2005 Stratix GX Transceiver User Guide...
Page 300 Input port [NUMBER_OF_QUADS - 1..0] pllenable[] signal to the wide. transceiver block transmitter PLL. Sends a power Input port [NUMBER_OF_QUADS - 1..0] pll_areset[] down signal to the wide. transceiver block transmitter PLL. B–4 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 301: Output Ports
Output Ports Table B–2 lists the output ports of the Stratix GX device. Table B–2. Output Ports (Part 1 of 4) Port Name Required Description Comments Gives the status of the Output port [NUMBER_OF_QUADS - 1..0] pll_locked[] transceiver block wide. The...
Page 302 Channel alignment Output port [NUMBER_OF_QUADS - 1..0] rx_channelaligned[] status for the wide. If the parameter is set to PROTOCOL transceiver block , the port XAUI rx_channelaligned[] receiver channels. must be connected. B–6 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 303 Indicates whether the Output port [NUMBER_OF_CHANNELS * rx_ctrldetect[] 8B/10B decoder DWIDTH_FACTOR - 1..0] wide. If you set detects a control code. parameter to USE_8B_10B_MODE , the port is not rx_ctrldetect available. Altera Corporation B–7 January 2005 Stratix GX Transceiver User Guide...
Page 304 Output port [NUMBER_OF_CHANNELS * rx_a1a2sizeout[] signal as DWIDTH_FACTOR - 1..0] wide. a1a2size seen by the word aligner. Serialized transceiver Output port [NUMBER_OF_CHANNELS - tx_out[] block transmitter 1..0] wide. channel data signal. B–8 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 305: Parameter Descriptions
Parameter Table B–3 describes the Stratix GX device parameters. Descriptions Table B–3. Parameter Descriptions (Part 1 of 6) Parameter Type Required Comments String Specifies the operation of the transceiver block OPERATION_MODE transmitter PLL and transceiver block receiver PLL. Values are , and .
Page 306 MHz; (1 / ) * 1,000,000. When you CRU_INCLOCK_PERIOD specify the , the CRU_INCLOCK_PERIOD parameter cannot be used. PLL_INCLOCK_PERIOD For more information, see the table in the comments for the parameter. DATA_RATE B–10 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 307 USE_RATE_MATCH_FIFO Values are . If omitted, the default is String Indicates whether to use the built-in self test mode. USE_SELF_TEST_MODE Values are . If omitted, the default is Altera Corporation B–11 January 2005 Stratix GX Transceiver User Guide...
Page 308 Specifies whether the VOD control signal is used. If USE_VOD_CTRL_SIGNAL this parameter is turned on, the port is tx_vodctrl used and the parameter is VOD_CTRL_SETTING ignored. Values are . If omitted, the default B–12 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 309 Values are . If omitted, the default is String Specifies whether the transceiver block transmitter INSTANTIATE_ PLL is instantiated. Values are . If omitted, TRANSMITTER_PLL the default is Altera Corporation B–13 January 2005 Stratix GX Transceiver User Guide...
Page 310 If omitted, the default is 0. String Use this parameter for modeling and behavioral INTENDED_DEVICE_FAMILY simulation purposes. Create the altgxb megafunction ® with the MegaWizard Plug-in Manager to calculate the value for this parameter. B–14 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 311: Appendix C. Refclkb Pin Constraints
If the reference clock to the receiver (rx_cruclk) is routed globally, the clock pad is not in use and will not flat-line the reference clock. When the rxanalogreset signal of all four channels in a transceiver block is asserted, it also resets the transmitter PLL. Altera Corporation C–1 January 2005...
Page 312 Quartus II software simulation. Figure C–1 shows an example of a problem configuration using the Stratix GX 25F device. This configuration is also applicable to all devices in the Stratix GX device family. Figure C–1. Example Configuration Stratix GX25F Device...
Page 313: Quartus Ii Software Messages
(including the board) and cannot make changes. The Quartus II software version 4.0 supports configuration 3. There are no warnings and results vary from simulation to actual silicon. Altera Corporation C–3 January 2005 Stratix GX Transceiver User Guide...
Page 314 Error: XGMII GXB_RX:GXB_RX_b|CUSTOM_RX:CUSTOM_RX_inst|altgxb:altg xb_component|xgm_machine[0] exists in a Quad that has no GXB Transmitters and has GXB Transmitter PLL GXB_RX:GXB_RX_b|CUSTOM_RX:CUSTOM_RX_inst|altgxb:altg xb_component|pll[0], but all the RXANALOGRESET signals are connected. This is not allowed. C–4 Altera Corporation Stratix GX Transceiver User Guide January 2005...
Page 315: Recommendations
This reset signal must be used only if the PLLs fall into an unrecoverable state. During lab testing at the factory, the Stratix GX device did not require that the PLLs be reset. The PLLs have a wide pull in range and were able to relock to their respective reference clocks.
Page 316 ■ Do not use the pll_areset, pllenable, or rxanalogreset signals in receive-only configurations. The Stratix GX device is used in various systems and configurations. Based on the feedback and tests performed in the lab, assertion of any or all of these reset signals is not required for the PLLs to recover if they lose lock.
Page 317 (rx_cruclk). You must carefully evaluate your design based on the recommendations in this appendix. Because you can configure the Stratix GX device in many different ways, there might be some configurations that are not covered by this document. Please contact ALTERA Applications for resolution on issues that are not addressed in this document.
Page 318 Known Issues C–8 Altera Corporation Stratix GX Transceiver User Guide January 2005...

Altera Stratix GX User Manual

About this User Guide

Chapter 1. Introduction

Chapter 2. Stratix GX Analog Description

Chapter 3. Basic Mode

Chapter 4. SONET Mode

Chapter 5. XAUI Mode

Chapter 6. Gige Mode

Chapter 7. Loopback Modes

Chapter 8. Stratix GX Built-In Self Test (BIST)

Chapter 9. Reset Control & Power down

Appendix A. Data & Control Codes

Appendix B. Ports & Parameters

Appendix C. REFCLKB Pin Constraints

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Summary of Contents for Altera Stratix GX

Table of Contents