Panasonic DP-CL18 Technical Manual page 59

DP-CL18
3.6.5. Communication between CPU (IC6), ASIC1 (IC15) and Main Memory (SO-DIMM)
The main memory is the SO-DIMM that consists of SDRAM. It is controlled by the main memory interface in ASIC1 (IC15).
The followings are performed to the main memory by CPU and ASIC1.
(A) : Data reading/writing by CPU
(B) : Data reading by ASIC1 (IC15) and DMA write accessing by ASIC1
The access control for above operations (A) and (B) is controlled by ASIC1 (IC15). The address and control signals are outputted
from ASIC1. When the above operation (A) is performed, the data buses (DH, DL) are directly communicated between CPU and
main memory. When the above operation (B) is performed, the data buses (DH, DL) are directly communicated between ASIC1
and main memory.
When the above operation (A) is performed, the bus grant signal (NBG) over the bus request of CPU (IC6) is outputted from ASIC1
(IC15) and gated by PLD (IC11). Then the gated NBG (NBG-GATE) is inputted into CPU (IC6).
The main memory interface in ASIC1 outputs the control signals (SDRE, SDCE, SDW, SDCKE, SDDM7~0, SDMA12~0, SDBA1,
SDBA0 and SDCS3~0) to the SO-DIMM for directly communicating between CPU (or ASIC1) and SO-DIMM. The control signals
except SDCKE are fetched when one of signals SDCS3~0 is the low because the control signals except SDCS3~0 are common
usage for each memories.
The command [NOP, REF (auto refresh), PALL (all bank precharge), ACTV (low address strobe/bank active), READ (read), WRIT
(write), MRS (mode register set), etc] for the SO-DIMM is specified by the control signals SDRE, SDCE, SDW and specified
address signals. The specifying of byte is performed by the signals SDDM7~0. The reading/writing access is performed to the byte
that the SDDM7~0 is the low.
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