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LPC
The Low Pin Count Interface was defined by Intel
transition towards legacy free systems. It allows the integration of low-bandwidth legacy I/O
components within the system, which are typically provided by a Super I/O controller. Fur-
thermore, it can be used to interface firmware hubs, and embedded controller solutions. Data
transfer on the LPC bus is implemented over a 4 bit serialized data interface, which uses a
33MHz LPC bus clock. For more information about LPC bus refer to the Intel
Interface Specification Revision 1.1'.
Chapter 2 Hardware Installation
Chapter 2
LAD0
LPC
LAD1
VCC3
GND
10
2
1
9
LDA2
CLK
LAD3
RST#
FRAME#
Corporation to facilitate the industry's
®
Low Pin Count
®
Battery
The lithium ion battery powers the real-time clock and CMOS memory. It is an auxiliary source
of power when the main power is shut off.
Safety Measures
•
Danger of explosion if battery incorrectly replaced.
•
Replace only with the same or equivalent type recommend by the manufacturer.
•
Dispose of used batteries according to local ordinance
27
Battery
.
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