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Internal I/O Connectors
X
LPC Connector
The Low Pin Count Interface was defined by Intel
tion towards legacy free systems. It allows the integration of low-bandwidth legacy I/O compo-
nents within the system, which are typically provided by a Super I/O controller. Furthermore, it
can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embed-
ded controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized
data interface, which uses a 33MHz LPC bus clock. For more information about LPC bus refer
to the Intel
Low Pin Count Interface Specification Revision 1.1'. The table below indicates the
®
pin functions of the LPC connector.
Pin
Assignment
1
CLK
3
RST#
5
FRAME#
7
LAD3
9
LAD2
11
SERIRQ
13
5V5B
User's Manual | CMS630
„ LPC Connector
14
13
1
2
Corporation to facilitate the industry's transi-
®
Pin
Assignment
2
L_AD1
4
L_AD0
6
VCC3
8
GND
10
---
12
GND
14
5V
Internal I/O Connectors
X
PS2
„ PS2 Pin Assignment
Pin
Assignment
Pin
1
KCLK
2
3
KDAT
4
5
GND
6
7
---
8
9
GND
10
Chapter 2
HARDWARE INSTALLATION
1
2
Assignment
9
10
MCLK
MDAT
GND
GND
GND
28
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