Fluke 43B Service Manual page 40

43B
Service Manual
large HF gain. The C-ASIC includes a HF pre-amplifier with switchable gain factors for
the 1-2-5 steps. The C-ASIC also includes circuitry to adjust the gain, and pulse
response.
ADC output pin 27
The combined conditioned HF/LF signal is supplied to the ADC output (pin 27) via an
internal ADC buffer. The output voltage is 150 mV/d. The MIDADC signal (pin 28),
supplied by the ADC, matches the middle of the C-ASIC output voltage swing to the
middle of the ADC input voltage swing.
TRIGGER output pin 29
The combined conditioned HF/LF signal is also supplied to the trigger output (pin 29)
via an internal trigger buffer. The output voltage is 100 mV/d. This signal (TRIG-A) is
supplied to the TRIGGER ASIC for triggering, and for capacitance measurements.
For capacitance measurements the ADC output is not used, but the TRIG-A output pulse
length indicates the measured capacitance, see "Capacitance measurements" below.
GPROT input pin 2
PTC (Positive Temperature Coefficient) resistors (R106-R206) are provided between the
Input 1 and Input 2 shield ground, and the COM input (instrument ground). This
prevents damage to the test tool if the various ground inputs are connected to different
voltage levels. The voltage across the PTC resistor is supplied via the GPROT input pin
2 to an input buffer. If this voltage exceeds ±200 mV, the ground protect circuit in the
C-ASIC makes the DACTEST output (pin 24) high. The DACTEST line output level is
read by the D-ASIC via the slow ADC (See 3.3.2 "Power"). The test tool will give a
ground error warning.
Because of ground loops, a LF interference voltage can arise across PTC resistor R106
(mainly mains interference when the power adapter is connected). To eliminate this LF
interference voltage, it is buffered (also via input GPROT, pin 2), and subtracted from
the input signal. Pin 43B (PROTGND) is the ground reference of the input buffer.
CALSIG input pin 36
The reference circuit on the TRIGGER part supplies an accurate +1.23 V DC voltage to
the CALSIG input pin 36 via R141. This voltage is used for internal calibration of the
gain, and the capacitance measurement threshold levels. A reference current Ical is
supplied by the T-ASIC via R144 for calibration of the resistance and capacitance
measurement function. For ICAL see also Section 3.3.3.
POS input pin 1
The PWM circuit on the Digital part provides an adjustable voltage (0 to 3.3 V) to the
POS input via R151. The voltage level is used to move the input signal trace on the
LCD. The REFN line provides a negative bias voltage via R152, to create the correct
voltage swing level on the C-ASIC POS input.
OFFSET input pin 44
The PWM circuit on the Digital part supplies an adjustable voltage (0 to +3.3 V) to the
OFFSET input via R153. The voltage level is used to compensate the offset in the LF
path of the C-ASIC. The REFN line provides a negative bias voltage via R152, to create
the correct voltage swing level on the C-ASIC POS input.
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