Hyper Threading; Active Processor Cores; Limit Cpuid Maximum; Execute-Disable Bit (If Supported By The Os And The Cpu) - Supermicro Supero X9SRH-7F User Manual

X9SRH Motherboard Series User's Manual

Hyper Threading

Set to Enabled to use the processor's Hyper Threading Technology feature. The
options are Enabled and Disabled.

Active Processor Cores

Set to Enabled to use a processor's Second Core and beyond. (Please refer to
Intel's web site for more information.) The options are All,1, 2, 4 and 6. Note: The
options displayed here depends on the type of processor that is installed.

Limit CPUID Maximum

This feature allows the user to set the maximum CPU ID value. Enable this function
to boot the legacy operating systems that cannot support processors with extended
CPUID functions. The options are Enabled and Disabled (for the Windows OS.).

Execute-Disable Bit (if supported by the OS and the CPU)

Set to Enabled to enable the Execute Disable Bit which will allow the processor
to designate areas in the system memory where an application code can execute
and where it cannot, thus preventing a worm or a virus from flooding illegal codes
to overwhelm the processor or damage the system during an attack. The default is
Enabled. (Refer to Intel and Microsoft Web Sites for more information.)
Intel® AES-NI (If supported by the CPU)
Set to Enabled to use the processor's Advanced Encryption Standard (AES) feature.
The options are Enabled and Disabled.

MLC Streamer Prefetcher (if supported by the CPU)

If set to Enabled, the hardware pre fetcher will pre fetch streams of data and instruc-
tions from the main memory to the L2 cache in the forward or backward manner to
improve CPU performance. The options are Disabled and Enabled.

MLC Spatial Prefetch (if supported by the CPU)

The CPU fetches the cache line for 64 bytes if this option is set to Disabled. The
CPU fetches both cache lines for 128 bytes as comprised if Enabled.

DCU Streamer Prefetcher

This feature enables prefetch of the next L1 data line based on multiple loads in
the same cache line. The options are Enabled and Disabled.

DCU IP Prefetcher

Set this feature to Enabled to activate the L1 Data Prefetcher based on sequential
load history. The options are Enabled and Disabled.
4-6