D-Ram Refreshment Controller; Figure 2-27. D-Ram Cycle Timings; Table 2-10. Junction Method (Cpu-2Cas Dram); Figure 2-28. Junction Method (Cpu-Dram) - Epson 4003353 Service Manual

D-RAM Refreshment Controller

2.3.2.7
The H8 CPU is eauimxd with a the refresh controller into the internal mntroller. This CPU can
contact the 16-bit ien'~ IC5 D-RAM which is a 2 CAS type. The fallowing table lists the
method between the H8 CPU and the 2 CAS BRAM.

Table 2-10. Junction Method (CPU-2CAS DRAM)

*
method of the D-RAM reikeshment is only
The
following figure shows the timing of each cycle.
I
. . . . . . . . . . . . . . . . . . . . . .
AS
1
(Read / Write Cycle)
CPU H8 (ICI)
I

Figure 2-28. Junction Method (CPU-DRAM)

2-22
CPU
used to the CAS befbre RAS cycle method. The
I
I
Read Cycle
Write Cycle
I
J

Figure 2-27. D-RAM Cycle Timings

79
LWR , ~,
7 8
2 CAS D-RAM
(Refresh Cycle)
D-RAM (IC5)
28
2 7 + M
O E
J
Rev. A