Dram Clock/Drive Control; Dram Timing - VIA Technologies EX10000EG - VIA EPIA Motherboard User Manual

Chapter 3
DRAM C
LOCK
DRAM Clock

DRAM Timing

x SDRAM CAS Latency [DDR/DDR
x Bank Interleave
x Precharge to Active(Trp)
x Active to Precharge(Tras)
x Active to CMD(Trcd)
x REF to ACT/REF (Trfc)
x ACT(0) to ACT(1) (TRRD)
Read to Precharge (Trtp)
Write to read CMD (Twtr)
Write Recovery Time (Twr)
RDSAIT mode
x RDSAIT selection
: Move
F5: Previous Values
DRAM Clock
The chipset supports synchronous and asynchronous mode between host
clock and DRAM clock frequency.
Settings: [By SPD, 100 MHz, 133 MHz, 166 MHz, 200MHz, 266MHz, 333MHz
DRAM Timing
The value in this field depends on the memory modules installed in your
system. Changing the value from the factory setting is not recommended
unless you install new memory that has a different performance rating than
the original modules.
Settings: [Manual, Auto By SPD]
/D C
RIVE ONTROL
Phoenix - AwardBIOS CMOS Setup Utility
PnP / PCI Configurations
[By SPD]
[Auto By SPD]
2.5 / 4
Disabled
4T
07T
4T
25T
3T
[2T]
[1T/2T]
[4T]
[Auto]
03
Enter: Select +/-/PU/PD: Value
F6: Fail-Safe Defaults
F10: Save ESC: Exit
F7: Optimized Defaults
60
Item Help
Menu Level
F1: General Help