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DRAM C
LOCK
DRAM Clock
DRAM Timing
SDRAM CAS Latency [DDR/DDR2]
Bank Interleave
Precharge to Active(Trp)
Active to Precharge(Tras)
Active to CMD(Trcd)
REF to ACT/REF (Trfc)
ACT(0) to ACT(1) (TRRD)
Read to Precharge (Trtp)
Write to read CMD (Twtr)
Write Recovery Time (Twr)
RDSAIT mode
x RDSAIT selection
: Move
F5: Previous Values
DRAM Clock
The chipset supports synchronous and asynchronous mode between host
clock and DRAM clock frequency.
Settings: [By SPD, 100 MHz, 133 MHz, 166 MHz, 200MHz, 266MHz, 333MHz]
DRAM Timing
The value in this field depends on the memory modules installed in your
system. Changing the value from the factory setting is not recommended
unless you install new memory that has a different performance rating than
the original modules.
Settings: [Manual, Auto By SPD]
SDRAM CAS Latency [DDR/DDR2]
Settings: [1.5/2, 2/3, 2.5/4, 3/5]
Bank Interleave
Settings: [Disabled, 2 Bank, 4 Bank, 8 Bank]
Precharge to Active (Trp)
Settings: [2T, 3T, 4T, 5T]
/D
C
RIVE
ONTROL
Phoenix - AwardBIOS CMOS Setup Utility
PnP / PCI Configurations
[By SPD]
[Manual]
[2.5 / 4]
[Disabled]
[4T]
[07T]
[4T]
[25T]
[3T]
[2T]
[1T/2T]
[4T]
[Auto]
03
Enter: Select
+/-/PU/PD: Value
F6: Fail-Safe Defaults
Menu Level
F10: Save
ESC: Exit
F7: Optimized Defaults
BIOS Setup
Item Help
F1: General Help
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