Dram Clock/Drive Control - VIA Technologies EPIA User Manual

Chapter 3
DRAM C /D C
LOCK RIVE ONTROL
DRAM Clock
Set the DRAM Clock.
Settings: [Host CLK, HCLK-33M, By Auto]
DRAM Timing By SPD
Set the DRAM Timing by SPD.
Settings: [Disabled, Enabled]
SDRAM Cycle Length
Set the DRAM Cycle Length.
Settings: [3, 2]
Bank Interleave
Set the Bank Interleave mode.
Settings: [Disabled, 2 Bank, 4 Bank]
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