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DRAM C
LOCK
Current FSB Frequency
Current DRAM Frequency
DRAM Clock
DRAM Timing
SDRAM CAS Latency
Bank Interleave
Precharge To Active (Trp)
Active to Precharge (Tras)
Active to CMD (Trcd)
REF to ACT/REF to REF (Trfc)
ACT(0) to ACT(1) (TRRD)
DRAM Command Rate
: Move
Enter: Select
F5: Previous Values
Current FSB Frequency
This setting specifies the maximum operating frequency of the link's
transmitter clock.
Current DRAM Frequency
This setting specifies the maximum memory clock limit on the system.
DRAM Clock
This item allows you to set the speed of Direct Memory Access (DMA) at
either equal to or one-half of the SYSCLK (system clock signal) speed.
Settings: [By SPD, 100MHz, 133MHz, 166MHz, 200MHz]
Note: While speed is always desirable, choosing the higher setting
may prove to be too fast for some components.
/ D
C
RIVE
ONTROL
Phoenix - Award WorkstationBIOS CMOS Setup Utility
DRAM Clock/Drive Contorl
133MHz
200MHz
[By SPD]
[Auto By SPD]
2.5
Disabled
4T
9T
4T
15T
3T
[2T Command]
+/-/PU/PD: Value
F6: Fail-Safe Defaults
Menu Level
F10: Save
ESC: Exit
F7: Optimized Defaults
43
BIOS Setup
Item Help
F1: General
Help
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