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Chapter 3
Pin # Signal
39
FPDEN
40
FP0
41
FPCLKS
42
VEEON
43
ENVDD
44
FPVS
45
ENVEE
46
FPHS
47, 48
GND
49, 50
+12V
Notes: The shaded area denotes power or ground.
LVDS Interface (J7)
Table 3-22. LVDS Interface Pin/Signal Descriptions (J7)
Pin # Signal
1
3.3V_Panel
2
5V_Panel
3
GND
4
GND
5
LVDS_Y0M
6
LVDS_Y0P
7
LVDS_Y1M
8
LVDS_Y1P
9
LVDS_Y2M
10
LVDS_Y2P
11
LVDS_CLKYM
12
LVDS_CLKYP
13
LVDS_Z0M
14
LVDS_Z0P
15
LVDS_Z1M
16
LVDS_Z1P
17
LVDS_Z2M
18
LVDS_Z2P
19
LVDS_CLKZM
20
LVDS_CLKZP
Notes: The shaded area denotes power or ground.
NOTE
Pins 5-12 constitute 1
single channel interface. Pins 13-20 constitute 2
interface of a two channel interface.
48
Description
Flat Panel Data Enable – This signal to settle the horizontal display position.
Flat Panel Data Output 0 – Refer to pin-2 for more information.
Flat Panel Shift clock – This signal can be inverted by jumper JP1.
Voltage On – This signal is high (+5V) when ENVEE & Power Good are High
Flat Panel Enable VDD – This is power sequencing output for LCD driver
Flat Panel VSync (FLM) – This signal is digital monitor equivalent of VSYNC
Flat Panel Enable VEE – This signal is used for power sequencing
Flat Panel HSync (LP) – This signal is the digital monitor equivalent of HSYNC
Ground
+12V (this voltage is supplied externally from the AT/ATX power supply input
connector. It may also be used by the PCI bus or ISA bus.
Description
+3.3V source
+5V source
Ground
Ground
Data Negative Output
Data Positive Output
Data Negative Output
Data Positive Output
Data Negative Output
Data Positive Output
Clock Negative Output
Clock Positive Output
Data Negative Output
Data Positive Output
Data Negative Output
Data Positive Output
Data Negative Output
Data Positive Output
Clock Negative Output
Clock Positive Output
st
channel interface of two channels, or a
Reference Manual
Line
Channel
NA
NA
0
1
Channel 1
2
Clock
0
1
Channel 2
2
Clock
nd
channel
Hardware
ReadyBoard 700
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