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Chapter 3
Pin #
Signal
25 (A25)
SA6
26 (A26)
SA5
27 (A27)
SA4
28 (A28)
SA3
29 (A29)
SA2
30 (A30)
SA1
31 (A31)
SA0
32 (A32)
GND
Notes: The shaded area denotes power or ground. The signals marked with * = Negative true logic.
Table 3-6. PC/104 Interface Pin/Signal Descriptions (J13B)
Pin #
Signal
33 (B1)
GND
34 (B2)
RESETDRV Reset Drive – This signal is used to reset or initialize system logic on
35 (B3)
+5V
36 (B4)
IRQ9
37 (B5)
-5V
38 (B6)
DRQ2
39 (B7)
-12V
40 (B8)
ENDXFR*
41 (B9)
+12V
42 (B10)
GND
43 (B11)
SMEMW*
44 (B12)
SMEMR*
45 (B13)
IOW*
46 (B14)
IOR*
47 (B15)
DACK3*
ReadyBoard 700
Description (J13 Row A)
System Address 6 – Refer to SA19, pin-A12, for more information.
System Address 5 – Refer to SA19, pin-A12, for more information.
System Address 4 – Refer to SA19, pin-A12, for more information.
System Address 3 – Refer to SA19, pin-A12, for more information.
System Address 2 – Refer to SA19, pin-A12, for more information.
System Address 1 – Refer to SA19, pin-A12, for more information.
System Address 0 – Refer to SA19, pin-A12, for more information.
Ground
Descriptions (J13 Row B)
Ground
power up or subsequent system reset.
+5 volt power ±10%
Interrupt request 9 – Asserted by a device when it has pending interrupt
request. Only one device may use the request line at a time.
Not connected (-5 volts)
DMA Request 2 – Used by I/O resources to request DMA service, or to
request ownership of the bus as a bus master device. Must be held high
until associated DACK2 line is active.
Not connected (-12 volts)
Zero Wait State – This signal is driven low by a bus slave device to
indicate it is capable of performing a bus cycle without inserting any
additional wait states. To perform a 16-bit memory cycle without wait
states, this signal is derived from an address decode.
+12 Volts
Not connected (Key Pin)
System Memory Write – This signal is used by bus owner to request a
memory device to store data currently on the data bus and only active
for the lower 1MB. Used for legacy compatibility with 8-bit cards.
System Memory Read – This signal is used by bus owner to request a
memory device to drive data onto the data bus and only active for lower
1MB. Used for legacy compatibility with 8-bit cards.
I/O Write – This strobe signal is driven by the owner of the bus (ISA
bus master or DMA controller) and instructs the selected I/O device to
capture the write data on the data bus.
I/O Read – This strobe signal is driven by the owner of the bus (ISA bus
master or DMA controller) and instructs the selected I/O device to drive
read data onto the data bus.
DMA Acknowledge 3 – Used by DMA controller to select the I/O
resource requesting the bus, or to request ownership of the bus as a bus
master device. Can also be used by the ISA bus master to gain control
of the bus from the DMA controller.
Reference Manual
Hardware
29
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