Pg Motor Driver Circuit; Figure 2-29. Pg Motor Driver Circuit - Epson C117001-N - DFX 5000+ B/W Dot-matrix Printer Service Manual

Operating Principles

2.3.7 PG Motor Driver Circuit

Figure 2-29 shows a block diagram of the PG motor driver circuit, and Table 2-8 provides PG motor
specifications. The motor phase switching signals are output from the PGA port and input to the
(+35 VDC) and hold mode (+5 VDC) using the pulses from port PGI of the gate array. The phase
driver IC (QM2) is turned on when the motor pulse switching data is LOW.
The phase A output pulse from the platen gap encoder (ENCA) is input to general purpose port
to general purpose port ENCB of the gate array. The gate array counts these pulses using the
internal counter and determines the amount and direction of motor rotation.
E05A67
Z z
c-) (-l
encoder
(on the CARRIAGE)
Specification
Form
Supply voltage
Internal coil resistance
Current consumption
Frequency
2-32
PGAN
gap .

Figure 2-29. PG Motor Driver Circuit

Table 2-9. PG Motor Specifications
I
4-phase, 48-pole, PM pulse motor
35 VDC * 60/0 (applied to the driver circuit)
I
Driving: 0.20 A (average)
Holding: 0.02 A * 0.5 mA
333 pps
15,16
13,14
B2
11,12
B3
9,10
B4
,
Description
VP or +5
Rev. A