Abov MC96F1206 Manuals

Manuals and User Guides for Abov MC96F1206. We have 1 Abov MC96F1206 manual available for free PDF download: User Manual

Abov MC96F1206 User Manual (133 pages)

CMOS single-chip 8-bit MCU with 12-bit ADC and LDO

Brand: Abov | Category: Microcontrollers | Size: 4 MB

Figure 1. MC96F1206 Block Diagram
1
Table of Contents
2
Device Overview
8
Table 1. MC96F1206 Device Features and Peripheral Counts
8
Block Diagram
10
Figure 2. MC96F1206 Block Diagram
10
Pinouts and Pin Descriptions
11
Pinouts
11
Figure 3. MC96F1206AEN 16 SOPN Pinouts
11
Figure 4. MC96F1206 20TSSOP Assignment
12
Figure 5. MC96F1206 16SOPN Assignment
12
Pin Description
13
Table 2. 16 SOPN Pin Description
13
GPIO Port Structure
15
Figure 6. General Purpose I/O Port Structure
15
External Interrupt I/O Port Structure
16
Figure 7. External Interrupt I/O Port Structure
16
Memory Organization
17
Program Memory
17
Internal Data Memory
18
Figure 8. Program Memory
18
Figure 9. Internal Data Memory Map
19
Extended SFR Area
20
SFR Map
20
Figure 10. Lower 128 Bytes Internal RAM
20
SFR Map Summary
21
SFR Map
21
Table 3. SFR Map Summary
21
Table 4. SFR Map
21
8051 Compiler Compatible SFR Map
26
I/O Ports
28
Port Registers
28
Data Register (Px)
28
Direction Register (Pxio)
28
Pull-Up Register Selection Register (Pxpu)
28
Open-Drain Selection Register (Pxod)
28
Port Function Selection Register (PSR0,PSR2,PSR3)
28
Pin Change Interrupt Enable Register (PCI)
29
Register Map
29
Port P0
29
Port Description of P0
29
Table 5. Port Register Map
29
Register Description of P0
30
Port P1
31
Port Description of P1
31
Register Description of P1
31
Port P2
32
Port Description of P2
32
Register Description of P2
32
Interrupt Controller
35
External Interrupt
36
Pin Change Interrupt
36
Figure 11. Interrupt Group Priority Level
36
Figure 12. External Interrupt Description
37
Figure 13. PCI Interrupt Description
37
Interrupt Controller Block Diagram
38
Interrupt Vector Table
38
Figure 14. Interrupt Controller Block Diagram
38
Interrupt Sequence
39
Table 6. Interrupt Vector Address Table
39
Table 7. LJMP Description and Example Code
40
Figure 15. Interrupt Sequence Flow
41
Effective Timing after Controlling Interrupt Bit
42
Multi Interrupt
42
Figure 16. Case A: Effective Timing of Interrupt Enable Register
42
Figure 17. Case B: Effective Timing of Interrupt Flag Register
42
Interrupt Enable Accept Timing
43
Figure 18. Effective Timing of Multi Interrupt
43
Interrupt Service Routine Address
44
Saving/ Restore General-Purpose Registers
44
Figure 19. Interrupt Response Timing Diagram
44
Figure 20. Correspondence between Vector Table Address and ISR Entry Address
44
Interrupt Timing
45
Figure 21. Saving and Restore Process Diagram and Example Code
45
Interrupt Register
46
Interrupt Enable Registers (IE, IE1)
46
Interrupt Priority Registers (IP, IP1)
46
External Interrupt Flag Register (EIFLAG)
46
Figure 22. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
46
External Interrupt Polarity Registers (EIPOL0, EIPOL1)
47
6.12.5 Register Map
47
6.12.6 Interrupt Register Description
47
Table 8. Interrupt Register Map
47
Block Diagram
51
Register Map
51
Register Description
51
Figure 23. Clock Generator in Block Diagram
51
Table 9. Clock Generator Register Map
51
Block Diagram
53
Register Map
53
Register Description
53
Figure 24. Basic Interval Timer in Block Diagram
53
Table 10. Basic Interval Timer Register Map
53
Table 11. BIT Period Table
54
Block Diagram
55
WDT Interrupt Timing Waveform
55
Figure 25. Watchdog Timer in Block Diagram
55
Register Map
56
Figure 26. Watchdog Timer Interrupt Timing Waveform
56
16-Bit Timer/ Counter Mode
58
16-Bit Capture Mode
59
Figure 27. 16-Bit Timer/ Counter Mode of TIMER 0/1
59
Figure 28. 16-Bit Timer/ Counter 0/1 Interrupt Example
59
Figure 29. 16-Bit Capture Mode of TIMER 0/1
60
Figure 30. Input Capture Mode Operation of TIMER 0/1
61
Figure 31. Express Timer Overflow in Capture Mode
61
PWM Mode
62
Figure 32. Pwmx Mode Block Diagram
62
Table 12. PWM Frequency Vs. Resolution at 16Mhz and 32Mhz
62
Timer Data and Period/Duty Write
63
Figure 33. Example of PWM at 8Mhz
63
Figure 34. Example of PWM at 8Mhz(Duty=Period)
63
Register Map
64
Figure 35. Timer X Compare Data Write
64
Table 13. TIMER 0 Register Map
64
Register Description for Timer/Counter X
65
Bit A/D Converter
69
Block Diagram
70
Figure 36. ADC Block Diagram
70
Figure 37. A/D Analog Input Pin Connecting Capacitor
70
ADC Operation
71
Figure 38. ADC Operation for Align Bit
71
Figure 39. Converter Operation Flow
72
Register Map
73
Register Description for ADC
73
Table 14. ADC Register Map
73
Power down Operation
76
Peripheral Operation in IDLE/STOP Mode
76
Table 15. Peripheral Operation During Power down Mode
76
IDLE Mode
77
STOP Mode
77
Figure 40. IDLE Mode Release Timing by External Interrupt
77
Release Operation of STOP1,2 Mode
78
Figure 41. STOP Mode Release Timing by External Interrupt
78
Figure 42. STOP Mode Release Flow
78
Register Map and Register Description for Power down Operation
79
Register Description
79
Table 16. Power-Down Operation Register Map
79
Table 17. Example Code with 3 or more NOP Instructions
79
Reset Block Diagram
80
Power on Reset
80
Figure 43. Reset Block Diagram
80
Table 18. Reset Value and the Relevant on Chip Hardware
80
Figure 44. Fast VDD Rising Time
81
Figure 45. Internal Reset Release Timing on Power-Up
81
Figure 46. Configuration Timing When Power-On
81
Figure 47. Boot Process Waveform
82
Table 19. Boot Process Description
83
External RESETB Input
84
Figure 48. Timing Diagram after RESET
84
Figure 49. Reset Noise Canceller Time Diagram
84
Low Voltage Indicator Processor
85
13.4.1 Block Diagram
85
Figure 50. Oscillator Generating Waveform Example
85
Figure 51. LVI Block Diagram
85
13.4.2 Internal Reset and LVD Reset in Timing Diagram
86
Register Map
86
Register Description
86
Figure 52. Internal Reset at Power Fail Situation
86
Table 20. Reset Operation Register Map
86
Flash Program ROM Structure
89
Figure 53. Flash Memory Map
89
Figure 54.Address Configuration of Flash Memory
89
Register Map
90
Register Description
90
Table 21. Flash Memory Register Map
90
Table 22. Program/Erase Time
92
Serial In-System Program (ISP) Mode
93
14.4.1 Flash Operation
93
Figure 55.The Sequence of Page Program and Erase of Flash Memory
93
Figure 56. the Sequence of Bulk Erase of Flash Memory
94
14.4.2 Flash Read
95
14.4.3 Enable Program Mode
95
14.4.4 Flash Write Mode
95
14.4.5 Flash Page Erase Mode
96
14.4.6 Flash Bulk Erase Mode
96
14.4.7 Flash OTP Area Read Mode
96
14.4.8 Flash OTP Area Write Mode
97
14.4.9 Flash OTP Area Erase Mode
97
14.4.10 Flash Program Verify Mode
97
14.4.12 OTP Program Verify Mode
98
14.4.13 Flash Erase Verify Mode
98
14.4.14 Flash Page Buffer Read
98
Summary of Flash Program/Erase Mode
98
Security
98
Table 23.Operation Mode
98
Table 24.Security Policy Using Lock-Bits
99
Electrical Characteristics
100
Absolute Maximum Ratings
100
Table 25.Absolute Maximum Ratings
100
Recommended Operating Conditions
100
Table 26.Recommended Operating Conditions
100
A/D Converter Characteristics
101
Low Drop out Characteristics
101
Power-On Reset Characteristics
101
Table 27.Low Drop out Characteristics
101
Table 28.Power-On Reset Characteristics
101
Low Voltage Reset and Low Voltage Indicator Characteristics
102
Internal RC Oscillator Characteristics
102
Table 29.LVR and LVI Characteristics
102
Table 30.Internal RC Oscillator Characteristics
102
Internal WDT Oscillator Characteristics
103
DC Characteristics
103
Table 31.Internal WDT Oscillator Characteristics
103
Table 32.DC Characteristics
103
AC Characteristics
104
Figure 57. AC Timing
104
Table 33.AC Characteristics
104
Operating Voltage Range
105
Typical Characteristics
105
Figure 58. Operating Voltage Range
105
Output Low Voltage(VOL) Figure 60. Output High Voltage (VOH1)
105
Recommended Application Circuit
106
Output High Voltage (VOH2) Figure 62.Power Supply Current (RUN, IDLE)
106
Figure 63. Power Supply Current (STOP1, STOP2)
106
Figure 64. IRC Tolerance
106
Figure 65. Recommended Power Circuit Part When Using DC Power
107
Development Tools
108
Compiler
108
OCD (On-Chip Debugger) Emulator and Debugger
108
Figure 66. OCD and Pin Descriptions
108
Programmer
109
Figure 67. E-PGM+ (Single Writer) and Pin Descriptions
109
MTP Programming
110
Figure 68. E-Gang4 and E-Gang6 (for Mass Production)
110
Table 34.Specification of E-Gang4 and E-Gang6
110
Table 35. Pins for MTP Programming
110
Circuit Design Guide
111
16.5.1 On-Chip Debug System
111
Figure 69. PCB Design Guide for On-Board Programming
111
Figure 70. On-Chip Debugging System in Block Diagram
112
Table 36. Features of OCD
112
16.5.2 Two-Pin External Interface
113
Figure 71. 10-Bit Transmission Packet
113
Figure 72. Data Transfer on Twin Bus
114
Figure 73. Bit Transfer on Serial Bus
114
Figure 74. Start and Stop Condition
114
Figure 75. Acknowledge on Serial Bus
115
Figure 76. Clock Synchronization During Wait Procedure
115
16.5.3 Connection of Transmission
116
Figure 77. Connection of Transmission
116
Package Information
117
Figure 78. 20QFN Package Outline
117
Figure 79. 20 TSSOP Package Outline
118
Figure 80. 16SOPN Package Outline
119
Figure 81. MC96F1206 Device Numbering Nomenclature
120
Table 37. MC96F1206 Device Ordering Information
120
Configure Option
121
Instruction Table
122
Table 38. Instruction Table: Arithmetic
122
Table 39. Instruction Table: Logical
123
Table 40. Instruction Table: Data Transfer
124
Table 41. Instruction Table: Boolean
125
Table 42. Instruction Table: Branching
126
Table 43. Instruction Table: Miscellaneous
126
Table 44. Instruction Table: Additional Instructions
127
Flash Protection for Invalid Erase/ Write
128
How to Protect the Flash
128
Figure 82. Flash Protection against Abnormal Operations
128
Protection Flow Description
129
Figure 83. Flowchart of Flash Protection
130
Other Protection by the Configure Options
131
Revision History
132

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