ST STM32U3 Application Note page 5

Figure 2. STM32U375xxxxQ and STM32U385xxxxQ power supply overview (with SMPS)
In devices without SMPS, the V
block. The V
CORE
Note: If the selected package has the SMPS step-down converter option but the SMPS is not used by the application
(and the embedded LDO is used instead), the SMPS power supply pins must be set as follows:
• VDDSMPS and VLXSMPS connected to VSS
• VDD11 pins connected to VSS through one 4.7 µF to two 2.2 µF capacitors as in normal mode
2.1.1 Independent analog peripherals supply
To improve ADC and DAC conversion accuracy and to extend the supply flexibility, the analog peripherals have
an independent power supply that can be separately filtered and shielded from noise on the PCB.
The voltage supply input of the analog peripherals is available on a separate VDDA pin. An isolated supply
ground connection is provided on VSSA pin.
The V supply voltage can be different from V
DDA
logically and electrically isolated and therefore are not available. The isolation must be removed before using
these peripherals, by setting the ASV bit in PWR_SVMCR, once the V
The V supply can be monitored by analog voltage monitors (AVM), and compared with two thresholds
DDA
(1.6 V for AVM1 or 1.8 V for AVM2). For more details, refer to the device datasheet and section Peripheral voltage
monitoring (PVM) of document [1].
When a single supply is used, the VDDA pin can be externally connected to the same V
external filtering circuit, to ensure a noise-free V
AN6011 - Rev 1
V
VDDA
VSSA
Operational amplifiers
Voltage reference buffer
VDDUSB
VSS
V
V
VDDIO2
VSS
V domain
DD
V
DDIO1
Reset block
Internal RC oscillators
Standby circuitry
VSS
(Wake-up logic, IWDG)
VDD
Voltage regulator
LDO regulator
1-2 x VDD11
VLXSMPS
SMPS regulator
VDDSMPS
VSSSMPS
Low-voltage detector
V
SW
VBAT
LSE crystal 32 kHz oscillator
LSI 32 kHz oscillator
Backup registers
RCC_BDCR and PWR_BDCR registers
RTC
TAMP
supply source feeds the I/Os and system analog peripherals such as reset
DD
power supply for digital peripherals and memories is generated from the LDO.
domain
DDA
A/D converters
Comparators
D/A converters
USB transceiver
domain
DDIO2
DDIO2
I/O ring
PG[15:2]
I/O ring
V domain
CORE
Core
SRAM1
SRAM2
V
Digital
CORE
peripherals
Flash memory
Backup domain
. After reset, the analog peripherals supplied by V
DD
DDA
reference voltage.
DD
Power supply management
DDA
supply is present.
supply, through an
DD
AN6011
are
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