ST STM32U3 Application Note page 10

Note: • SMPS and LDO regulators provide, in a concurrent way, the V
requirements. However, only one of them is active at the same time. When SMPS is active, it feeds the
V
CORE
4.7 μF capacitor on packages with one VDD11 pin, or two 2.2 μF capacitors on packages with two VDD11
pins are then required. When LDO is active, it provides the V
decoupling capacitors on VDD11 pins.
• It is recommended to add a decoupling capacitor of 100 nF near each VDD11 pin/ball, but it is not
mandatory.
2.3 Power supply sequence between V
2.3.1 Power supply isolation
The devices feature a powerful reset system that ensures the main power supply (V
operating range before releasing the MCU reset.
This reset system is also in charge of isolating the independent power domains: V
This reset system is supplied by V
worse‑case conditions).
AN6011 - Rev 1
Figure 4. Power supply scheme for STM32U375/385xx (without SMPS)
VBAT
1.65 – 3.6 V
3.3 V
VDDUSB
100 nF
4.7 µF
V
DD
n x VDD
n x 100 nF
GPIOs
+ 1 x 10 µF
n x VSS
V
DDIO2
m x VDDIO2
m x 100 nF
+ 4.7 µF
GPIOs
m x VSS
V
DDA
V
REF
100 nF
+1 µF
100 nF+ 1 µF
on the two VDD11 pins provided through the SMPS VLXSMPS output pin. A 2.2 µH coil and a
and is not functional before V
DD
VCAP Power switch
LDO
regulator
V
DDIO1
OUT
IN
V
DDIO2
OUT
IN
VDDA
ADCs/
DACs/
V
REF+
OPAMPs/
V
REF-
COMPs/
VREFBUF
VSSA
CORE
CORE
, V , V
DDA DDUSB
reaches a minimal voltage (1 V in
DD
Power supply management
Backup circuitry
(LSE, RTC, TAMP
backup registers)
V
CORE
V
CORE
Kernel logic
(CPU, digital
I/O
and
logic
memories)
I/O
logic
supply depending on application
and regulates it using the same
, and V
DDIO2 DD
) has reached a valid
DD
, V , V
DDA DDUSB DDIO2
AN6011
, and V .
DD
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