Intel Altera Agilex 7 Manuals

Manuals and User Guides for Intel Altera Agilex 7. We have 2 Intel Altera Agilex 7 manuals available for free PDF download: User Manual

Intel Altera Agilex 7 User Manual

Intel Altera Agilex 7 User Manual (72 pages)

SoC FPGA Boot

Brand: Intel | Category: Computer Hardware | Size: 1 MB

Table of Contents

Table of Contents
2
Introduction
4
Glossary
4
Agilex 7 Soc FPGA Boot Overview
5
FPGA Configuration First Mode
6
Boot Flow Overview for FPGA Configuration First Mode
6
Power-On Reset (POR)
7
Secure Device Manager
8
First-Stage Bootloader
8
Second-Stage Bootloader
8
Operating System
9
Application
9
System Layout for FPGA Configuration First Mode
9
External Configuration Host Only
10
External Configuration Host with HPS Flash
10
Single SDM Flash
11
Related Information
12
FPGA Configuration - First Dual Flash System
12
HPS Boot First Mode
13
Boot Flow Overview
13
Power-On Reset (POR)
15
Secure Device Manager
15
First-Stage Bootloader
16
Second-Stage Bootloader
16
Operating System
17
Application
17
System Layout for HPS Boot First Mode
18
External Configuration Host Only
18
External Configuration Host with HPS Flash
19
Single SDM Flash
19
HPS Boot First - Dual Flash System
21
Creating the Configuration Files
22
Overview
22
Quartus Prime Hardware Project Compilation
23
Device and Pin Options
23
Platform Designer Options
24
Bootloader Software Compilation
24
Programming File Generator
25
Configuration over JTAG
26
FPGA Configuration First
26
HPS Boots First
26
Configuration from QSPI
27
Supported QSPI Devices
27
FPGA Configuration First
27
HPS Boot First
32
Configuration over AVST
37
FPGA Configuration First
37
HPS Boot First
40
Configuration Via Protocol
43
Creating Configuration Files from Command Line
44
Creating Configuration Files Using Graphical Interface
45
Remote System Update
48
Partial Reconfiguration
49
Related Information
51
Golden System Reference Design and Design Examples
52
Golden System Reference Design
52
Bootloader Examples
52
Additional Design Examples
52
Configuring the FPGA Fabric from HPS Software
54
Configuring the FPGA Fabric from U-Boot
54
Configuring the FPGA Fabric from Linux
54
FPGA Partial Reconfiguration from Linux
56
Debugging the Agilex 7 Soc FPGA Boot Flow
60
Reset
60
HPS Reset Pin
61
L4 Watchdog Timer 0
62
Debugging the HPS Bootloader Using the Arm DS Intel Soc FPGA Edition
62
Other Debug Considerations
62
Soc FPGA Boot User Guide Archives
66
Document Revision History for Agilex 7 Soc FPGA Boot User Guide
67
Boot Scratch Registers
68
Boot_Scratch_Cold0
68
Boot_Scratch_Cold1
68
Boot_Scratch_Cold2
69
Boot_Scratch_Cold3
69
Boot_Scratch_Cold4, Boot_Scratch_Cold5
69
Boot_Scratch_Cold6, Boot_Scratch_Cold7
69
Boot_Scratch_Cold8
70
Boot_Scratch_Cold9
72

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Intel Altera Agilex 7 User Manual

Intel Altera Agilex 7 User Manual (69 pages)

FPGA I-Series Transceiver (6xF-Tile) Development Kit

Brand: Intel | Category: Microcontrollers | Size: 6 MB

Table of Contents

Table of Contents
2
Overview
4
Ordering Information
4
Block Diagram
5
Feature Summary
5
Box Contents
6
Related Information
6
Recommended Operating Conditions
6
Getting Started
7
Before You Begin
7
Handling the Board
7
Software and Driver Installation
7
Installing the Quartus Prime Pro Edition Software
8
Installing the Intel Soc EDS
8
Installing the Development Kit
9
Installing the Intel FPGA Download Cable II Driver
10
Development Kit Setup
11
Default Settings
11
Powering up the Development Kit
12
Performing Board Restore
12
Restoring Board System MAX 10 with Default Factory Image
12
Restoring Board QSPI Flash with the Default Factory Image
13
Board Test System
14
Setting up the BTS GUI Running Environment
15
Downloading Openjdk
15
Downloading Openjfx
15
Installing Openjdk and Openjfx
15
Setting up the Quartus Prime Software for BTS Operation
16
Running the BTS GUI
16
BTS Functionalities
18
The Bottom Info Bar
18
The Configure Menu
18
The Sys Info Tab
19
Board Information
20
The GPIO Tab
20
The XCVR Tab
21
PMA Setting
23
Error Control
24
The Memory Tab
31
Performance Indicators
32
Test Control
32
Control On-Board Clock through Clock Controller GUI
34
Soft Reset
36
Monitor On-Board Power Regulator through Power Monitor GUI
37
Data Record
37
Identify Test Pass or Fail-Based on BTS GUI Test Status
38
Development Kit Hardware and Configuration
40
Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
40
Configuring the FPGA Device by Avalon Streaming Modes
40
Custom Projects for the Development Kit
41
Add Smartvid Settings in the Quartus Prime QSF File
41
Golden Top
41
Document Revision History for the Agilex 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide
42
Development Kit Components
43
Board Overview and Components
43
Board Overview
43
Board Components
44
System Management
45
Power
47
Power Tree
47
Clocks
48
General Input/Output
51
Memory Interfaces
55
Communication Interfaces
55
Daughter Cards
62
Developer Resources
63
Safety and Regulatory Compliance Information
64
Safety and Regulatory Information
64
Safety Warnings
65
Power Cord Requirements
66
Safety Cautions
66
Cooling Requirements
67
Electromagnetic Interference (Emi)
67
Electrostatic Discharge (ESD) Warning
68
Compliance Information
69
CE EMI Conformity Caution
69

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