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Intel Altera Agilex 7 User Manual
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Intel Altera Agilex 7 User Manual

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Agilex
7 SoC FPGA Boot User Guide
®
Updated for Quartus
Prime Design Suite: 22.4
683389
Online Version
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2024.08.28
UG-20294

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Summary of Contents for Intel Altera Agilex 7

  • Page 1 ™ Agilex 7 SoC FPGA Boot User Guide ® Updated for Quartus Prime Design Suite: 22.4 683389 Online Version Send Feedback 2024.08.28 UG-20294...

  • Page 2: Table Of Contents

    Contents Contents 1. Introduction........................4 1.1. Glossary.......................4 1.2. Agilex 7 SoC FPGA Boot Overview................5 2. FPGA Configuration First Mode..................6 2.1. Boot Flow Overview for FPGA Configuration First Mode..........6 2.1.1. Power-On Reset (POR)................7 2.1.2. Secure Device Manager................8 2.1.3. First-Stage Bootloader................8 2.1.4.
  • Page 3 7.1. Reset......................... 60 7.1.1. HPS Reset Pin..................61 7.1.2. L4 Watchdog Timer 0................62 7.2. Debugging the HPS Bootloader Using the Arm DS Intel SoC FPGA Edition....62 7.3. Other Debug Considerations.................. 62 8. SoC FPGA Boot User Guide Archives................66 9. Document Revision History for Agilex 7 SoC FPGA Boot User Guide......67 A.

  • Page 4: Introduction

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 5: Agilex 7 Soc Fpga Boot Overview

    1. Introduction 683389 | 2024.08.28 1.2. Agilex 7 SoC FPGA Boot Overview The Agilex 7 SoC FPGA combines an FPGA with a hard processor system (HPS) that is capable of booting Bare Metal applications or operating systems such as Linux*. When booting the device from a power-on reset, you can choose between two different methods of booting: •...

  • Page 6: Fpga Configuration First Mode

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 7: Power-On Reset (Por)

    2. FPGA Configuration First Mode 683389 | 2024.08.28 Table 2. FPGA Configuration First Stages The sections following this table describe each stage in more detail. Time Boot Stage Device State to T Power-on reset to T Secure Device Manager (SDM)- 1.

  • Page 8: Secure Device Manager

    U-Boot secondary program loader (SPL) — Intel provides the source code for U-Boot on GitHub. • Arm Trusted Firmware — Intel provides the source code for the Arm Trusted Firmware on GitHub. Related Information • Creating the Configuration Files on page 22 •...

  • Page 9: Operating System

    SDRAM. Depending on your application requirements, you may implement a conventional OS or an RTOS. Intel provides the Golden System Reference Design (GSRD) which includes the Linux kernel and a root filesystem built with Yocto recipes. Related Information...

  • Page 10: External Configuration Host Only

    2. FPGA Configuration First Mode 683389 | 2024.08.28 2.2.1. External Configuration Host Only Figure 2. External Configuration Host Only External Configuration Secure Device Hard Processor System (HPS) Host Manager (SDM) (AvST/JTAG) FPGA ® In this example, the external configuration host (Avalon streaming or JTAG) provides the SDM with a configuration bitstream that consist of: •...

  • Page 11: Single Sdm Flash

    2. FPGA Configuration First Mode 683389 | 2024.08.28 • SDM configuration firmware • FPGA I/O and HPS EMIF I/O configuration data • FPGA core configuration data • HPS FSBL code and HPS FSBL hardware handoff binary In this system layout, you can use the HPS flash to store the HPS SSBL, Linux image device tree information and OS file system.

  • Page 12: Related Information

    2. FPGA Configuration First Mode 683389 | 2024.08.28 Related Information • Agilex 7 Hard Processor System Technical Reference Manual For more information, refer to the Booting and Configuration Appendix • Agilex 7 SoC FPGA First Single QSPI Flash Boot 2.2.4. FPGA Configuration - First Dual Flash System In a dual flash system, the SDM flash stores the configuration bitstream, while the HPS flash stores the HPS SSBL and the rest of the OS files.

  • Page 13: Hps Boot First Mode

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 14 3. HPS Boot First Mode 683389 | 2024.08.28 Table 5. HPS Boot First Stages Time Boot Stage Device State Power-on reset to T SDM- Boot ROM 1. SDM samples the pins to determine the MSEL configuration and boot source. It also establishes the device security level based on eFuse values.

  • Page 15: Power-On Reset (Por)

    3. HPS Boot First Mode 683389 | 2024.08.28 Note: To avoid configuration failures, the Agilex 7 device requires clocks for the PCIe* and all E-tile transceiver reference clocks. You must provide the input reference clock, , and it must be free-running and stable at device power up for a successful refclk device configuration.

  • Page 16: First-Stage Bootloader

    U-Boot on GitHub. • Arm Trusted Firmware — Intel provides the source code for the Arm Trusted Firmware on GitHub. The latest source code is also available on the Intel public git repository. Related Information •...

  • Page 17: Operating System

    The SSBL loads the operating system (OS) stage into SDRAM. The OS executes from SDRAM. Depending on your application requirements you may implement a conventional OS or an RTOS. Intel provides the Golden System Reference Design (GSRD) which includes the Linux kernel and a root filesystem built with Yocto recipes. Related Information...

  • Page 18: System Layout For Hps Boot First Mode

    3. HPS Boot First Mode 683389 | 2024.08.28 3.2. System Layout for HPS Boot First Mode 3.2.1. External Configuration Host Only Figure 7. External Configuration Host Only External Configuration Secure Device Hard Processor System (HPS) Host Manager (SDM) (AvST/JTAG) FPGA In this example, the external configuration host (Avalon Streaming or JTAG) provides the SDM a configuration bitstream that consists of the following components: •...

  • Page 19: External Configuration Host With Hps Flash

    3. HPS Boot First Mode 683389 | 2024.08.28 3.2.2. External Configuration Host with HPS Flash Figure 8. External Configuration Host with HPS Flash HPS SD Card External HPS SSBL Configuration Secure Device Hard Processor System (HPS) Host Manager (SDM) Kernel Image (AvST/JTAG) and device tree FPGA Core &...
  • Page 20 3. HPS Boot First Mode 683389 | 2024.08.28 Depending on the boot stage that performs the FPGA configuration, you have the following options for storing the FPGA core and I/O configuration file: • An SDM flash storage partition—In this case the SSBL initiates configuration •...

  • Page 21: Hps Boot First - Dual Flash System

    3. HPS Boot First Mode 683389 | 2024.08.28 3.2.4. HPS Boot First - Dual Flash System In a dual flash system, the SDM flash such as an active serial flash stores the configuration bitstream. The HPS flash such as an SD card stores the HPS SSBL and the rest of the OS files.

  • Page 22: Creating The Configuration Files

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 23: Quartus Prime Hardware Project Compilation

    4. Creating the Configuration Files 683389 | 2024.08.28 Source Component Description Handoff Data for SDM Firmware Used to pass parameters to SDM firmware Handoff Data for HPS FSBL Used to pass parameter to HPS FSBL Quartus Prime SDM Firmware Located at the beginning of configuration bitstream and can be executed as part of the configuration.

  • Page 24: Platform Designer Options

    For more information about these settings, refer to the Agilex 7 HPS Component User Guide. Related Information Agilex 7 Hard Processor System Component Reference Manual 4.3. Bootloader Software Compilation Intel supports the following bootloaders: • U-Boot • UEFI For more information about the bootloaders, including how to configure and build for the various booting scenarios, refer to the BuildingBootloader web page on RocketBoards.

  • Page 25: Programming File Generator

    4. Creating the Configuration Files 683389 | 2024.08.28 4.4. Programming File Generator The tool that is used for creating the configuration files is called Programming File Generator. This tool is part of the Quartus Prime Programmer, which is included with the full Quartus Prime software installation.

  • Page 26: Configuration Over Jtag

    In this case, the configuration bitstream is sent to the device over JTAG with the help of the Quartus Prime Programmer. 4.5.1. FPGA Configuration First The following figure shows an overview of the process: Figure 12. Configuration over JTAG with FPGA Configuration First Intel® Quartus® Hardware Intel® Quartus® Intel® Quartus® JTAG SOF File...

  • Page 27: Configuration From Qspi

    The device configures itself with the bitstream which it reads from QSPI flash. This configuration method is also called “Active Serial x4” or “ASx4”. 4.6.1. Supported QSPI Devices For the list of supported QSPI devices, refer to the Intel Supported Configuration Devices web page. 4.6.2. FPGA Configuration First...
  • Page 28 4. Creating the Configuration Files 683389 | 2024.08.28 Figure 14. Configuration from QSPI using FPGA Configuration First Intel® Quartus® Hardware Intel® Quartus® Intel® Quartus® JTAG SOF File JIC File Prime Programming Board Project Prime Software Prime Programmer File Generator HPS Bootloader HPS FSBL Intel®...
  • Page 29 4. Creating the Configuration Files 683389 | 2024.08.28 • Input Files: — design.sof — fsbl.hex • Output Files: — design.jic — design.rpd — design.map The command parameters are listed below: Table 11. Command Parameters Parameter Description Location of HPS FSBL file in hex format hps_path Target QSPI device.
  • Page 30 4. Creating the Configuration Files 683389 | 2024.08.28 Figure 15. Quartus Prime Programming File Generator Pro Edition Window: Output Files 5. Switch to Input Files tab by clicking it. In the Input Files tab, do the following: a. Click the Add Bitstream button, browse to your SOF file, then click Open. b.
  • Page 31 4. Creating the Configuration Files 683389 | 2024.08.28 Figure 16. Quartus Prime Programming File Generator Pro Edition Window: Input Files 6. Switch to the Configuration Device tab by clicking it. In the Configuration Device tab, do the following: a. Click Add device, select your desired flash device (in this example MT25QU128) then click OK b.

  • Page 32: Hps Boot First

    FPGA fabric using the typically much larger phase 2 configuration bitstream. The following figure shows an overview of the process: Figure 18. Configuration from QSPI using HPS Boot First Phase 2 HPS Software Core RBF File Intel® Quartus® Hardware Intel® Quartus® Phase 1 Intel® Quartus® JTAG SOF File...
  • Page 33 4. Creating the Configuration Files 683389 | 2024.08.28 The following steps are involved: 1. Compile hardware project with Quartus Prime to obtain the SOF file. 2. Compile the HPS FSBL source code to obtain the HPS FSBL hex file, or use a precompiled one.
  • Page 34 4. Creating the Configuration Files 683389 | 2024.08.28 • Input Files: — design.sof — fsbl.hex • Output Files: — design.hps.jic — design.core.rbf — (optional) design.rpd — (optional) design.map The command parameters are listed below: Table 12. Command Parameters Parameter Description Location of HPS FSBL file in hex format hps_path Target QSPI device.
  • Page 35 4. Creating the Configuration Files 683389 | 2024.08.28 d. Optionally check the Memory Map File (.map) sub-option. e. Optionally check the Raw Programming Data (.rpd) sub-option. Click the Raw Programming Data (.rpd) sub-option (if checked above) then click Edit button and select the Bit swap option to be “on”. This ensures the file uses the natural byte format that can be used by 3rd party tools like U- Boot.
  • Page 36 4. Creating the Configuration Files 683389 | 2024.08.28 Figure 20. Quartus Prime Programming File Generator Pro Edition Window: Input Files 6. Switch to the Configuration Device tab by clicking it. In the Configuration Device tab, do the following: a. Click Add device, select your desired flash device (in this example MT25QU128) then click OK.

  • Page 37: Configuration Over Avst

    Boot configuration and device tree) and the OS (for example: Linux device tree). 4.7.1. FPGA Configuration First The following figure shows an overview of the process: Figure 22. Configuration over Avalon Streaming Using FPGA Configuration First Intel® Quartus® Hardware Intel® Quartus® External AVST...
  • Page 38 4. Creating the Configuration Files 683389 | 2024.08.28 The following steps are involved: 1. Compile hardware project with Quartus Prime to obtain the SOF file. 2. Compile the HPS FSBL source code to obtain the HPS FSBL hex file, or use a precompiled file.
  • Page 39 4. Creating the Configuration Files 683389 | 2024.08.28 Figure 23. Quartus Prime Programming File Generator Pro Edition Window: Output Files 5. Switch to Input Files tab by clicking it. In the Input Files tab, do the following: a. Click the Add Bitstream button, browse to your SOF file, then click Open. b.

  • Page 40: Hps Boot First

    HPS software can configure the FPGA fabric using the typically much larger phase 2 configuration bitstream. The following figure shows an overview of the process: Figure 25. Configuration over Avalon Streaming Using HPS Boot First Phase 1 Intel® Quartus® Intel® Quartus® Hardware External AVST SOF File...
  • Page 41 4. Creating the Configuration Files 683389 | 2024.08.28 • Raw Binary File (RBF): contains the small phase 1 configuration bitstream. • Core RBF File: contains the typically much larger phase 2 configuration bitstream, to be used by HPS software later to configure the fabric. a.
  • Page 42 4. Creating the Configuration Files 683389 | 2024.08.28 a. Change the output file Name to “design”. b. Check Raw Binary File for HPS Core Configuration (.rbf) option – the others are grayed out. Check Raw Binary File for Periphery Configuration (.rbf) sub-option. The Quartus Prime Programming File Generator window is displayed: Figure 26.

  • Page 43: Configuration Via Protocol

    PCIe interface quickly. Then, later, the PCIe host computer configures the fabric with the Core RBF file. Figure 28. Configuration over Protocol PCIE Core RBF File HPS Software Intel® Quartus® Intel® Quartus® Hardware Peripheral Intel® Quartus® JTAG SOF File...

  • Page 44: Creating Configuration Files From Command Line

    4. Creating the Configuration Files 683389 | 2024.08.28 The following steps are involved: 1. Compile hardware project with Quartus Prime to obtain the SOF file. 2. Compile the HPS FSBL source code to obtain the HPS FSBL hex file, or use a precompiled file.

  • Page 45: Creating Configuration Files Using Graphical Interface

    4. Creating the Configuration Files 683389 | 2024.08.28 Table 15. Command Parameters Parameter Description Location of HPS FSBL file in hex format hps_path Target QSPI device. Use a device listed in Supported QSPI Devices or use the graphical interface to device determine available options.
  • Page 46 4. Creating the Configuration Files 683389 | 2024.08.28 Figure 29. Quartus Prime Programming File Generator Pro Edition Window: Output Files 5. Switch to Input Files tab by clicking it. In the Input Files tab, do the following: a. Click the Add Bitstream button, browse to your SOF file, then click Open. b.
  • Page 47 4. Creating the Configuration Files 683389 | 2024.08.28 Figure 30. Quartus Prime Programming File Generator Pro Edition Window: Input Files 6. Switch to the Configuration Device tab by clicking it. In the Configuration Device tab, do the following: a. Click Add device, select your desired flash device (in this example MT25QU128) then click OK b.

  • Page 48: Remote System Update

    4. Creating the Configuration Files 683389 | 2024.08.28 Figure 31. Quartus Prime Programming File Generator Pro Edition Window: Configuration Device 7. Click the Generate button. Once the files are generated, a confirmation message is received. 8. Optionally, go to File Save or File Save As to save the configuration in file.

  • Page 49: Partial Reconfiguration

    4. Creating the Configuration Files 683389 | 2024.08.28 4.10. Partial Reconfiguration Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically, while the rest of the FPGA design continues to function. The portion that can be reconfigured is referred to as PR region while the FPGA design that is to be configured in the PR region is referred to as PR persona.
  • Page 50 The command used to create the RBF files is shown next: # Command to create personaX.rbf quartus_pfg -c personaX.pmsf personaX.rbf Figure 33. Process to Create the RBF File PR Build flow added to standard flow Intel® Quartus® PR Configuration PMFS Files Prime Programming Files Fille Generator personaX.pmfs...

  • Page 51: Related Information

    4. Creating the Configuration Files 683389 | 2024.08.28 Related Information FPGA Partial Reconfiguration from Linux on page 56 ™ Agilex 7 SoC FPGA Boot User Guide Send Feedback...

  • Page 52: Golden System Reference Design And Design Examples

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 53 5. Golden System Reference Design and Design Examples 683389 | 2024.08.28 • Agilex 7 SoC FPGA First Single QSPI Flash Boot • Agilex 7 SoC with eMMC Storage on HPS ™ Agilex 7 SoC FPGA Boot User Guide Send Feedback...

  • Page 54: Configuring The Fpga Fabric From Hps Software

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 55 If you want to test the FPGA reconfiguration at kernel level, make the following changes to the kernel source code: 1. In the file , add a second .dtb file. arch/arm64/boot/dts/intel/Makefile For example: dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb dtb-$(CONFIG_ARCH_AGILEX) += overlay.dtb 2. Create the new file and add the overlay information of the RBF file overlay.dts...

  • Page 56: Fpga Partial Reconfiguration From Linux

    6. Configuring the FPGA Fabric from HPS Software 683389 | 2024.08.28 If you want to re-apply the overlay, you have to first remove the existing overlay, and then re-run the previous steps: # rmdir /sys/kernel/config/device-tree/overlays/0 # mkdir /sys/kernel/config/device-tree/overlays/0 # echo overlay.dtb >/sys/kernel/config/device-tree/overlays/0/path 6.3.
  • Page 57 6. Configuring the FPGA Fabric from HPS Software 683389 | 2024.08.28 • pr_personaX.dtbo—This is the overlay for the PR Persona X and extends the fpga_pr_regionN node created in the PR Static Region overlay. This overlay is generated from the file. Here is where it is indicated which is pr_personaX.dts the RBF file that corresponds to the FPGA design to be loaded in the PR region (referred to as the...
  • Page 58 6. Configuring the FPGA Fabric from HPS Software 683389 | 2024.08.28 Figure 34. Components Involved As indicated before, to perform the partial reconfiguration from Linux, we make use of command which allows the device tree overlays handling. At the time that dtbt the overlay is applied, the PR is performed automatically, and the Linux driver associated to the overlay is loaded.
  • Page 59 6. Configuring the FPGA Fabric from HPS Software 683389 | 2024.08.28 3. If another PR persona wants to be loaded, the current PR persona overlay needs to be removed and then the new PR Persona overlay should be applied. root@agilex:~# dtbt -r pr_persona0.dtbo -p /boot/devicetree root@agilex:~# dtbt -a pr_persona1.dtbo -p /boot/devicetree root@agilex:~# dtbt -l Static region and persona1 overlays should be shown.

  • Page 60: Debugging The Agilex 7 Soc Fpga Boot Flow

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 61: Hps Reset Pin

    7. Debugging the Agilex 7 SoC FPGA Boot Flow 683389 | 2024.08.28 Reset Type Initiated By Details Warm Reset • FSBL or any software that makes a • Before you can write to the warm reset request through the RMR_EL3 register, CPU0 must EL3 register software write to the ensure that the other CPUs are in...

  • Page 62: L4 Watchdog Timer 0

    7.2. Debugging the HPS Bootloader Using the Arm DS Intel SoC FPGA Edition You can debug the bootloader by using Arm DS Intel SoC FPGA Edition. In order to do that, you need a JTAG connection, so you must enable the HPS Debug Access Port to be accessible through either the SDM or HPS pins.
  • Page 63 7. Debugging the Agilex 7 SoC FPGA Boot Flow 683389 | 2024.08.28 Data Trace Failure If your board fabrication facility does not perform bare board testing, you must perform these tests. To detect data trace failures on your memory interface, use a “walking ones"...
  • Page 64 7. Debugging the Agilex 7 SoC FPGA Boot Flow 683389 | 2024.08.28 Table 20. Address Trace Test (Powers of Two) Example Address Written Value Read Value Failure Detected 00000000 No failure detected. 00000001 No failure detected. 00000010 Error, the second address bit, , is stuck A[1] low.
  • Page 65 7. Debugging the Agilex 7 SoC FPGA Boot Flow 683389 | 2024.08.28 communication failure for the entire group of devices. To guarantee a stable connection, you must isolate the FPGA under test from the other devices in the same JTAG chain. Related Information •...

  • Page 66: Soc Fpga Boot User Guide Archives

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 67: Document Revision History For Agilex 7 Soc Fpga Boot User Guide

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 68: Boot Scratch Registers

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 69: Boot_Scratch_Cold2

    • ATF: — plat/intel/soc/agilex/bl31_plat_setup.c:bl31_platform_setup() ATF writes to the register to bring up the secondary Arm cores. A.6. BOOT_SCRATCH_COLD6, BOOT_SCRATCH_COLD7 Boot Scratch Agilex 7 F/I-Series...

  • Page 70: Boot_Scratch_Cold8

    SPL, it reads the register, and if equal to magic value 0x1228E5E7, then request a warm reset through RMR_EL3. — ATF: • writes plat/intel/soc/common/socfpga_psci.c:socfpga_system_reset2() magic value (0x1228E5E7) to the register L2_RESET_DONE_STATUS • plat/intel/soc/common/aarch64/plat_helpers.S: reads the register, and if equal to magic value...
  • Page 71 Flag to indicate a CPU power domain is about to be turned on (value = 1) • Usage — ATF: • plat/intel/soc/common/socfpga_psci.c socfpga_pwr_domain_on() Handler called when a power domain is about to be turned on. Bit[18] ACF DDR Data rate set by SDM Can be used as scratch memory.

  • Page 72: Boot_Scratch_Cold9

    A. Boot Scratch Registers 683389 | 2024.08.28 A.8. BOOT_SCRATCH_COLD9 Boot Scratch Agilex 7 F/I-Series Agilex 7 M-Series Register Boot_Scratch_Cold9 Bits[31:0] Stores the ECC DBE Address • Usage: — Linux • Set through the ATF SMC handler A.9. BOOT_SCRATCH_COLD0, BOOT_SCRATCH_COLD1, BOOT_SCRATCH_COLD8, BOOT_SCRATCH_COLD9 Arm Trusted Firmware (ATF) is configured as the SMC handler, and it allows these registers to be read, written, and updated by U-Boot and Linux.