Power Bypass Capacitor Layout - Realtek RTL8762C Hardware Instructions


There should be no signal trace under the buck inductor body, which means keeping copper
plane of the back layer (BOT) complete.

There is no GND copper between the pads of wire wound inductor.
(as yellow rectangular mark shown)

13.3 Power Bypass Capacitor Layout

1. The decoupling capacitor of VBAT must be placed near the input port of IC CHIP to ensure
return path back to GND without blocking.
2. The capacitor of VBAT should be connected to the GND layer through GND Via. Furthermore,
GND Via should be as close to the pad as possible in order to shorten the ground loop. (as
shown in the picture below)
3. The trace route must go to the capacitor first, and then go into the input pin of chip. It is
suggested that trace width is larger than 15mil.
RTL8762C Evaluation Board User Manual
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