Realtek RTL8762C Hardware Instructions page 16

RTL8762C Evaluation Board User Manual
value may be unstable. It is recommended to calculate average value after sampling multiple times.
If VCC itself fluctuates, it is suggested to place a larger capacitor on C2 to suppress fluctuations.
Divide mode (range: 0~3.3V)：
In this mode, at the moment of AUXADC sampling, the impedance between ADC pin P2_X and
Ground is the sum of Ra + Rb. AUXADC full-scale is 3.3V in this mode. When the input voltage
is 3.3~3.6V, the ADC value may be out of range, causing measurement error. Moreover, the
internal load impedance of ADC pin is ~500K. In the continuous sampling mode, the resistance of
Ra+Rb will be affected by the sampling rate. The higher the sampling rate is, the lower the
resistance is. Because the ADC load impedance is large, the sampled value is possible to fluctuate
under conditions of large external impedance. Hence, divide mode is not suitable for the
application which is connected to large external impedance.
VBAT channel is only available in Divide mode. Power supply voltage of VBAT pin can be tested
inside the chip.
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