Mfr_Config_All[6] Setting); Fault Detection And Handling - Analog Devices Linear ADI Power LTM4681 Manual

LTM4681
OPERATION
Table 4. ASEL_nn Pin Strapping Look-Up Table to Set the
LTM4681's Slave Address (Applicable Regardless of

MFR_CONFIG_ALL[6] Setting)

R * (kΩ)
ASEL
Open
32.4
22.6
18.0
15.4
12.7
10.7
9.09
7.68
6.34
5.23
4.22
3.24
2.43
1.65
0.787
0
Where:
R/W = Read/Write bit in control byte
All PMBus device addresses listed in the specification are 7 bits wide
unless otherwise noted.
Note: The LTM4681 will always respond to slave address 0x5A and 0x5B
regardless of the NVM or ASEL resistor configuration values.
*R value indicated is nominal. Select R
CFG
such that its value is always within 3% of the value indicated in the table.
Take into account resistor initial tolerance, T.C.R. and resistor operating
temperatures, soldering heat/IR reflow, and endurance of the resistor
over its lifetime. Thermal shock cycling, moisture (humidity) and other
effects (depending on one's specific application) could also affect R
value over time. All such effects must be taken into account in order for
resistor pin-strapping to yield the expected result at every SV
and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the
lifetime of one's product.
Example:
ASEL_
nn
R
ASEL
SGND_C0_C1
38
SLAVE ADDRESS
100_1111_R/W
100_1111_R/W
100_1110_R/W
100_1101_R/W
100_1100_R/W
100_1011_R/W
100_1010_R/W
100_1001_R/W
100_1000_R/W
100_0111_R/W
100_0110_R/W
100_0101_R/W
100_0100_R/W
100_0011_R/W
100_0010_R/W
100_0001_R/W
100_0000_R/W
from a resistor vendor
CFG
CFG
power-up
IN
PIN
For more information
Table 5. LTM4681 MFR_ADDRESS Command Examples
Expressed in 7- and 8-Bit Addressing
HEX DEVICE
ADDRESS
DESCRIPTION 7-BIT
4
Rail 0x5A
4
Global 0x5B
Default 0x4F
Example 1 0x40
Example 2 0x41
2,3
Disabled
Note 1: This table can be applied to the MFR_RAIL_ADDRESSn
commands, but not the MFR_ADDRESS command.
Note 2: A disabled value in one command does not disable the device,
nor does it disable the global address.
Note 3: A disabled value in one command does not inhibit the device
from responding to device addresses specified in other commands.
Note 4: It is not recommended to write the value 0x00, 0x0C (7-bit), 0x5A
(7-bit), 0x5B (7-bit) or 0x7C(7-bit) to the MFR_CHANNEL_ADDRESSn or
the MFR_RAIL_ADDRESSn commands.

FAULT DETECTION AND HANDLING

A variety of fault and warning reporting and handling
mechanisms are available. Fault and warning detection
capabilities include:
Input OV FAULT Protection and UV Warning
n
Average Input OC Warn
n
Output OV/UV Fault and Warn Protection
n
Output OC Fault and Warn Protection
n
Internal control Die and Internal Module
n
's
Overtemperature Fault and Warn Protection
Internal Undertemperature Fault and Warn Protection
n
CML Fault (Communication, Memory or Logic)
n
External Fault Detection via the Bidirectional FAULTn
n
Pins
In addition, the LTM4681 can map any combination of
fault indicators to their respective FAULTn pin using the
propagate FAULTn response commands, MFR_FAULT_
PROPAGATE. Typical usage of a FAULTn pin is as a
driver for an external crowbar device, overtemperature
alert, overvoltage alert or as an interrupt to cause a
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BIT
8-BIT 7 6 5 4 3 2 1 0 R/W
0xB4 0 1 0 1 1 0 1 0
0xB6 0 1 0 1 1 0 1 1
0x9E 0 1 0 0 1 1 1 1
0x80 0 1 0 0 0 0 0 0
0x82 0 1 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0
0
0
0
0
0
Rev. A