Config_All[6] = 1B) Top Resistor = 14.3K - Analog Devices Linear ADI Power LTM4681 Manual

LTM4681
OPERATION
The ASEL_nn pin settings are described in Table 4. ASEL_
nn selects slave address for the LTM4681 internal control-
ler. For more detail, refer to Table 5.
NOTE: Per the PMBus specification, pin programmed
parameters can be overridden by commands from the
digital interface with the exception of ASEL_nn which is
always honored. Do not set any part address to 0x5A or
0x5B because these are global addresses and all parts
will respond to them.
Table 1. VOUTn _CFG Pin Strapping Look-Up Table for the
LTM4681's Output Voltage, Coarse Setting (Not Applicable if
MFR_CONFIG_ALL[6] = 1b) Top Resistor = 14.3k
R * V
VOUTn_CFG
(kΩ) SETTING COARSE
Open
32.4
22.6
18.0
15.4
12.7
10.7
9.09
7.68
6.34
5.23
4.22
3.24
2.43
1.65
0.787
0
*R value indicated is nominal. Select R
VOUTn_CFG
vendor such that its value is always within 3% of the value indicated in the
table. Take into account resistor initial tolerance, T .C.R. and resistor operating
temperatures, soldering heat/IR reflow, and endurance of the resistor over its
lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending
on one's specific application) could also affect R
All such effects must be taken into account in order for resistor pin strapping
to yield the expected result at every SV
MFR_RESET or RESTORE_ USER_ALL, over the lifetime of one's product.
R = 14.3k is external to the part. Example:
TOP
V
DD25_nn
R
TOP
14.3k
R
VOUTn
SGND_
36
(V) MFR_PWM_
OUTn
MODEn[1] BIT
NVM NVM
NVM NVM
3.3 0
3.1 0
2.9 0
2.7 0
2.5 0, if V > 0mV
TRIMn
1, if V ≤ 0mV
TRIMn
2.3 1
2.1 1
1.9 1
1.7 1
1.5 1
1.3 1
1.1 1
0.9 1
0.7 1
0.5 1
from a resistor
VOUTn_CFG
's value over time.
VOUTn_CFG
power-up and/or every execution of
IN
V _CFG
OUTn
_CFG
nn
For more information
Table 2. VTRIMn_CFG Pin Strapping Look-Up Table for the
LTM4681's Output Voltage, Fine Adjustment Setting (Not
Applicable if MFR_CONFIG_ALL[6] = 1b) Top Resistor = 14.3k
R * V
VTRIMn_CFG TRIM
(kΩ)
Open
32.4
22.6
18.0
15.4
12.7
10.7
9.09
7.68
6.34
5.23
4.22
3.24
2.43
1.65
0.787
0
*R value indicated is nominal. Select R
VTRIMn_CFG
resistor vendor such that its value is always within 3% of the value
indicated in the table. Take into account resistor initial tolerance, T.C.R. and
resistor operating temperatures, soldering heat/IR reflow, and endurance
of the resistor over its lifetime. Thermal shock/cycling, moisture (humidity)
and other effects (depending on one's specific application) could also
affect R 's value over time. All such effects must be taken into
VTRIMn_CFG
account in order for resistor pin strapping to yield the expected result
at every SV power-up and/or every execution of MFR_RESET, or
IN_nn
RESTORE_USER_ALL over the lifetime of one's product. R
external to the part.
Example:
V
DD25
14.3k
V
TRIMn
R
TRIM
SGND_
www.analog.com
(mV) FINE ADJUSTMENT TO V
OUTn
SETTING WHEN RESPECTIVE
0
99
86.625
74.25
61.875
49.5
37.125
24.75
12.375
–12.375
–24.75
–37.125
–49.5
–61.875
–74.25
–86.625
–99
from a
VTRIMn_CFG
= 14.3k is
TOP
_CFG
_CFG BOT
nn
Rev. A