Analog Devices Linear ADI Power LTM4681 Manual page 11

ELECTRICAL CHARACTERISTICS
Note that the maximum ambient temperature consistent with these
specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified
Note 4: The two power inputs—V
power outputs—V and V
OUT0,1 OUT2,3
production. A shorthand notation is used in this document that allows
these parameters to be referred to by "V
permitted to take on a value of 0–3. This italicized, subscripted "n "
notation and convention is extended to encompass all such pin names, as
well as register names with channel-specific, i.e., paged data. For example,
VOUT_COMMANDn refers to the VOUT_COMMAND command code data
located in Pages 0 and 1, which in turn relate to channel 0,2 (V
and channel 1,3 (V ). Registers containing non-page-specific data,
OUT1,3
i.e., whose data is "global" to the module or applies to all of the module's
channels lack the italicized, subscripted "n ", e.g., FREQUENCY_SWITCH.
Note 5: V (DC) and line and load regulation tests are performed in
OUTn
production with digital servo disengaged (MFR_PWM_MODEn[6] = 0b)
and low V range selected MFR_PWM_MODEn[1] = 1b. The digital
OUTn
servo control loop is exercised in production (setting MFR_PWM_
MODEn[6] = 1b), but convergence of the output voltage to its final settling
value is not necessarily observed in final test—due to potentially long
time constants involved—and is instead guaranteed by the output voltage
readback accuracy specification. Evaluation in application demonstrates
capability; see the Typical Performance Characteristics section.
Note 6: See output current derating curves for different V
located in the Applications Information section.
Note 7: Part tested with PWM disabled. Evalution in appliction
demonstrates capability. TUE(%) = ADC Gain Error (%) + 100 (zero code
offset + ADC Linearity Error)/Actual Value.
Note 8: Minimum on-time is tested at wafer sort.
Note 9: The data conversion is done by default in round robin fashion. All
inputs signals are continuously converted for a typical latency of 90ms.
Setting MFR_ADC_CONTRL value to be 0 to 12, LTM4681 can do fast
data conversion with only 8ms to 10ms. See section PMBus Command
for details.
Note 10: The following telemetry parameters are formatted in PMBus-
defined "Linear Data Format", in which each register contains a word
comprised of 5 most significant bits—representing a signed exponent, to
be raised to the power of 2—and 11 least significant bits—representing a
signed mantissa: input voltage (on SV
command code; output currents (I
command codes; module input current (I
accessed via the READ_IIN command code; channel input currents (I
+ 1/2 • I ), accessed via the MFR_READ_IINn command codes;and
SVIN_nn
duty cycles of channel 0 and channel 1 switching power stages, accessed
via the READ_DUTY_CYCLE command codes. This data format limits the
n
resolution of telemetry readback data to 10 bits even though the internal
ADC is 16 bits and the LTM4681's internal calculations use 32-bit words.
and V —and their respective
IN01 IN23
—are tested independently in
" and "V ", where n is
INnn OUTn
OUT0,2
, V , and T
IN OUT
), accessed via the READ_VIN
IN_nn
), accessed via the READ_IOUTn
OUTn
+ I + I ),
VIN_nn VIN_nn SVIN_nn
For more information
Note 11: The absolute maximum rating for the SV
voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled
down from the SV
IN_nn
Note 12: These typical parameters are based on bench measurements and
are not production tested.
Note 13: EEPROM endurance and retention are guaranteed by wafer-level
testing for data retention. The minimum retention specification applies
for devices whose EEPROM has been cycled less than the minimum
endurance specification, and whose EEPROM data was written to at 0°C
≤ T ≤ 85°C. The RESTORE_USER_ALL or MFR_RESET is valid over
J
the entire operating temperature range and does not influence EEPROM
characteristics.
Note 14: Channel 0–3 OV/UV comparator threshold accuracy for
MFR_PWM_MODEn[1] = 0b tested in ATE at V
3.6V. 1V condition tested at IC-level only. Channel 0–3 OV/UV comparator
)
threshold accuracy for MFR_PWM_MODEn[1] = 1b tested in ATE with
V – V = 0.5V. 1.5V condition tested at IC-level only.
VOSNSn SGND
MFR_PWM_MODEn[1] = 1b is the low range.
Note 15: Tested at IC-level ATE.
Note 16: The LTM4681's EEPROM temperature range for valid write
commands is 0°C to 85°C. To achieve guaranteed EEPROM data retention,
execution of the "STORE_USER_ALL" command—i.e., uploading RAM
contents to NVM—outside this temperature range is not recommended.
However, as long as the LTM4681's EEPROM temperature is less than
130°C, the LTM4681 will obey the STORE_USER_ALL command. Only
when EEPROM temperature exceeds 130°C, the LTM4681 will not act
on any STORE_USER_ALL transactions: instead, the LTM4681 NACKs
the serial command and asserts its relevant CML (communications,
,
memory, logic) fault bits. EEPROM temperature can be queried
A
prior to commanding STORE_USER_ALL; see the Applications
Information section.
Note 17: The LTM4681 includes overtemperature protection that is
intended to protect the device during momentary overload conditions.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
62
56
50
43
37
31
25
19
VIN_nn
12
6
0
0
Figure 1. Programmable R
www.analog.com
LTM4681
pin is 18V. Input
IN_nn
pin.
+
– V
VOSNSn
5 10 15 20 25 30
CODE
4680 F01
COMPn
–
=
VOSNSn
35
Rev. A
11