Pin Functions - Analog Devices Linear ADI Power LTM4681 Manual

LTM4681

PIN FUNCTIONS

PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY .
GND (A1-A4, A7, A12, B1-B4, B7, B12, C3-C4, C7,
C12, D3-D4, D7, D12, E3-E4, E7, E12, F1-F4, F7,
F12, G3-G4, G7, G12, H3-H4, H7, H12, J3-J4, J7,
J12, K1-K4, K7-K12, L1-L15, M1-M15, N1-N4, N7-N8,
N12, P3-P4, P7, P12, R3-R4, R7, R12, T3-T4, T7, T12,
U1-U4, U7, U12, V3-V4, V7, V12, W3-W4, W7, W12,
Y3-Y4, Y7, Y12, AA1-AA4, AA7, AA12, AB1-AB4, AB7,
AB12): Power Ground of the LTM4681. Power return for
V V V and V
IN01 IN23 OUT0,1
capacitors to this point.
V (A13-A15, B13-B15, C13-C15, D13-D15, E13-
OUT0
E15): Channel 0 Output Voltage. Place recommended
output capacitors from this shape to GND. See recom-
mended layout.
+
V (J11): Channel 0 Positive Differential Voltage
OSNS0
Sense Input. Together, V
Kelvin-sense the V output voltage at V
OUT0
of load (POL) and provide the differential feedback signal
directly to channel 0's feedback loop. Command V
target regulation voltage by serial bus. Its initial command
value at SV power-up is dictated by NVM (non-volatile
IN_01
memory) contents (factory default: 1.000V)—or, option-
ally, may be set by configuration resistors; see VOUT0_
CFG, VTRIM0_CFG and the Applications Information
section.
–
V (H11): Channel 0 Negative Differential Voltage
OSNS0
+
Sense Input. See V
OSNS0
V (F13-F15, G13-G15, H13-H15, J13-J15, K13-
OUT1
K15): Channel 1 Output Voltage. Place recommended
output capacitors from this shape to GND. See recom-
mended layout.
+
V (G8): Channel 1 Positive Differential Voltage
OSNS1
Sense Input. Together, V
Kelvin-sense the V output voltage at V
OUT1
of load (POL) and provide the differential feedback signal
directly to channel 1's feedback loop. Command V
target regulation voltage by serial bus. Its initial command
value at SV power-up is dictated by NVM (non-volatile
IN_01
16
. Return input and output
OUT2,3
+ –
and V serve to
OSNS0 OSNS0
's point
OUT0
.
+ –
and V serve to
OSNS1 OSNS1
's point
OUT1
For more information
memory) contents (factory default: 1.000V)—or, option-
ally, may be set by configuration resistors; see VOUT1_
CFG, VTRIM1_CFG and the Applications Information
section.
–
V (F8): Channel 1 Negative Differential Voltage
OSNS1
Sense Input. See V
V (N13-N15, P13-P15, R13-R15, T13-T15, U13-
OUT2
U15): Channel 2 Output Voltage. Place recommended
output capacitors from this shape to GND. See recom-
mended layout.
+
V (P8): Channel 2 Positive Differential Voltage
OSNS2
Sense Input. Together, V
Kelvin-sense the V
of load (POL) and provide the differential feedback signal
directly to channel 2's feedback loop. Command V
target regulation voltage by serial bus. Its initial command
value at SV
IN_23
memory) contents (factory default: 1.000V)—or, option-
ally, may be set by configuration resistors; see VOUT2_
CFG, VTRIM2_CFG and the Applications Information
section.
's
OUT0
–
V (R8): Channel 2 Negative Differential Voltage
OSNS2
Sense Input. See V
V (V13-V15, W13-W15, Y13-Y15, AA13-AA15,
OUT3
AB13-AB15): Channel 3 Output Voltage. Place recom-
mended output capacitors from this shape to GND See
recommended layout.
+
V (R11): Channel 3 Positive Differential Voltage
OSNS3
Sense Input. Together, V
Kelvin-sense the V
of load (POL) and provide the differential feedback signal
directly to channel 3's feedback loop. Command V
target regulation voltage by serial bus. Its initial command
value at SV
IN_23
memory) contents (factory default: 1.000V)—or, option-
ally, may be set by configuration resistors; see VOUT3_
CFG, VTRIM3_CFG and the Applications Information
section.
's
OUT1
–
V (T11): Channel 3 Negative Differential Voltage
OSNS3
Sense Input. See V
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+
.
OSNS1
+
and V
OSNS2 OSNS2
output voltage at V
OUT2
power-up is dictated by NVM (non-volatile
+
.
OSNS2
+
and V
OSNS3 OSNS3
output voltage at V
OUT3
power-up is dictated by NVM (non-volatile
+
.
OSNS3
–
serve to
's point
OUT2
's
OUT2
–
serve to
's point
OUT3
's
OUT3
Rev. A