Download Print this page

Cypress CapSense CY8C20396 Specification Sheet page 25

Cypress evaluation pod specification sheet

Advertisement

AC SPI Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 31. AC SPI Specifications
Symbol
F
Maximum Input Clock Frequency Selection,
SPIM
Master 2.4V<Vdd<5.5V
Maximum Input Clock Frequency Selection,
Master
1.71V<Vdd<2.4V
(21)
F
Maximum Input Clock Frequency Selection,
SPIS
Slave 2.4<Vdd<5.5V
Maximum Input Clock Frequency Selection,
Slave 1.71V<Vdd<2.4V
T
Width of SS_ Negated Between Transmissions
SS
2
AC I
C Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 32. AC Characteristics of the I
Symbol
F
SCL Clock Frequency
SCLI2C
T
Hold Time (repeated) START Condition. After this period, the first clock pulse is
HDSTAI2C
generated.
T
LOW Period of the SCL Clock
LOWI2C
T
HIGH Period of the SCL Clock
HIGHI2C
T
Setup Time for a Repeated START Condition
SUSTAI2C
T
Data Hold Time
HDDATI2C
T
Data Setup Time
SUDATI2C
T
Setup Time for STOP Condition
SUSTOI2C
T
Bus Free Time Between a STOP and START Condition
BUFI2C
T
Pulse Width of spikes are suppressed by the input filter.
SPI2C
Figure 13. Definition for Timing for Fast/Standard Mode on the I
SDA
T
LOWI2C
SCL
T
T
S
HDDATI2C
HDSTAI2C
Note
10. A Fast-Mode I2C-bus device can be used in a Standard Mode I2C-bus system, but the requirement t
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line t
+ t
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
rmax
SU;DAT
Document Number: 001-12696 Rev. *D
Description
2
C SDA and SCL Pins
Description
T
SUDATI2C
T
T
SUSTAI2C
HIGHI2C
CY8C20x36/46/66, CY8C20396
Conditions
Output clock frequency is half
of input clock rate.
Output clock frequency is half
of input clock rate
T
HDSTAI2C
T
SUSTOI2C
Sr
≥ 250 ns must then be met. This automatically be the case
SU;DAT
Min
Typ
Max
12
6
12
6
50
Standard Mode Fast Mode
Min
Max
Min
Max
0
100
0
400
4.0
0.6
4.7
1.3
4.0
0.6
4.7
0.6
0
0
[1
250
100
0]
4.0
0.6
4.7
1.3
0
50
2
C Bus
T
SPI2C
T
BUFI2C
P
S
Page 25 of 34
Units
MHz
MHz
MHz
MHz
ns
Units
kHz
μs
μs
μs
μs
μs
ns
μs
μs
ns
[+] Feedback

Advertisement

loading
Need help?

Need help?

Do you have a question about the CapSense CY8C20396 and is the answer not in the manual?

Questions and answers

This manual is also suitable for:

Capsense cy8c20x36Capsense cy8c20x46Capsense cy8c20x66