Cypress CY91F59ACH Manuals

Manuals and User Guides for Cypress CY91F59ACH. We have 1 Cypress CY91F59ACH manual available for free PDF download: Hardware Manual

Cypress CY91F59ACH Hardware Manual

Cypress CY91F59ACH Hardware Manual (1982 pages)

Brand: Cypress | Category: Computer Hardware | Size: 27 MB

Table of Contents

Table of Contents
11
Overview
34
Overview
35
Features
36
FR81S CPU Core
37
Peripheral Functions
38
Product Line-Up
44
Function Overview
54
Block Diagram
58
Cpu
60
General-Purpose Registers
61
Dedicated Registers
62
Pin Assignment
63
Package Dimensions
68
Explanation of Pin Functions
71
Pins of each Function
98
Pins of A/D Converter
99
Pins of CAN (Ch.0 to Ch.2)
101
Pins of External Interrupt Input (Ch.0 to Ch.15)
102
Pins of LIN-UART (Ch.2 to Ch.7)
103
Pins of Multi-Function Serial Interface (Ch.0, Ch.1, Ch.8 to Ch.11)
105
Pins of PPG (Ch.0 to Ch.23)
106
Pin of Real Time Clock
108
Pins of Stepping Motor Controller (Ch.0 to Ch.5)
109
Pins of Output Compare (Ch.0 to Ch.3)
111
Pins of Input Capture (Ch.0 to Ch.11)
112
Pins of Sound Generator (Ch.0 to Ch.4)
113
Pins of Free-Run Timer (Ch.0 to Ch.7)
114
Pins of Base Timer (Ch.0, Ch.1)
115
Pins of Reload Timer (Ch.0 to Ch.3, Ch.7 to Ch.10)
116
Pins of Up/Down Counter (Ch.0 to Ch.2)
117
Pins of External Bus Interface (GDC External Memory I/F)
118
Pins of SPI Interface (GDC External Memory I/F)
120
Pins of Port Function (General-Purpose I/O)
121
Pins of GDC (Capture RGB Mode)
126
Pins of GDC (Capture 656 Mode)
127
Pins of GDC (Capture Other)
128
Pins of GDC (Display)
129
Pins of GDC (NTSC)
131
Pin of GDC (HS-SPI)
132
Pin of GDC (Other)
133
I/O Circuit Types
136
Handling the Device
142
Handling Precautions
143
Handling Device
147
Application Notes
150
Function Switching of a Multiplexed Port
151
Low-Power Consumption Mode
152
Notes When Writing Data in a Register Having the Status Flag
153
Cpu
154
Overview
155
Features
156
CPU Operating Description
158
Pipeline Operation
160
Floating Point Operation Processing
161
Data Structure
162
Addressing
163
Programming Model
164
General-Purpose Registers, Dedicated Registers, and Floating Point Registers
165
System Register
166
Reset and EIT Processing
167
Reset
168
EIT Processing
169
Vector Table
170
Memory Protection Function (MPU)
172
Overview
173
List of Registers
174
Description of Registers
175
Operations of Memory Protection Function (MPU)
192
Operation Mode
200
Overview
201
Features
202
Configuration
203
Register
204
Operation
205
MD0, MD1, MD2, P127 Pins Settings
206
Fetching the Operation Mode
207
Explanation of each Operation Mode
208
Clock
210
Overview
211
Features
213
Configuration
214
Registers
219
Division Configuration Register 0 : DIVR0 (Division Clock Configuration Register 0)
220
Division Configuration Register 1 : DIVR1 (Division Clock Configuration Register 1)
221
Division Configuration Register 2 : DIVR2 (Division Clock Configuration Register 2)
222
Clock Source Selection Register : CSELR (Clock Source Selection Register)
223
Clock Source Monitor Register : CMONR (Clock Source Monitor Register)
226
Main Timer Control Register : MTMCR (Main Clock Timer Control Register)
228
Sub Timer Control Register : STMCR (Sub Clock Timer Control Register)
231
PLL Setting Register : PLLCR (PLL Configuration Register)
234
Clock Stabilization Selection Register : CSTBR (Clock Stabilization Selection Register)
237
PLL Clock Oscillation Timer Control Register : PTMCR (PLL Clock Osc Timer Control Register)
239
PLL/SSCG Clock Selection Register : CCPSSELR (Cctl Pll/Sscg Clock Selection Register)
240
PLL/SSCG Output Clock Division Setting Register : CCPSDIVR (Cctl Pll/Sscg Clock Division Register)
241
PLL Feedback Division Setting Register : CCPLLFBR (Cctl PLL FB Clock Division Register)
243
SSCG Feedback Division Setting Register 0 : CCSSFBR0 (Cctl Sscg FB Clock Division Register 0)
244
SSCG Feedback Division Setting Register 1 : CCSSFBR1 (Cctl Sscg FB Clock Division Register 1)
245
SSCG Configuration Setting Register 0 : CCSSCCR0 (Cctl Sscg Config. Register 0)
246
SSCG Configuration Setting Register 1 : CCSSCCR1 (Cctl Sscg Config. Register 1)
248
Clock Gear Configuration Setting Register 0 : CCCGRCR0 (Cctl Clock Gear Config. Register 0)
249
Clock Gear Configuration Setting Register 1 : CCCGRCR1 (Cctl Clock Gear Config. Register 1)
251
Clock Gear Configuration Setting Register 2 : CCCGRCR2 (Cctl Clock Gear Config. Register 2)
252
RTC/PMU Clock Selection Register : CCRTSELR (Cctl Rtc Pmu Clock Selection Register)
253
PMU Clock Division Setting Register 0 : CCPMUCR0 (Cctl PMU Clock Division Register 0)
254
PMU Clock Division Setting Register 1 : CCPMUCR1 (Cctl PMU Clock Division Register 1)
255
Sync/Async Control Register : SACR (Sync/Async Control Register)
256
Peripheral Interface Clock Divider : PICD (Peripheral Interface Clock Divider)
257
GDC PLL Control Register : GPLLCR
258
GDC PLL Timer Setting Register : PTIMCR
259
GDC PLL External Division Setting Register : PEDIVCR
260
GDC PLL Multiplier Setting Register : PDIVCR
262
GDC PLL_SSCG Multiplier Setting Register 0 : SDIVCR0
263
GDC PLL_SSCG Multiplier Setting Register 1 : SDIVCR1
264
GDC PLL_SSCG Spread Spectrum Setting Register 0 : SSSCR0
265
GDC PLL_SSCG Spread Spectrum Setting Register 1 : SSSCR1
267
GDC PLL Clock Gear Setting Register 0 : PGRCR0
268
GDC PLL Clock Gear Setting Register 1 : PGRCR1
270
GDC PLL Clock Gear Setting Register 2 : PGRCR2
271
GDC PLL_SSCG Clock Gear Setting Register 0 : SGRCR0
272
GDC PLL_SSCG Clock Gear Setting Register 1: SGRCR1
274
GDC PLL _SSCG Clock Gear Setting Register 2 : SGRCR2
275
Operation
276
Oscillation Control
277
Oscillation Stabilization Wait
285
Selecting the Source Clock (SRCCLK)
289
Timer
296
Notes When Clocks Conflict
304
The Clock Gear Circuit
305
Operations During MDI Communications
308
About PMU Clock (PMUCLK)
309
GDC Clock
311
Clock Reset State Transitions
312
Overview
313
Device States and Transitions
314
Diagram of State Transitions
315
Explanation of each States
317
Priority of State Transition Requests
319
Device State and Regulator Mode Corresponding to those States
320
Reset
322
Overview
323
Features
324
Configuration
325
Registers
328
Reset Source Register : RSTRR (Reset Result Register)
329
Reset Control Register : RSTCR (Reset Control Register)
331
CPU Abnormal Operation Register : CPUAR (CPU Abnormal Operation Register)
332
PMU Status Register : PMUSTR (Power Management Unit Status Register)
334
Operation Description
335
Reset Level
336
Reset Factor
339
Reset Acceptance
350
Reset Issue
355
Reset Sequence
360
Notes
367
DMA Controller (DMAC)
368
Overview
369
Features
370
Configuration
371
Registers
372
DMA Control Register: DMACR (DMA Control Register)
375
DMA Channel Control Register 0 to 15: DCCR0 to 15 (DMA Channel Control Register 0 to 15)
377
DMA Channel Status Register 0 to 15 : DCSR0 to 15: (DMA Channel Status Register 0 to 15)
383
DMA Transfer Count Register 0 to 15 : DTCR0 to 15: (DMA Transfer Count Register 0 to 15)
385
DMA Transfer Source Register 0 to 15 : DSAR0 to 15: (DMA Source Address Register 0 to 15)
386
DMA Transfer Destination Register 0 to 15 : DDAR0 to 15 (DMA Destination Address Register 0 to 15)
388
DMA Transfer Suppression NMI Flag Register : DNMIR (DMA-Halt by NMI Register)
390
DMA Transfer Suppression Level Register : DILVR (DMA-Halt by Interrupt Level Register)
391
Operation
392
DMA Operation Enable
393
Separate Items for each Channel
394
Operations
398
DMA Usage Examples
410
Generation and Clearing of DMA Transfer Requests
412
Overview
413
Features
414
Configuration
415
Registers
416
DMA Request Clear Register 0 : ICSEL0 (Interrupt Clear Select Register 0)
417
DMA Request Clear Register 1 : ICSEL1 (Interrupt Clear Select Register 1)
418
DMA Request Clear Register 2 : ICSEL2 (Interrupt Clear Select Register 2)
419
DMA Request Clear Register 3 : ICSEL3 (Interrupt Clear Select Register 3)
420
DMA Request Clear Register 4 : ICSEL4 (Interrupt Clear Select Register 4)
421
DMA Request Clear Register 5 : ICSEL5 (Interrupt Clear Select Register 5)
422
DMA Request Clear Register 6 : ICSEL6 (Interrupt Clear Select Register 6)
423
DMA Request Clear Register 7 : ICSEL7 (Interrupt Clear Select Register 7)
424
DMA Request Clear Register 8 : ICSEL8 (Interrupt Clear Select Register 8)
425
DMA Request Clear Register 9 : ICSEL9 (Interrupt Clear Select Register 9)
426
DMA Request Clear Register 10 : ICSEL10 (Interrupt Clear Select Register 10)
427
DMA Request Clear Register 11 : ICSEL11 (Interrupt Clear Select Register 11)
428
DMA Request Clear Register 12 : ICSEL12 (Interrupt Clear Select Register 12)
429
DMA Request Clear Register 13 : ICSEL13 (Interrupt Clear Select Register 13)
430
DMA Request Clear Register 14 : ICSEL14 (Interrupt Clear Select Register 14)
431
DMA Request Clear Register 15 : ICSEL15 (Interrupt Clear Select Register 15)
432
DMA Request Clear Register 16 : ICSEL16 (Interrupt Clear Select Register 16)
433
DMA Request Clear Register 17 : ICSEL17 (Interrupt Clear Select Register 17)
434
DMA Request Clear Register 18 : ICSEL18 (Interrupt Clear Select Register 18)
435
DMA Request Clear Register 19 : ICSEL19 (Interrupt Clear Select Register 19)
436
DMA Request Clear Register 20 : ICSEL20 (Interrupt Clear Select Register 20)
437
DMA Request Clear Register 21 : ICSEL21 (Interrupt Clear Select Register 21)
438
DMA Request Clear Register 22 : ICSEL22 (Interrupt Clear Select Register 22)
439
IO Transfer Request Setting Register 0 to 15 : IORR0 to 15 (IO Triggered DMA Request Register for Ch. 0 to 15)
440
Operation
442
Configuration
443
Notes
444
Fixedvector Function
446
Overview
447
Operation Explanation
448
I/O Ports
450
Overview
451
Features
452
Configuration
453
Registers
454
Port Data Register 00 to 13, a to H : PDR00 to PDR13, PDRA to PDRH (Port Data Register 00-13,A-H)
457
Data Direction Register 00 to 13, a to H : DDR00 to DDR13, DDRA to DDRH (Data Direction Register 00-13,A-H)
459
Port Function Register 00 to 13, a to H : PFR00 to PFR13, PFRA to PFRH (Port Function Register 00-13,A-H)
461
Input Data Direct Register 00 to 13, a to H : PDDR00 to PDDR13, PDDRA to PDDRH (Port Data Direct Register 00-13,A-H)
463
Port Pull-Up/Down Control Register 00 to 13, a to H : PPCR00 to PPCR13, PPCRA to PPCRH (Port Pull-Up/Down Control Register 00-13,A-H)
465
Port Pull-Up/Down Enable Register 00 to 13, a to H : PPER00 to PPER13, PPERA to PPERH (Port Pull-Up/Down Enable Register 00-13,A-H)
467
Port Input Level Selection Register 00 to 13, a to H : PILR00 to PILR13, PILRA to PILRH (Port Input Level Register 00-13, A-H)
469
Extended Port Input Level Selection Register 06 to 13 : EPILR06 to EPILR13 (Extended Port Input Level Register 06-13)
471
Port Output Drive Register 06 to 13 : PODR06 to PODR13 (Port Output Drive Register 06-13)
472
Extended Port Output Drive Register 06 to 08 : EPODR06 to EPODR08 (Extended Port Output Drive Register 06-08)
474
Extended Port Output Drive Register for Graphic Digital Interface: EPODRGD
475
Extended Port Output Drive Register for Graphic Flash Interface: EPODRGF
476
Extended Port Function Register 00 to 58 : EPFR00 to EPFR58 (Extended Port Function Register 00-58)
478
Port Input Enable Register : PORTEN(PORT Enable Register)
510
Operation
511
Pin I/O Assignment
512
EPFR Setting Priority
520
Notes on Input I/O Relocation Setting
521
Input Interception by GPORTEN
522
Notes on Pins with the A/D Converter Function
523
Setting When Using the Base Timer TIOA1 Pin
524
Operation at Wake up from Power Shutdown
525
Notes on Switching the Port Function
526
Inputs Interception Using Dedicated Peripheral Functions
527
Interrupt Control (Interrupt Controller)
528
Overview
529
Features
530
Configuration
531
Registers
532
Interrupt Control Registers 00 to 47 : ICR00 to ICR47 (Interrupt Control Register 00 to 47)
533
Operation
534
External Interrupt Input
536
Overview
537
Features
538
Configuration
539
Registers
540
External Interrupt Factor Register 0/1 : EIRR0/EIRR1 (External Interrupt Request Register 0/1)
541
External Interrupt Enable Register 0/1 : ENIR0/ENIR1 (Enable Interrupt Request Register 0/1)
542
External Interrupt Request Level Register 0/1 : ELVR0/ELVR1 (External Interrupt Level Register 0/1)542
543
Operation
544
Setting
547
Q&A
548
Notes
549
NMI Input
550
Overview
551
Features
552
Configuration
553
Register
554
Operation
555
Usage Example
556
Delay Interrupt
558
Overview
559
Features
560
Configuration
561
Registers
562
Operation
563
Restrictions
564
Interrupt Request Batch Read
566
Overview
567
Features
568
Configuration
569
Registers
570
Interrupt Request Batch Read Register 0 Upper-Order : IRPR0H (Interrupt Request Peripheral Read Register 0H)
572
Interrupt Request Batch Read Register 0 Lower-Order : IRPR0L (Interrupt Request Peripheral Read Register 0L)
573
Interrupt Request Batch Read Register 1 Upper-Order : IRPR1H (Interrupt Request Peripheral Read Register 1H)
574
Interrupt Request Batch Read Register 1 Lower-Order : IRPR1L (Interrupt Request Peripheral Read Register 1L)
575
Interrupt Request Batch Read Register 2 Upper-Order : IRPR2H (Interrupt Request Peripheral Read Register 2H)
576
Interrupt Request Batch Read Register 2 Lower-Order : IRPR2L (Interrupt Request Peripheral Read Register 2L)
577
Interrupt Request Batch Read Register 3 Upper-Order : IRPR3H (Interrupt Request Peripheral Read Register 3H)
578
Interrupt Request Batch Read Register 3 Lower-Order : IRPR3L (Interrupt Request Peripheral Read Register 3L)
579
Interrupt Request Batch Read Register 4 Upper-Order : IRPR4H (Interrupt Request Peripheral Read Register 4H)
580
Interrupt Request Batch Read Register 4 Lower-Order : IRPR4L (Interrupt Request Peripheral Read Register 4L)
581
Interrupt Request Batch Read Register 5 Upper-Order : IRPR5H (Interrupt Request Peripheral Read Register 5H)
582
Interrupt Request Batch Read Register 5 Lower-Order : IRPR5L (Interrupt Request Peripheral Read Register 5L)
583
Interrupt Request Batch Read Register 6 Upper-Order : IRPR6H (Interrupt Request Peripheral Read Register 6H)
584
Interrupt Request Batch Read Register 6 Lower-Order : IRPR6L (Interrupt Request Peripheral Read Register 6L)
585
Interrupt Request Batch Read Register 7 Upper-Order : IRPR7H (Interrupt Request Peripheral Read Register 7H)
586
Interrupt Request Batch Read Register 7 Lower-Order : IRPR7L (Interrupt Request Peripheral Read Register 7L)
587
Interrupt Request Batch Read Register 8 Upper-Order IRPR8H (Interrupt Request Peripheral Read Register 8H)
588
Interrupt Request Batch Read Register 8 Lower-Order : IRPR8L (Interrupt Request Peripheral Read Register 8L)
589
Interrupt Request Batch Read Register 9 Upper-Order : IRPR9H (Interrupt Request Peripheral Read Register 9H)
590
Interrupt Request Batch Read Register 9 Lower-Order : IRPR9L (Interrupt Request Peripheral Read Register 9L)
591
Interrupt Request Batch Read Register 10 Upper-Order : IRPR10H (Interrupt Request Peripheral Read Register 10H)
592
Interrupt Request Batch Read Register 10 Lower-Order : IRPR10L (Interrupt Request Peripheral Read Register 10L)
593
Interrupt Request Batch Read Register 11 Upper-Order : IRPR11H (Interrupt Request Peripheral Read Register 11H)
594
Interrupt Request Batch Read Register 11 Lower-Order : IRPR11L (Interrupt Request Peripheral Read Register 11L)
595
Interrupt Request Batch Read Register 12 Upper-Order : IRPR12H (Interrupt Request Peripheral Read Register 12H)
596
Interrupt Request Batch Read Register 12 Lower-Order : IRPR12L (Interrupt Request Peripheral Read Register 12L)
597
Interrupt Request Batch Read Register 13 Upper-Order : IRPR13H (Interrupt Request Peripheral Read Register 13H)
598
Interrupt Request Batch Read Register 13 Lower-Order : IRPR13L (Interrupt Request Peripheral Read Register 13L)
599
Interrupt Request Batch Read Register 14 Upper-Order : IRPR14H (Interrupt Request Peripheral Read Register 14H)
600
Interrupt Request Batch Read Register 14 Lower-Order : IRPR14L (Interrupt Request Peripheral Read Register 14L)
601
Interrupt Request Batch Read Register 15 Upper-Order : IRPR15H (Interrupt Request Peripheral Read Register 15H)
602
Operation
603
Ppg
604
Overview
605
Features
606
Configuration
608
Registers
609
PPG Cycle Setting Register : PCSR
613
PPG Duty Setting Register : PDUT
614
PPG Control Status Register : PCN
615
General Control Register 10-13 : GCN10 to GCN13
618
General Control Register14, 15 : GCN14, GCN15
620
General Control Register 20-25 : GCN20 to GCN25
621
PPG Timer Register : PTMR
622
PPG0 Output Division Setting Register : PPGDIV
623
Operation
624
PWM Operation
625
One-Shot Operation
627
Restart Operation
629
Setting
630
Q&A
632
How to Set (Rewrite) Cycle and Duty Values
633
How to Enable/Stop PPG Operation
634
How to Set PPG Operation Mode (Pwm/One-Shot)
635
How to Restart
636
Type and Selection of Count Clock
637
How to Fix the PPG Pin Output Level
638
Type and Selection of Activation Trigger
639
How to Reverse the Output Polarity
641
How to Change a Pin to a PPG Output Pin
642
How to Generate Activation Trigger
643
How to Stop PPG Operation
644
Interrupt-Related Registers
645
Type and Selection of Interrupts
646
How to Enable/Disable/Clear Interrupt
647
Sample Programs
648
Notes
652
Watchdog Timer
654
Overview
655
Features
656
Configuration
657
Registers
658
Watchdog Control Register 0 : WDTCR0 (Watchdog Timer Configuration Register 0)
659
Watchdog Timer 0 Clear Register : WDTCPR0 (Watchdog Timer Clear Pattern Register 0)
661
Watchdog Timer 1 Cycle Information Register : WDTCR1 (Watchdog Timer Cycle Information Register 1)
662
Watchdog Timer 1 Clear Register : WDTCPR1 (Watchdog Timer Clear Pattern Register 1)
663
Operation
664
Usage Example
666
Base Timer
668
Overview
669
Features
670
16/32-Bit Reload Timer
671
16-Bit PWM Timer
672
16/32-Bit PWC Timer
673
16-Bit PPG Timer
674
Configuration
675
Registers
676
Common Registers
678
Registers for 16/32-Bit Reload Timer
689
Registers for 16-Bit PWM Timer
692
Registers for 16-Bit PPG Timer
697
16/32-Bit PWC Timer Register
701
Operation
705
Selection of Timer Function
706
I/O Allocation
707
32-Bit Mode Operation
710
16/32-Bit Reload Timer Operation
714
16-Bit PWM Timer Operation
726
16-Bit PPG Timer Operation
736
16/32-Bit PWC Timer Operation
749
Reload Timer
762
Overview
763
Features
764
Configuration
766
Registers
767
Control Status Register : TMCSR (Timer Control and Status Register)
769
16-Bit Timer Register : TMR (16Bit Timer Register)
773
16-Bit Timer Reload Register A, 16-Bit Timer Reload Register B : TMRLRA, TMRLRB
774
(16Bit Timer Reload Register A/B)
774
Operation
776
Setting
777
Operation Procedure
785
Operations of each Counter
793
Cascade Input
811
Priority of Concurrent Operations
812
Application Note
813
Single One-Shot Timer
815
Reload Timer
818
Ppg
821
Pwm
825
Pwc
829
Free-Run Timer
832
Overview
833
Features
834
Configuration
835
Registers
836
Timer Control Register (Upper Bit) : TCCSH
838
Timer Control Register (Lower Bit) : TCCSL
840
Compare Clear Register : CPCLR
842
Timer Data Register : TCDT
843
Operation
844
Count Operation of the Free-Run Timer
845
Counting up
847
Timer Clear
848
Each Clear Operations of the Free-Run Timer
849
Timer Interrupt
851
Setting
852
Q&A
853
How to Select Internal Clock Dividers
854
How to Select the External Clock
855
How to Enable/Disable the Count Operation of the Free-Run Timer
856
How to Clear the Free-Run Timer
857
About Interrupt Related Registers
858
How to Enable Compare Clear Interrupt
859
How to Stop the Free-Run Timer Operation
860
Sample Program
861
Notes
862
Output Compare
864
Overview
865
Features
866
Configuration Diagram
868
Registers
869
Free-Run Timer Selection Register : OCFS
870
Output Control Register (Upper Bit) : OCSH
871
Output Control Register (Lower Bit) : OCSL
873
Compare Register : OCCP
875
Operation
876
Output Compare Output (Independent Invert) CMOD = "0
877
Output Compare Output (Coordinated Invert) CMOD = "1
878
Output Compare Operation Timing
879
Setting
883
Q&A
884
How Can I Set the Compare Value
885
How Can I Set the Compare Mode? (Example with OCU1)
886
How Can I Enable/Disable the Compare Operation? (Example with OCU0, OCU1)
887
How Can I Set the Compare Pin Output Initial Level? (Example with OCU0, OCU1)
888
How Can I Set the Compare Pin OCU0, OCU1 for Output
889
How Can I Clear the Free-Run Timer
890
How Can I Enable the Compare Operation
891
Interrupt Related Register
892
Interrupt Type
893
How Can I Enable the Interrupt
894
Calculation Method for the Compare Value
895
Sample Program
898
Notes
900
Input Capture
902
Overview
903
Features
904
Configuration
905
Registers
906
Input Capture Data Register : IPCP
908
Free-Run Timer Selection Register : ICFS
909
Input Capture Control Register : ICS
911
LIN SYNCH FIELD Switching Register : LSYNS
913
Operation
915
Capture and Interrupt Timings
916
Edge Detection Specifications for Input Capture and Their Operations
918
Setting
920
Q&A
921
Effective Edge Polarity of External Input: Types and How to Select
922
How to Enable External Input Pins (ICU0 to ICU11)
923
About Interrupt Related Registers
924
About Interrupt Types
925
How to Enable Interrupt
926
How to Measure the Pulse Width of the Input Signal
927
Sample Program
928
Notes
929
Real-Time Clock(RTC)
930
Overview
931
Features
932
Configuration
933
Registers
934
RTC Control Register : WTCR
935
Sub-Second Register : WTBR
939
Day/Hour/Minute/Second Register : WTDR/ WTHR/ WTMR/ WTSR
940
Operation
942
Setting
944
Q&A
945
How to Set the 0.5 Second Count Interval
946
How to Initialize the Real-Time Clock
947
How to Set/Update Number of Days (Day) and Time (Hour/Minute/Second)
948
How to Start/Stop the Count of the Real-Time Clock
949
How to Confirm that the Real-Time Clock Is Running
950
How to Know the Number of Days and Time
951
How to Stop the Real-Time Clock
952
How to Calibrate the Real-Time Clock
953
What Are Interrupt Related Registers
954
What Are the Interrupt Types and How to Select Them
955
How to Enable Interrupts
956
Sample Program
957
Notes
958
RTC/WDT1 Calibration
960
Overview
961
Features
962
Configuration
963
Registers
964
Calibration Unit Control Register 0 : CUCR0 (Calibration Unit Control Register 0)
965
Sub Clock Timer Data Register : CUTD0 (Calibration Unit Timer Data Register 0)
966
Main Oscillation Timer Result Register 0 : CUTR0 (Calibration Unit Timer Result Register 0)
967
Calibration Unit Control Register 1 : CUCR1 (Calibration Unit Control Register 1)
968
CR Clock Timer Data Register : CUTD1 (Calibration Unit Timer Data Register 1)
969
Main Oscillation Timer Result Register 1 : CUTR1 (Calibration Unit Timer Result Register 1)
970
CR Oscillation Trimming Setting Register : CRTR (CR Oscillator Calibration Trimming Register)
971
Operation
972
Real-Time Clock (RTC) Calibration
973
WDT1 Calibration (CR Clock Calibration)
974
Notes
975
Power Consumption Control
976
Overview
977
Features
978
Configuration
979
Registers
981
Standby Control Register : STBCR (Standby Mode Control Register)
982
PMU Control Register : PMUCTLR (Power Management Unit Control Register)
984
Power on Timing Control Register : PWRTMCTL (Power on Timing Control Register)
985
PMU Interrupt Flag Register 0 : PMUINTF0 (Power Management Unit Interrupt Flag0 Register)
986
PMU Interrupt Flag Register 1 : PMUINTF1 (Power Management Unit Interrupt Flag1 Register)
987
PMU Interrupt Flag Register 2 : PMUINTF2 (Power Management Unit Interrupt Flag2 Register)
988
GDC Status Register : GSTR (Gdc Status Register)
990
GDC Control Register : GCTLR (Gdc Control Register)
991
Operation
992
Clock Control
993
List of Clock Supply in Low-Power Consumption Mode
994
Sleep Mode
995
Standby Mode : Watch Mode
997
Standby Mode : Watch Mode with Power-Shutdown
999
Standby Mode : Stop Mode
1003
Standby Mode : Stop Mode with Power-Shutdown
1005
Stop State of Microcontroller
1010
Power-Shutdown GDC Unit
1011
Transition to Illegal Standby Mode
1013
GDC Regulator
1014
Restrictions on Power Shutdown and Normal Standby Control
1015
Example of Use
1019
Low Voltage Detection (Internal Low-Voltage Detection)
1020
Overview
1021
Features
1022
Configuration
1023
Registers
1024
Microcontroller Unit Internal Low Voltage Detection Register : LVD (Low Voltage Detect Internal Power Fall Register)
1025
GDC Unit Internal Low Voltage Detection Register : GLVD (Gdc Low Voltage Detect Internal Power Fall Register)
1027
Operation
1029
Internal Low-Voltage Detection in Microcontroller Unit
1030
Internal Low-Voltage Detection in GDC Unit
1031
Notes
1032
Low Voltage Detection (External Low-Voltage Detection)
1034
Overview
1035
Features
1036
Configuration
1037
Registers
1038
Microcontroller Unit External Low Voltage Detection Rise Detection Register : LVD5R (Low Voltage Detect External 5V Rise Register)
1039
Microcontroller Unit External Low Voltage Detection Fall Detection Register: LVD5F (Low Voltage Detect External 5V Fall Register)
1040
GDC Unit External Low Voltage Detection Rise Detection Register: GLVD5R
1042
(Gdc Low Voltage Detect External 5V Rise Register)
1042
GDC Unit External Low Voltage Detection Fall Detection Register: GLVD5F (Gdc Low Voltage Detect External 5V Fall Register)
1044
Operation
1046
Microcontroller Unit External Low Voltage Detection
1047
GDC Unit External Low Voltage Detection
1048
Notes
1049
Wild Register
1050
Overview
1051
Features
1052
Configuration
1053
Registers
1054
Wild Register Data Enable Register: WREN (Wild Register Data Enable Register)
1056
Wild Register Address Register 00 to 15 : WRAR00 to 15 (Wild Register Address Register 00
1057
Wild Register Data Register 00 to 15 : WRDR00 to 15 (Wild Register Data Register 00 to 15)
1058
Operation
1059
Usage Example
1060
Clock Supervisor
1062
Overview
1063
Configuration
1064
Register
1065
Operation
1068
Initial State
1069
Stopping CR Oscillator and the Clock Supervisor Function
1070
Re-Enabling the Clock Supervisor
1071
Sub Clock Mode
1072
Stop Mode
1073
Watch Mode
1074
Checking the Reset Factor Using the Clock Supervisor
1075
Return from CR Clock
1076
Sound Generator
1078
Overview
1079
Features
1080
Configuration
1081
Registers
1082
DMA Transfer Update Enable Register: SGDE (SG DMA Enable Register)
1084
Sound Control Register: SGCR (SG Control Register)
1086
Amplitude Data Register : SGAR (SG Amplitude Register)
1089
Frequency Data Register : SGFR (SG Frequency Register)
1090
Tone Outputs Number Register : SGNR (SG Tone Number Register)
1091
Cycle Register: SGTCR (SG Tone Cycle Register)
1092
Increment Decrement Data Register: SGIDR (SG Increment Decrement Register)
1093
PWM Cycles Number Data Register: SGPCR (SG PWM Cycle Register)
1094
DMA Transfer Indirect Register : SGDMAR (SG DMA Register)
1095
Operation
1096
Relation of Amplitude Data Register (SGAR) and PWM Pulse
1097
Relation of Frequency Data Register (SGFR) and Tone Pulse Signals
1098
Relation of PWM Cycles Number Data Register (SGPCR) and PWM Cycle
1099
Relation of DMA Transfer Update Enable Register (SGDER) and DMA Transfers Count/Dma Transfer Size/Transfer Byte Location
1100
Operation of Sound Generator
1107
Sound Generator Continuous Operation by CPU
1110
Sound Generator Operation Coordinated with DMA
1112
When DMA Transfer of 4 Bytes × 2 Is Performed N Times
1113
Stepping Motor Controller
1126
Overview
1127
Features
1128
Configuration
1129
Registers
1130
PWM Control Register: PWC
1132
PWM1&2 Compare Register : PWC1/PWC2
1134
PWM1 Selection Register : PWS1
1135
PWM2 Selection Register : PWS2
1136
Operation
1137
PWM Operation
1138
PWM Compare Register Loading with the BS Bit
1140
Selection of Motor Drive Signals
1142
Setting
1143
Q&A
1144
How to Set Cycle and Duty
1145
How to Enable/Stop PWM Operation
1146
How to Reflect the Duty Change
1147
Type and Selection of Operating Clock
1148
How to Change the Motor Drive Signals
1149
How to Assign a Pin as a PWM Output Pin Is Shown below
1150
How to Assign a Pin as an A/D Converter Analog Input Pin
1151
Sample Programs
1152
Notes
1153
Regulator Control
1154
Overview
1155
Features
1156
Configuration
1157
Register
1158
Regulator Output Voltage Select Register : REGSEL (Regulator Output Voltage Select Register)
1159
Operation
1161
Bus Performance Counters
1162
Overview
1163
Features
1164
Configuration
1165
Registers
1166
BPC-A Control Register : BPCCRA (Bus Performance Counter Control Register A)
1167
BPC-B Control Register : BPCCRB (Bus Performance Counter Control Register B)
1169
BPC-C Control Register : BPCCRC (Bus Performance Counter Control Register C)
1170
BPC-A Count Register : BPCTRA (Bus Performance Counter Register A)
1171
BPC-B Count Register : BPCTRB (Bus Performance Counter Register B)
1172
BPC-C Count Register : BPCTRC (Bus Performance Counter Register C)
1173
Operations
1174
Setting
1175
Starting and Stopping
1177
Operation
1178
Measurement and Result Processing
1179
Crc
1182
Overview
1183
Features
1184
Configuration
1185
Registers
1186
CRC Control Register : CRCCR
1187
CRC Initial Value Register : CRCINIT
1188
CRC Input Data Register : CRCIN
1189
CRC Register : CRCR
1190
Operation
1191
CRC Definition
1192
Reset Operation
1193
Initialization
1194
Byte and Bit Orders
1195
CRC Calculation Sequence
1196
Examples
1197
Ramecc
1204
Overview
1205
Features
1206
Configuration
1207
Registers
1210
ECC Error Control Register XBS RAM : EECSRX (Ecc Error Control and Status Register Xbs Ram)
1211
Single-Bit ECC Error Address Register XBS RAM : SEEARX (Single Bit Ecc Error Address Register Xbs Ram)
1212
Double-Bit ECC Error Address Register XBS RAM : DEEARX (Double Bit Ecc Error Address Register Xbs Ram)
1213
ECC False Error Generation Address Register XBS RAM : EFEARX (Ecc False Error Address Register Xbs Ram)
1214
ECC False Error Generation Control Register XBS RAM : EFECRX ( Ecc False Error Control Register Xbs Ram)
1215
ECC Error Control Register AHB RAM : EECSRH (Ecc Error Control and Status Register Ahb Ram)
1217
Single-Bit ECC Error Address Register ABS RAM : SEEARH (Single Bit Ecc Error Address Register Ahb Ram)
1218
Double-Bit ECC Error Address Register AHB RAM : DEEARH (Double Bit Ecc Error Address Register Ahb Ram)
1219
ECC False Error Generation Address Register AHB RAM : EFEARH (Ecc False Error Address Register Ahb Ram)
1220
ECC False Error Generation Control Register AHB RAM : EFECRH ( Ecc False Error Control Register Ahb Ram)
1221
ECC Error Control Register BACKUP-RAM : EECSRA (Ecc Error Control and Status Register Backup-Ram)
1223
Single-Bit ECC Error Address Register BACKUP-RAM : SEEARA (Single Bit Ecc Error Address Register Backup-Ram)
1224
Double-Bit ECC Error Address Register BACKUP-RAM : DEEARA (Double Bit Ecc Error Address Register Backup-Ram)
1225
ECC False Error Generation Address Register BACKUP-RAM : EFEARA (Ecc False Error Address Register Backup-RAM)
1226
ECC False Error Generation Control Register BACKUP-RAM : EFECRA (Ecc False Error Control Register Backup-RAM)
1227
Operation
1229
ECC Generation
1230
ECC Inspection
1231
Interrupt by Error Detection
1232
Test Function
1233
Multi-Function Serial Interface
1234
Overview
1235
Features
1236
Uart
1237
Csio
1239
Lin-Uart
1240
I 2 C
1242
Note
1244
Configuration
1245
Registers
1249
Common Registers
1254
Registers for UART
1265
Registers for CSIO
1276
Registers for LIN-UART
1285
Registers for I C
1296
Operation of UART
1312
Interrupt of UART
1313
Operation of UART
1321
Setup Procedure and Program Flow
1337
Operation of CSIO
1343
Interrupts of CSIO
1344
Operation of CSIO
1351
Setup Procedure and Program Flow
1372
Operation of LIN-UART
1376
Interrupts of LIN-UART
1377
Operation of LIN-UART
1387
Setup Procedure and Program Flow
1402
Operation of I C
1408
Interrupts of I C
1409
Operation for I C Interface Communication
1411
I C Master Mode
1418
I C Slave Mode
1457
Bus Error
1467
Example of I C Flowchart
1470
Lin-Uart
1478
Overview
1479
Features
1480
Functions
1481
Operation Mode
1483
Configuration
1484
Block Diagram of the LIN-UART
1485
Explanation of each Block
1487
Registers
1506
Serial Control Register : SCR
1508
Serial Mode Register : SMR
1511
Serial Status Register :SSR
1514
Reception Data Register / Transmission Data Register : RDR / TDR
1517
Extended Status Control Register : ESCR
1520
Extended Communication Control Register : ECCR
1523
Baud Rate Generator Register : BGR
1525
Interrupts
1526
Overview
1527
Generation of Reception Interrupt and Flag Setting Timing
1533
Occurrence of Transmission Interrupt and Flag Timing
1536
Baud Rates
1539
Selection of Baud Rates
1540
Baud Rate Setting
1544
Reload Counter
1550
Operation
1556
Overview
1557
Asynchronous Mode (Operation Modes 0 and 1)
1565
Synchronous Mode (Operation Mode 2)
1575
LIN Mode (Operation Mode 3)
1590
Direct Access to the Serial Pin
1600
Bidirectional Communication Function (Normal Mode)
1601
Master/ Slave Mode Communication Function (Multi-Processor Mode)
1604
LIN Communication Function
1608
LIN-UART Sample Flowchart in LIN Communication Mode (Operation Mode 3)
1611
Notes on Usage
1614
Operation Enable
1615
Communication Mode Setting
1616
Timing of Enabling Transmission Interrupt
1617
Operation Setting Change
1618
Detection of a LIN Synch Break
1619
LIN Slave Setting
1620
Program Compatibility
1621
Address/Data Format Selection Bit (SCR:AD)
1622
LIN-UART Software Reset
1623
Detection of LIN Synch Field in Input Capture
1624
Bus Idle Detection
1625
Notes on DMAC Linkage Operation
1626
Transmission Operation
1627
Reception Operation
1628
Can
1630
Overview
1631
Features
1632
Configuration
1633
Registers
1634
Overview
1635
Overall Control Registers
1643
Message Interface Register
1656
Message Object
1667
Message Handler Registers
1674
CAN Prescaler Register (CANPRE)
1683
Operation
1685
Message Object
1686
Message Transmission Operation
1689
Message Reception Operation
1694
FIFO Buffer Function
1701
Interrupt Function
1706
Bit Timing and CAN System Clock (Fsys) Generation
1707
Test Mode
1710
Software Initialization
1717
Limitations
1718
INIT Bit
1719
A/D Converter
1722
Overview
1723
Features
1724
Configuration
1725
Registers
1726
Analog Input Enable Register : ADER
1727
A/D Control Status Register (Upper) : ADCS1
1729
A/D Control Status Register (Lower) : ADCS0
1732
Data Register : ADCR0, ADCR1
1735
Conversion Time Setting Register: ADCT
1736
A/D Start/Completion Channel Setting Register : ADSCH, ADECH
1738
Operation
1741
Single Conversion Operation
1742
Scan Conversion Operation
1743
Conversion Mode
1744
Setting
1745
Q&A
1747
Conversion Mode Type and Setting Method
1748
How Can I Specify the Bit Length
1749
How Can I Select Channels
1750
How Can I Set the Conversion Time
1753
How Can I Enable the Analog Pin Input
1754
How Can I Select the A/D Converter Activation Method
1756
How Can I Activate the A/D Converter
1757
How Can I Check the Conversion Completion
1758
How Can I Read the Conversion Value
1759
How Can I Stop the A/D Conversion Operation Forcibly
1760
Interrupt-Related Register
1761
Interrupt Type
1762
How Can I Enable/Disable/Clear the Interrupt
1763
Sample Program
1764
Notes
1767
Term Definition for A/D Converter
1768
Flash Memory
1772
Overview
1773
Features
1774
Configuration
1776
Block Diagram
1777
Sector Configuration Diagram
1778
Sector Number and Flash Macro Number Correspondence Chart
1783
Registers
1785
Flash Control Register: FCTLR (Flash Control Register)
1786
Flash Status Register : FSTR (Flash Status Register)
1789
Flash Interface Control Register : FLIFCTLR(Flash I/F Control Register)
1791
Flash I/F Feature Extension Register 1: FLIFFER1
1792
Flash I/F Feature Extension Register 2: FLIFFER2
1793
Operation
1794
Access Mode Setting
1795
Programming Flash Memory by CPU
1796
Automatic Algorithm
1797
Reset Command
1805
Write Command
1806
Chip Erase Command
1809
Sector Erase Command
1810
Sector Erase Suspend Command
1813
Security Function
1814
Notes on Using Flash Memory
1819
Workflash Memory
1820
Overview
1821
Features
1822
Configuration
1823
Block Diagram
1824
Sector Configuration Diagram
1825
Registers
1826
Workflash Control Register : DFCTLR (Workflash Control Register)
1827
Workflash Status Register : DFSTR (Workflash Status Register)
1828
Flash Interface Control Register : FLIFCTLR (Flash I/F Control Register)
1829
Operation
1830
Access Mode Setting
1831
Writing Flash Memory by CPU
1834
Automatic Algorithm
1835
Reset Command
1843
Write Command
1844
Chip Erase Command
1847
Sector Erase Command
1848
Sector Erase Suspend Command
1851
Security Function
1852
Notes on Using Flash Memory
1857
On Chip Debugger (OCD)
1858
Overview
1859
Features
1860
Configuration
1862
DEBUG I/F Clock
1864
Registers
1867
DBG Register
1868
User IO Register
1869
Operation
1870
OCDU Operating Mode
1871
Overview of DEBUG I/F
1874
Specification Restrictions at Connection to OCD Tool of this Series
1878
OCD-DSU ID Code and Mount Type Information on this Series
1887
GDC External Control
1888
Overview
1889
Features
1890
Configuration
1891
Registers
1892
GDC Control Register : GDCCR
1893
GDC Trigger Register : GDCTRGR
1895
GDC Swap Setting Register : GDCSWPR
1896
Note
1898
Up/Down Counter
1900
Overview
1901
Features
1902
Configuration
1904
Registers
1906
Reload Compare Register (RCR0, RCR1)
1908
Up/Down Count Register (UDCR0, UDCR1)
1909
Counter Control Register (CCR0, CCR1)
1910
Counter Status Register (CSR0, CSR1)
1915
Interrupt
1918
Operation and Setting Procedure Examples
1920
Operation in Timer Mode
1924
Operation in Up/Down Count Mode
1926
Operation in the Phase Difference Count Mode (Multiply-By-Two)
1929
Operation in the Phase Difference Count Mode (Multiply-By-Four)
1931
Appendix
1934
Memory Map
1935
I/O Map
1941
List of Interrupt Vector
1976
Pin Status in CPU Status
1979
JTAG Boundary Scan Test
1980
Revision History
1982
Document Revision History
1982

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